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drm/panel/panel-ilitek-ili9806e: Add Densitron DMT028VGHMCMI-1D TFT to ILI9806E DSI TCON driver

Add Densitron DMT028VGHMCMI-1D 480x640 TFT matrix 2.83 inch panel
attached to Ilitek ILI9806E DSI TCON into the ILI9806E driver.

Note that the Densitron panels use different TCONs, this driver is for
the later panel, use panel-ilitek-st7701.c for the former panel:
DMT028VGHMCMI-1A - ST7701
DMT028VGHMCMI-1D - ILI9806E

Signed-off-by: Marek Vasut <marex@denx.de>
Reviewed-by: Michael Walle <mwalle@kernel.org>
Link: https://lore.kernel.org/r/20240724005700.196073-2-marex@denx.de
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://patchwork.freedesktop.org/patch/msgid/20240724005700.196073-2-marex@denx.de

authored by

Marek Vasut and committed by
Neil Armstrong 2108cdce aa48c30f

+165
+165
drivers/gpu/drm/panel/panel-ilitek-ili9806e.c
··· 380 380 .lanes = 2, 381 381 }; 382 382 383 + static void dmt028vghmcmi_1d_init(struct mipi_dsi_multi_context *ctx) 384 + { 385 + mipi_dsi_dcs_write_seq_multi(ctx, 0xff, 0xff, 0x98, 0x06, 0x04, 0x01); 386 + mipi_dsi_dcs_write_seq_multi(ctx, 0x08, 0x10); 387 + mipi_dsi_dcs_write_seq_multi(ctx, 0x21, 0x01); 388 + mipi_dsi_dcs_write_seq_multi(ctx, 0x30, 0x03); 389 + mipi_dsi_dcs_write_seq_multi(ctx, 0x31, 0x00); 390 + mipi_dsi_dcs_write_seq_multi(ctx, 0x60, 0x06); 391 + mipi_dsi_dcs_write_seq_multi(ctx, 0x61, 0x00); 392 + mipi_dsi_dcs_write_seq_multi(ctx, 0x62, 0x07); 393 + mipi_dsi_dcs_write_seq_multi(ctx, 0x63, 0x00); 394 + mipi_dsi_dcs_write_seq_multi(ctx, 0x40, 0x16); 395 + mipi_dsi_dcs_write_seq_multi(ctx, 0x41, 0x44); 396 + mipi_dsi_dcs_write_seq_multi(ctx, 0x42, 0x00); 397 + mipi_dsi_dcs_write_seq_multi(ctx, 0x43, 0x83); 398 + mipi_dsi_dcs_write_seq_multi(ctx, 0x44, 0x89); 399 + mipi_dsi_dcs_write_seq_multi(ctx, 0x45, 0x8a); 400 + mipi_dsi_dcs_write_seq_multi(ctx, 0x46, 0x44); 401 + mipi_dsi_dcs_write_seq_multi(ctx, 0x47, 0x44); 402 + mipi_dsi_dcs_write_seq_multi(ctx, 0x50, 0x78); 403 + mipi_dsi_dcs_write_seq_multi(ctx, 0x51, 0x78); 404 + mipi_dsi_dcs_write_seq_multi(ctx, 0x52, 0x00); 405 + mipi_dsi_dcs_write_seq_multi(ctx, 0x53, 0x6c); 406 + mipi_dsi_dcs_write_seq_multi(ctx, 0x54, 0x00); 407 + mipi_dsi_dcs_write_seq_multi(ctx, 0x55, 0x6c); 408 + mipi_dsi_dcs_write_seq_multi(ctx, 0x56, 0x00); 409 + /* Gamma settings */ 410 + mipi_dsi_dcs_write_seq_multi(ctx, 0xa0, 0x00); 411 + mipi_dsi_dcs_write_seq_multi(ctx, 0xa1, 0x09); 412 + mipi_dsi_dcs_write_seq_multi(ctx, 0xa2, 0x14); 413 + mipi_dsi_dcs_write_seq_multi(ctx, 0xa3, 0x09); 414 + mipi_dsi_dcs_write_seq_multi(ctx, 0xa4, 0x05); 415 + mipi_dsi_dcs_write_seq_multi(ctx, 0xa5, 0x0a); 416 + mipi_dsi_dcs_write_seq_multi(ctx, 0xa6, 0x07); 417 + mipi_dsi_dcs_write_seq_multi(ctx, 0xa7, 0x07); 418 + mipi_dsi_dcs_write_seq_multi(ctx, 0xa8, 0x08); 419 + mipi_dsi_dcs_write_seq_multi(ctx, 0xa9, 0x0b); 420 + mipi_dsi_dcs_write_seq_multi(ctx, 0xaa, 0x0c); 421 + mipi_dsi_dcs_write_seq_multi(ctx, 0xab, 0x05); 422 + mipi_dsi_dcs_write_seq_multi(ctx, 0xac, 0x0a); 423 + mipi_dsi_dcs_write_seq_multi(ctx, 0xad, 0x19); 424 + mipi_dsi_dcs_write_seq_multi(ctx, 0xae, 0x0b); 425 + mipi_dsi_dcs_write_seq_multi(ctx, 0xaf, 0x00); 426 + 427 + mipi_dsi_dcs_write_seq_multi(ctx, 0xc0, 0x00); 428 + mipi_dsi_dcs_write_seq_multi(ctx, 0xc1, 0x0c); 429 + mipi_dsi_dcs_write_seq_multi(ctx, 0xc2, 0x14); 430 + mipi_dsi_dcs_write_seq_multi(ctx, 0xc3, 0x11); 431 + mipi_dsi_dcs_write_seq_multi(ctx, 0xc4, 0x05); 432 + mipi_dsi_dcs_write_seq_multi(ctx, 0xc5, 0x0c); 433 + mipi_dsi_dcs_write_seq_multi(ctx, 0xc6, 0x08); 434 + mipi_dsi_dcs_write_seq_multi(ctx, 0xc7, 0x03); 435 + mipi_dsi_dcs_write_seq_multi(ctx, 0xc8, 0x06); 436 + mipi_dsi_dcs_write_seq_multi(ctx, 0xc9, 0x0a); 437 + mipi_dsi_dcs_write_seq_multi(ctx, 0xca, 0x10); 438 + mipi_dsi_dcs_write_seq_multi(ctx, 0xcb, 0x05); 439 + mipi_dsi_dcs_write_seq_multi(ctx, 0xcc, 0x0d); 440 + mipi_dsi_dcs_write_seq_multi(ctx, 0xcd, 0x15); 441 + mipi_dsi_dcs_write_seq_multi(ctx, 0xce, 0x13); 442 + mipi_dsi_dcs_write_seq_multi(ctx, 0xcf, 0x00); 443 + 444 + mipi_dsi_dcs_write_seq_multi(ctx, 0xff, 0xff, 0x98, 0x06, 0x04, 0x07); 445 + mipi_dsi_dcs_write_seq_multi(ctx, 0x17, 0x22); 446 + mipi_dsi_dcs_write_seq_multi(ctx, 0x18, 0x1d); 447 + mipi_dsi_dcs_write_seq_multi(ctx, 0x02, 0x77); 448 + mipi_dsi_dcs_write_seq_multi(ctx, 0xe1, 0x79); 449 + mipi_dsi_dcs_write_seq_multi(ctx, 0x06, 0x13); 450 + 451 + mipi_dsi_dcs_write_seq_multi(ctx, 0xff, 0xff, 0x98, 0x06, 0x04, 0x06); 452 + /* GIP 0 */ 453 + mipi_dsi_dcs_write_seq_multi(ctx, 0x00, 0x21); 454 + mipi_dsi_dcs_write_seq_multi(ctx, 0x01, 0x0a); 455 + mipi_dsi_dcs_write_seq_multi(ctx, 0x02, 0x00); 456 + mipi_dsi_dcs_write_seq_multi(ctx, 0x03, 0x05); 457 + mipi_dsi_dcs_write_seq_multi(ctx, 0x04, 0x01); 458 + mipi_dsi_dcs_write_seq_multi(ctx, 0x05, 0x01); 459 + mipi_dsi_dcs_write_seq_multi(ctx, 0x06, 0x98); 460 + mipi_dsi_dcs_write_seq_multi(ctx, 0x07, 0x06); 461 + mipi_dsi_dcs_write_seq_multi(ctx, 0x08, 0x01); 462 + mipi_dsi_dcs_write_seq_multi(ctx, 0x09, 0x00); 463 + mipi_dsi_dcs_write_seq_multi(ctx, 0x0a, 0x00); 464 + mipi_dsi_dcs_write_seq_multi(ctx, 0x0b, 0x00); 465 + mipi_dsi_dcs_write_seq_multi(ctx, 0x0c, 0x01); 466 + mipi_dsi_dcs_write_seq_multi(ctx, 0x0d, 0x01); 467 + mipi_dsi_dcs_write_seq_multi(ctx, 0x0e, 0x00); 468 + mipi_dsi_dcs_write_seq_multi(ctx, 0x0f, 0x00); 469 + mipi_dsi_dcs_write_seq_multi(ctx, 0x10, 0xf7); 470 + mipi_dsi_dcs_write_seq_multi(ctx, 0x11, 0xf0); 471 + mipi_dsi_dcs_write_seq_multi(ctx, 0x12, 0x00); 472 + mipi_dsi_dcs_write_seq_multi(ctx, 0x13, 0x00); 473 + mipi_dsi_dcs_write_seq_multi(ctx, 0x14, 0x00); 474 + mipi_dsi_dcs_write_seq_multi(ctx, 0x15, 0xc0); 475 + mipi_dsi_dcs_write_seq_multi(ctx, 0x16, 0x08); 476 + mipi_dsi_dcs_write_seq_multi(ctx, 0x17, 0x00); 477 + mipi_dsi_dcs_write_seq_multi(ctx, 0x18, 0x00); 478 + mipi_dsi_dcs_write_seq_multi(ctx, 0x19, 0x00); 479 + mipi_dsi_dcs_write_seq_multi(ctx, 0x1a, 0x00); 480 + mipi_dsi_dcs_write_seq_multi(ctx, 0x1b, 0x00); 481 + mipi_dsi_dcs_write_seq_multi(ctx, 0x1c, 0x00); 482 + mipi_dsi_dcs_write_seq_multi(ctx, 0x1d, 0x00); 483 + /* GIP 1 */ 484 + mipi_dsi_dcs_write_seq_multi(ctx, 0x20, 0x01); 485 + mipi_dsi_dcs_write_seq_multi(ctx, 0x21, 0x23); 486 + mipi_dsi_dcs_write_seq_multi(ctx, 0x22, 0x44); 487 + mipi_dsi_dcs_write_seq_multi(ctx, 0x23, 0x67); 488 + mipi_dsi_dcs_write_seq_multi(ctx, 0x24, 0x01); 489 + mipi_dsi_dcs_write_seq_multi(ctx, 0x25, 0x23); 490 + mipi_dsi_dcs_write_seq_multi(ctx, 0x26, 0x45); 491 + mipi_dsi_dcs_write_seq_multi(ctx, 0x27, 0x67); 492 + /* GIP 2 */ 493 + mipi_dsi_dcs_write_seq_multi(ctx, 0x30, 0x01); 494 + mipi_dsi_dcs_write_seq_multi(ctx, 0x31, 0x22); 495 + mipi_dsi_dcs_write_seq_multi(ctx, 0x32, 0x22); 496 + mipi_dsi_dcs_write_seq_multi(ctx, 0x33, 0xbc); 497 + mipi_dsi_dcs_write_seq_multi(ctx, 0x34, 0xad); 498 + mipi_dsi_dcs_write_seq_multi(ctx, 0x35, 0xda); 499 + mipi_dsi_dcs_write_seq_multi(ctx, 0x36, 0xcb); 500 + mipi_dsi_dcs_write_seq_multi(ctx, 0x37, 0x22); 501 + mipi_dsi_dcs_write_seq_multi(ctx, 0x38, 0x55); 502 + mipi_dsi_dcs_write_seq_multi(ctx, 0x39, 0x76); 503 + mipi_dsi_dcs_write_seq_multi(ctx, 0x3a, 0x67); 504 + mipi_dsi_dcs_write_seq_multi(ctx, 0x3b, 0x88); 505 + mipi_dsi_dcs_write_seq_multi(ctx, 0x3c, 0x22); 506 + mipi_dsi_dcs_write_seq_multi(ctx, 0x3d, 0x11); 507 + mipi_dsi_dcs_write_seq_multi(ctx, 0x3e, 0x00); 508 + mipi_dsi_dcs_write_seq_multi(ctx, 0x3f, 0x22); 509 + mipi_dsi_dcs_write_seq_multi(ctx, 0x40, 0x22); 510 + 511 + mipi_dsi_dcs_write_seq_multi(ctx, 0x52, 0x10); 512 + mipi_dsi_dcs_write_seq_multi(ctx, 0x53, 0x10); 513 + mipi_dsi_dcs_write_seq_multi(ctx, 0x54, 0x13); 514 + 515 + mipi_dsi_dcs_write_seq_multi(ctx, 0xff, 0xff, 0x98, 0x06, 0x04, 0x00); 516 + }; 517 + 518 + static const struct drm_display_mode dmt028vghmcmi_1d_default_mode = { 519 + .clock = 22000, 520 + 521 + .hdisplay = 480, 522 + .hsync_start = 480 + 20, 523 + .hsync_end = 480 + 20 + 4, 524 + .htotal = 480 + 20 + 4 + 10, 525 + 526 + .vdisplay = 640, 527 + .vsync_start = 640 + 40, 528 + .vsync_end = 640 + 40 + 4, 529 + .vtotal = 640 + 40 + 4 + 20, 530 + 531 + .width_mm = 53, 532 + .height_mm = 79, 533 + 534 + .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 535 + .type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED, 536 + }; 537 + 538 + static const struct panel_desc dmt028vghmcmi_1d_desc = { 539 + .init_sequence = dmt028vghmcmi_1d_init, 540 + .display_mode = &dmt028vghmcmi_1d_default_mode, 541 + .mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | 542 + MIPI_DSI_MODE_LPM | MIPI_DSI_CLOCK_NON_CONTINUOUS, 543 + .format = MIPI_DSI_FMT_RGB888, 544 + .lanes = 2, 545 + }; 546 + 383 547 static const struct of_device_id ili9806e_of_match[] = { 548 + { .compatible = "densitron,dmt028vghmcmi-1d", .data = &dmt028vghmcmi_1d_desc }, 384 549 { .compatible = "ortustech,com35h3p70ulc", .data = &com35h3p70ulc_desc }, 385 550 { } 386 551 };