drm/msm/a6xx: Enable preemption for tested a7xx targets

Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git

kernel os linux

Initialize with 4 rings to enable preemption.

Add the "preemption_enabled" module parameter to override this.

Tested-by: Rob Clark <robdclark@gmail.com>
Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8650-QRD
Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8550-QRD
Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8450-HDK
Signed-off-by: Antonino Maniscalco <antomani103@gmail.com>
Patchwork: https://patchwork.freedesktop.org/patch/618029/
Signed-off-by: Rob Clark <robdclark@chromium.org>

authored by

Antonino Maniscalco and committed by

Rob Clark 2 years ago 20f33275 7788d320

+23 -6

5 changed files

expand all

drivers

gpu

drm

msm

adreno

a6xx_catalog.c

a6xx_gpu.c

adreno_device.c

adreno_gpu.h

msm_submitqueue.c

+8 -4

drivers/gpu/drm/msm/adreno/a6xx_catalog.c

··· 1337 1337 .gmem = SZ_2M, 1338 1338 .inactive_period = DRM_MSM_INACTIVE_PERIOD, 1339 1339 .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT | 1340 - ADRENO_QUIRK_HAS_HW_APRIV, 1340 + ADRENO_QUIRK_HAS_HW_APRIV | 1341 + ADRENO_QUIRK_PREEMPTION, 1341 1342 .init = a6xx_gpu_init, 1342 1343 .zapfw = "a730_zap.mdt", 1343 1344 .a6xx = &(const struct a6xx_info) { ··· 1359 1358 .gmem = 3 * SZ_1M, 1360 1359 .inactive_period = DRM_MSM_INACTIVE_PERIOD, 1361 1360 .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT | 1362 - ADRENO_QUIRK_HAS_HW_APRIV, 1361 + ADRENO_QUIRK_HAS_HW_APRIV | 1362 + ADRENO_QUIRK_PREEMPTION, 1363 1363 .init = a6xx_gpu_init, 1364 1364 .zapfw = "a740_zap.mdt", 1365 1365 .a6xx = &(const struct a6xx_info) { ··· 1382 1380 .gmem = 3 * SZ_1M, 1383 1381 .inactive_period = DRM_MSM_INACTIVE_PERIOD, 1384 1382 .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT | 1385 - ADRENO_QUIRK_HAS_HW_APRIV, 1383 + ADRENO_QUIRK_HAS_HW_APRIV | 1384 + ADRENO_QUIRK_PREEMPTION, 1386 1385 .init = a6xx_gpu_init, 1387 1386 .a6xx = &(const struct a6xx_info) { 1388 1387 .hwcg = a740_hwcg, ··· 1404 1401 .gmem = 3 * SZ_1M, 1405 1402 .inactive_period = DRM_MSM_INACTIVE_PERIOD, 1406 1403 .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT | 1407 - ADRENO_QUIRK_HAS_HW_APRIV, 1404 + ADRENO_QUIRK_HAS_HW_APRIV | 1405 + ADRENO_QUIRK_PREEMPTION, 1408 1406 .init = a6xx_gpu_init, 1409 1407 .zapfw = "gen70900_zap.mbn", 1410 1408 .a6xx = &(const struct a6xx_info) {

+5 -1

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

··· 2436 2436 struct a6xx_gpu *a6xx_gpu; 2437 2437 struct adreno_gpu *adreno_gpu; 2438 2438 struct msm_gpu *gpu; 2439 + extern int enable_preemption; 2439 2440 bool is_a7xx; 2440 2441 int ret; 2441 2442 ··· 2475 2474 return ERR_PTR(ret); 2476 2475 } 2477 2476 2478 - if (is_a7xx) 2477 + if ((enable_preemption == 1) || (enable_preemption == -1 && 2478 + (config->info->quirks & ADRENO_QUIRK_PREEMPTION))) 2479 + ret = adreno_gpu_init(dev, pdev, adreno_gpu, &funcs_a7xx, 4); 2480 + else if (is_a7xx) 2479 2481 ret = adreno_gpu_init(dev, pdev, adreno_gpu, &funcs_a7xx, 1); 2480 2482 else if (adreno_has_gmu_wrapper(adreno_gpu)) 2481 2483 ret = adreno_gpu_init(dev, pdev, adreno_gpu, &funcs_gmuwrapper, 1);

drivers/gpu/drm/msm/adreno/adreno_device.c

··· 20 20 MODULE_PARM_DESC(allow_vram_carveout, "Allow using VRAM Carveout, in place of IOMMU"); 21 21 module_param_named(allow_vram_carveout, allow_vram_carveout, bool, 0600); 22 22 23 + int enable_preemption = -1; 24 + MODULE_PARM_DESC(enable_preemption, "Enable preemption (A7xx only) (1=on , 0=disable, -1=auto (default))"); 25 + module_param(enable_preemption, int, 0600); 26 + 23 27 extern const struct adreno_gpulist a2xx_gpulist; 24 28 extern const struct adreno_gpulist a3xx_gpulist; 25 29 extern const struct adreno_gpulist a4xx_gpulist;

drivers/gpu/drm/msm/adreno/adreno_gpu.h

··· 56 56 #define ADRENO_QUIRK_LMLOADKILL_DISABLE BIT(2) 57 57 #define ADRENO_QUIRK_HAS_HW_APRIV BIT(3) 58 58 #define ADRENO_QUIRK_HAS_CACHED_COHERENT BIT(4) 59 + #define ADRENO_QUIRK_PREEMPTION BIT(5) 59 60 60 61 /* Helper for formating the chip_id in the way that userspace tools like 61 62 * crashdec expect.

+5 -1

drivers/gpu/drm/msm/msm_submitqueue.c

··· 161 161 struct msm_drm_private *priv = drm->dev_private; 162 162 struct msm_gpu_submitqueue *queue; 163 163 enum drm_sched_priority sched_prio; 164 + extern int enable_preemption; 165 + bool preemption_supported; 164 166 unsigned ring_nr; 165 167 int ret; 166 168 ··· 172 170 if (!priv->gpu) 173 171 return -ENODEV; 174 172 175 - if (flags & MSM_SUBMITQUEUE_ALLOW_PREEMPT && priv->gpu->nr_rings == 1) 173 + preemption_supported = priv->gpu->nr_rings == 1 && enable_preemption != 0; 174 + 175 + if (flags & MSM_SUBMITQUEUE_ALLOW_PREEMPT && preemption_supported) 176 176 return -EINVAL; 177 177 178 178 ret = msm_gpu_convert_priority(priv->gpu, prio, &ring_nr, &sched_prio);