tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
clk: tegra: fix sdmmc clks on Tegra1x4
The sdmmc clocks on Tegra114 and Tegra124 are 3-bit wide muxes with
6 parents. Add support for tegra_clk_sdmmc*_8 and switch Tegra114
and Tegra124 to use these clocks instead.
Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
authored by
Andrew Bresticker
and committed by
Peter De Schrijver
20e7c323
82ba1c3c
+16
-8
+4
drivers/clk/tegra/clk-id.h
+4
drivers/clk/tegra/clk-id.h
···
180
180
tegra_clk_sbc6_8,
181
181
tegra_clk_sclk,
182
182
tegra_clk_sdmmc1,
183
+
tegra_clk_sdmmc1_8,
183
184
tegra_clk_sdmmc2,
185
+
tegra_clk_sdmmc2_8,
184
186
tegra_clk_sdmmc3,
187
+
tegra_clk_sdmmc3_8,
185
188
tegra_clk_sdmmc4,
189
+
tegra_clk_sdmmc4_8,
186
190
tegra_clk_se,
187
191
tegra_clk_soc_therm,
188
192
tegra_clk_sor0,
+4
drivers/clk/tegra/clk-tegra-periph.c
+4
drivers/clk/tegra/clk-tegra-periph.c
···
465
465
MUX("adx1", mux_plla_pllc_pllp_clkm, CLK_SOURCE_ADX1, 180, TEGRA_PERIPH_ON_APB, tegra_clk_adx1),
466
466
MUX("amx1", mux_plla_pllc_pllp_clkm, CLK_SOURCE_AMX1, 185, TEGRA_PERIPH_ON_APB, tegra_clk_amx1),
467
467
MUX("vi_sensor2", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_VI_SENSOR2, 20, TEGRA_PERIPH_NO_RESET, tegra_clk_vi_sensor2),
468
+
MUX8("sdmmc1", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SDMMC1, 14, 0, tegra_clk_sdmmc1_8),
469
+
MUX8("sdmmc2", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SDMMC2, 9, 0, tegra_clk_sdmmc2_8),
470
+
MUX8("sdmmc3", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SDMMC3, 69, 0, tegra_clk_sdmmc3_8),
471
+
MUX8("sdmmc4", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SDMMC4, 15, 0, tegra_clk_sdmmc4_8),
468
472
MUX8("sbc1", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SBC1, 41, TEGRA_PERIPH_ON_APB, tegra_clk_sbc1_8),
469
473
MUX8("sbc2", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SBC2, 44, TEGRA_PERIPH_ON_APB, tegra_clk_sbc2_8),
470
474
MUX8("sbc3", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SBC3, 46, TEGRA_PERIPH_ON_APB, tegra_clk_sbc3_8),
+4
-4
drivers/clk/tegra/clk-tegra114.c
+4
-4
drivers/clk/tegra/clk-tegra114.c
···
682
682
[tegra_clk_timer] = { .dt_id = TEGRA114_CLK_TIMER, .present = true },
683
683
[tegra_clk_uarta] = { .dt_id = TEGRA114_CLK_UARTA, .present = true },
684
684
[tegra_clk_uartd] = { .dt_id = TEGRA114_CLK_UARTD, .present = true },
685
-
[tegra_clk_sdmmc2] = { .dt_id = TEGRA114_CLK_SDMMC2, .present = true },
685
+
[tegra_clk_sdmmc2_8] = { .dt_id = TEGRA114_CLK_SDMMC2, .present = true },
686
686
[tegra_clk_i2s1] = { .dt_id = TEGRA114_CLK_I2S1, .present = true },
687
687
[tegra_clk_i2c1] = { .dt_id = TEGRA114_CLK_I2C1, .present = true },
688
688
[tegra_clk_ndflash] = { .dt_id = TEGRA114_CLK_NDFLASH, .present = true },
689
-
[tegra_clk_sdmmc1] = { .dt_id = TEGRA114_CLK_SDMMC1, .present = true },
690
-
[tegra_clk_sdmmc4] = { .dt_id = TEGRA114_CLK_SDMMC4, .present = true },
689
+
[tegra_clk_sdmmc1_8] = { .dt_id = TEGRA114_CLK_SDMMC1, .present = true },
690
+
[tegra_clk_sdmmc4_8] = { .dt_id = TEGRA114_CLK_SDMMC4, .present = true },
691
691
[tegra_clk_pwm] = { .dt_id = TEGRA114_CLK_PWM, .present = true },
692
692
[tegra_clk_i2s0] = { .dt_id = TEGRA114_CLK_I2S0, .present = true },
693
693
[tegra_clk_i2s2] = { .dt_id = TEGRA114_CLK_I2S2, .present = true },
···
723
723
[tegra_clk_bsev] = { .dt_id = TEGRA114_CLK_BSEV, .present = true },
724
724
[tegra_clk_i2c3] = { .dt_id = TEGRA114_CLK_I2C3, .present = true },
725
725
[tegra_clk_sbc4_8] = { .dt_id = TEGRA114_CLK_SBC4, .present = true },
726
-
[tegra_clk_sdmmc3] = { .dt_id = TEGRA114_CLK_SDMMC3, .present = true },
726
+
[tegra_clk_sdmmc3_8] = { .dt_id = TEGRA114_CLK_SDMMC3, .present = true },
727
727
[tegra_clk_owr] = { .dt_id = TEGRA114_CLK_OWR, .present = true },
728
728
[tegra_clk_csite] = { .dt_id = TEGRA114_CLK_CSITE, .present = true },
729
729
[tegra_clk_la] = { .dt_id = TEGRA114_CLK_LA, .present = true },
+4
-4
drivers/clk/tegra/clk-tegra124.c
+4
-4
drivers/clk/tegra/clk-tegra124.c
···
761
761
[tegra_clk_rtc] = { .dt_id = TEGRA124_CLK_RTC, .present = true },
762
762
[tegra_clk_timer] = { .dt_id = TEGRA124_CLK_TIMER, .present = true },
763
763
[tegra_clk_uarta] = { .dt_id = TEGRA124_CLK_UARTA, .present = true },
764
-
[tegra_clk_sdmmc2] = { .dt_id = TEGRA124_CLK_SDMMC2, .present = true },
764
+
[tegra_clk_sdmmc2_8] = { .dt_id = TEGRA124_CLK_SDMMC2, .present = true },
765
765
[tegra_clk_i2s1] = { .dt_id = TEGRA124_CLK_I2S1, .present = true },
766
766
[tegra_clk_i2c1] = { .dt_id = TEGRA124_CLK_I2C1, .present = true },
767
767
[tegra_clk_ndflash] = { .dt_id = TEGRA124_CLK_NDFLASH, .present = true },
768
-
[tegra_clk_sdmmc1] = { .dt_id = TEGRA124_CLK_SDMMC1, .present = true },
769
-
[tegra_clk_sdmmc4] = { .dt_id = TEGRA124_CLK_SDMMC4, .present = true },
768
+
[tegra_clk_sdmmc1_8] = { .dt_id = TEGRA124_CLK_SDMMC1, .present = true },
769
+
[tegra_clk_sdmmc4_8] = { .dt_id = TEGRA124_CLK_SDMMC4, .present = true },
770
770
[tegra_clk_pwm] = { .dt_id = TEGRA124_CLK_PWM, .present = true },
771
771
[tegra_clk_i2s2] = { .dt_id = TEGRA124_CLK_I2S2, .present = true },
772
772
[tegra_clk_gr2d] = { .dt_id = TEGRA124_CLK_GR_2D, .present = true },
···
802
802
[tegra_clk_uartd] = { .dt_id = TEGRA124_CLK_UARTD, .present = true },
803
803
[tegra_clk_i2c3] = { .dt_id = TEGRA124_CLK_I2C3, .present = true },
804
804
[tegra_clk_sbc4] = { .dt_id = TEGRA124_CLK_SBC4, .present = true },
805
-
[tegra_clk_sdmmc3] = { .dt_id = TEGRA124_CLK_SDMMC3, .present = true },
805
+
[tegra_clk_sdmmc3_8] = { .dt_id = TEGRA124_CLK_SDMMC3, .present = true },
806
806
[tegra_clk_pcie] = { .dt_id = TEGRA124_CLK_PCIE, .present = true },
807
807
[tegra_clk_owr] = { .dt_id = TEGRA124_CLK_OWR, .present = true },
808
808
[tegra_clk_afi] = { .dt_id = TEGRA124_CLK_AFI, .present = true },