Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux

wifi: rt2x00: improve MT7620 register initialization

1. Do not hard reset the BBP. We can use soft reset instead. This
change has some help to the calibration failure issue.
2. Enable falling back to legacy rate from the HT/RTS rate by
setting the HT_FBK_TO_LEGACY register.
3. Implement MCS rate specific maximum PSDU size. It can improve
the transmission quality under the low RSSI condition.
4. Set BBP_84 register value to 0x19. This is used for extension
channel overlapping IOT.

Signed-off-by: Shiji Yang <yangshiji66@outlook.com>
Acked-by: Stanislaw Gruszka <stf_xl@wp.pl>
Signed-off-by: Kalle Valo <kvalo@kernel.org>
Link: https://lore.kernel.org/r/TYAP286MB031553CCD4B7A3B89C85935DBCD4A@TYAP286MB0315.JPNP286.PROD.OUTLOOK.COM

authored by

Shiji Yang and committed by
Kalle Valo
1ffe76d5 0057680e

+45
+18
drivers/net/wireless/ralink/rt2x00/rt2800.h
··· 871 871 #define LED_CFG_LED_POLAR FIELD32(0x40000000) 872 872 873 873 /* 874 + * AMPDU_MAX_LEN_20M1S: Per MCS max A-MPDU length, 20 MHz, MCS 0-7 875 + * AMPDU_MAX_LEN_20M2S: Per MCS max A-MPDU length, 20 MHz, MCS 8-15 876 + * AMPDU_MAX_LEN_40M1S: Per MCS max A-MPDU length, 40 MHz, MCS 0-7 877 + * AMPDU_MAX_LEN_40M2S: Per MCS max A-MPDU length, 40 MHz, MCS 8-15 878 + * Maximum A-MPDU length = 2^(AMPDU_MAX - 5) kilobytes 879 + */ 880 + #define AMPDU_MAX_LEN_20M1S 0x1030 881 + #define AMPDU_MAX_LEN_20M2S 0x1034 882 + #define AMPDU_MAX_LEN_40M1S 0x1038 883 + #define AMPDU_MAX_LEN_40M2S 0x103C 884 + 885 + /* 874 886 * AMPDU_BA_WINSIZE: Force BlockAck window size 875 887 * FORCE_WINSIZE_ENABLE: 876 888 * 0: Disable forcing of BlockAck window size ··· 1556 1544 * EXP_ACK_TIME: 1557 1545 */ 1558 1546 #define EXP_ACK_TIME 0x1380 1547 + 1548 + /* 1549 + * HT_FBK_TO_LEGACY: Enable/Disable HT/RTS fallback to OFDM/CCK rate 1550 + * Not available for legacy SoCs 1551 + */ 1552 + #define HT_FBK_TO_LEGACY 0x1384 1559 1553 1560 1554 /* TX_PWR_CFG_5 */ 1561 1555 #define TX_PWR_CFG_5 0x1384
+24
drivers/net/wireless/ralink/rt2x00/rt2800lib.c
··· 5851 5851 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data; 5852 5852 u32 reg; 5853 5853 u16 eeprom; 5854 + u8 bbp; 5854 5855 unsigned int i; 5855 5856 int ret; 5856 5857 ··· 5860 5859 ret = rt2800_drv_init_registers(rt2x00dev); 5861 5860 if (ret) 5862 5861 return ret; 5862 + 5863 + if (rt2x00_rt(rt2x00dev, RT6352)) { 5864 + rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0x01); 5865 + 5866 + bbp = rt2800_bbp_read(rt2x00dev, 21); 5867 + bbp |= 0x01; 5868 + rt2800_bbp_write(rt2x00dev, 21, bbp); 5869 + bbp = rt2800_bbp_read(rt2x00dev, 21); 5870 + bbp &= (~0x01); 5871 + rt2800_bbp_write(rt2x00dev, 21, bbp); 5872 + 5873 + rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00); 5874 + } 5863 5875 5864 5876 rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE, 0x0000013f); 5865 5877 rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003); ··· 6027 6013 reg = rt2800_register_read(rt2x00dev, TX_ALC_CFG_1); 6028 6014 rt2x00_set_field32(&reg, TX_ALC_CFG_1_ROS_BUSY_EN, 0); 6029 6015 rt2800_register_write(rt2x00dev, TX_ALC_CFG_1, reg); 6016 + 6017 + rt2800_register_write(rt2x00dev, AMPDU_MAX_LEN_20M1S, 0x77754433); 6018 + rt2800_register_write(rt2x00dev, AMPDU_MAX_LEN_20M2S, 0x77765543); 6019 + rt2800_register_write(rt2x00dev, AMPDU_MAX_LEN_40M1S, 0x77765544); 6020 + rt2800_register_write(rt2x00dev, AMPDU_MAX_LEN_40M2S, 0x77765544); 6021 + 6022 + rt2800_register_write(rt2x00dev, HT_FBK_TO_LEGACY, 0x1010); 6023 + 6030 6024 } else { 6031 6025 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000000); 6032 6026 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606); ··· 7253 7231 rt2800_bbp_dcoc_write(rt2x00dev, 159, 0x64); 7254 7232 7255 7233 rt2800_bbp4_mac_if_ctrl(rt2x00dev); 7234 + 7235 + rt2800_bbp_write(rt2x00dev, 84, 0x19); 7256 7236 } 7257 7237 7258 7238 static void rt2800_init_bbp(struct rt2x00_dev *rt2x00dev)
+3
drivers/net/wireless/ralink/rt2x00/rt2800mmio.c
··· 760 760 761 761 rt2x00mmio_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003); 762 762 763 + if (rt2x00_rt(rt2x00dev, RT6352)) 764 + return 0; 765 + 763 766 reg = 0; 764 767 rt2x00_set_field32(&reg, MAC_SYS_CTRL_RESET_CSR, 1); 765 768 rt2x00_set_field32(&reg, MAC_SYS_CTRL_RESET_BBP, 1);