tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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Merge tag 'armsoc-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc

Pull ARM SoC fixes from Olof Johansson:
"I had queued up a batch of fixes that got a bit close to the release
for sending in before the merge window opened, so I'm including them
in the merge window batch instead.

Mostly smaller DT tweaks and fixes, the usual mix that we tend to have
through the releases"

* tag 'armsoc-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc:
ARM: dts: iwg20d-q7-common: Fix touch controller probe failure
ARM: OMAP2+: Restore MPU power domain if cpu_cluster_pm_enter() fails
ARM: dts: am33xx: modify AM33XX_IOPAD for #pinctrl-cells = 2
soc: actions: include header to fix missing prototype
arm64: dts: ti: k3-j721e: Rename mux header and update macro names
soc: qcom: pdr: Fixup array type of get_domain_list_resp message
arm64: dts: qcom: pm660: Fix missing pound sign in interrupt-cells
arm64: dts: qcom: kitakami: Temporarily disable SDHCI1
arm64: dts: sdm630: Temporarily disable SMMUs by default
arm64: dts: sdm845: Fixup OPP table for all qup devices
arm64: dts: allwinner: h5: remove Mali GPU PMU module
ARM: dts: sun8i: r40: bananapi-m2-ultra: Fix dcdc1 regulator
soc: xilinx: Fix error code in zynqmp_pm_probe()

Linus Torvalds 1f70935f f11901ed

+134 -82
+14 -1
arch/arm/boot/dts/iwg20d-q7-common.dtsi
··· 57 57 58 58 lvds-receiver { 59 59 compatible = "ti,ds90cf384a", "lvds-decoder"; 60 - powerdown-gpios = <&gpio7 25 GPIO_ACTIVE_LOW>; 60 + power-supply = <&vcc_3v3_tft1>; 61 61 62 62 ports { 63 63 #address-cells = <1>; ··· 81 81 panel { 82 82 compatible = "edt,etm0700g0dh6"; 83 83 backlight = <&lcd_backlight>; 84 + power-supply = <&vcc_3v3_tft1>; 84 85 85 86 port { 86 87 panel_in: endpoint { ··· 112 111 sndcodec: simple-audio-card,codec { 113 112 sound-dai = <&sgtl5000>; 114 113 }; 114 + }; 115 + 116 + vcc_3v3_tft1: regulator-panel { 117 + compatible = "regulator-fixed"; 118 + 119 + regulator-name = "vcc-3v3-tft1"; 120 + regulator-min-microvolt = <3300000>; 121 + regulator-max-microvolt = <3300000>; 122 + enable-active-high; 123 + startup-delay-us = <500>; 124 + gpio = <&gpio7 25 GPIO_ACTIVE_HIGH>; 115 125 }; 116 126 117 127 vcc_sdhi1: regulator-vcc-sdhi1 { ··· 219 207 reg = <0x38>; 220 208 interrupt-parent = <&gpio2>; 221 209 interrupts = <12 IRQ_TYPE_EDGE_FALLING>; 210 + vcc-supply = <&vcc_3v3_tft1>; 222 211 }; 223 212 }; 224 213
+5 -5
arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts
··· 223 223 }; 224 224 225 225 &reg_dc1sw { 226 - regulator-min-microvolt = <3000000>; 227 - regulator-max-microvolt = <3000000>; 226 + regulator-min-microvolt = <3300000>; 227 + regulator-max-microvolt = <3300000>; 228 228 regulator-name = "vcc-gmac-phy"; 229 229 }; 230 230 231 231 &reg_dcdc1 { 232 232 regulator-always-on; 233 - regulator-min-microvolt = <3000000>; 234 - regulator-max-microvolt = <3000000>; 235 - regulator-name = "vcc-3v0"; 233 + regulator-min-microvolt = <3300000>; 234 + regulator-max-microvolt = <3300000>; 235 + regulator-name = "vcc-3v3"; 236 236 }; 237 237 238 238 &reg_dcdc2 {
+3 -1
arch/arm/mach-omap2/cpuidle44xx.c
··· 174 174 */ 175 175 if (mpuss_can_lose_context) { 176 176 error = cpu_cluster_pm_enter(); 177 - if (error) 177 + if (error) { 178 + omap_set_pwrdm_state(mpu_pd, PWRDM_POWER_ON); 178 179 goto cpu_cluster_pm_out; 180 + } 179 181 } 180 182 } 181 183
+2 -4
arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi
··· 139 139 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 140 140 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 141 141 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 142 - <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 143 - <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 142 + <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 144 143 interrupt-names = "gp", 145 144 "gpmmu", 146 145 "pp", ··· 150 151 "pp2", 151 152 "ppmmu2", 152 153 "pp3", 153 - "ppmmu3", 154 - "pmu"; 154 + "ppmmu3"; 155 155 clocks = <&ccu CLK_BUS_GPU>, <&ccu CLK_GPU>; 156 156 clock-names = "bus", "core"; 157 157 resets = <&ccu RST_BUS_GPU>;
+6 -1
arch/arm64/boot/dts/qcom/msm8994-sony-xperia-kitakami.dtsi
··· 221 221 }; 222 222 223 223 &sdhc1 { 224 - status = "okay"; 224 + /* There is an issue with the eMMC causing permanent 225 + * damage to the card if a quirk isn't addressed. 226 + * Until it's fixed, disable the MMC so as not to brick 227 + * devices. 228 + */ 229 + status = "disabled"; 225 230 226 231 /* Downstream pushes 2.95V to the sdhci device, 227 232 * but upstream driver REALLY wants to make vmmc 1.8v
+1 -1
arch/arm64/boot/dts/qcom/pm660.dtsi
··· 44 44 gpio-ranges = <&pm660_gpios 0 0 13>; 45 45 #gpio-cells = <2>; 46 46 interrupt-controller; 47 - interrupt-cells =<2>; 47 + #interrupt-cells = <2>; 48 48 }; 49 49 }; 50 50 };
+8
arch/arm64/boot/dts/qcom/sdm630.dtsi
··· 518 518 <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>, 519 519 <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>, 520 520 <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>; 521 + 522 + status = "disabled"; 521 523 }; 522 524 523 525 tcsr_mutex_regs: syscon@1f40000 { ··· 751 749 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 752 750 <GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>, 753 751 <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>; 752 + 753 + status = "disabled"; 754 754 }; 755 755 756 756 lpass_smmu: iommu@5100000 { ··· 782 778 <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>, 783 779 <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>, 784 780 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>; 781 + 782 + status = "disabled"; 785 783 }; 786 784 787 785 spmi_bus: spmi@800f000 { ··· 1080 1074 <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>, 1081 1075 <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>, 1082 1076 <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>; 1077 + 1078 + status = "disabled"; 1083 1079 }; 1084 1080 1085 1081 apcs_glb: mailbox@17911000 {
+7 -2
arch/arm64/boot/dts/qcom/sdm845.dtsi
··· 1093 1093 qup_opp_table: qup-opp-table { 1094 1094 compatible = "operating-points-v2"; 1095 1095 1096 - opp-19200000 { 1097 - opp-hz = /bits/ 64 <19200000>; 1096 + opp-50000000 { 1097 + opp-hz = /bits/ 64 <50000000>; 1098 1098 required-opps = <&rpmhpd_opp_min_svs>; 1099 1099 }; 1100 1100 ··· 1106 1106 opp-100000000 { 1107 1107 opp-hz = /bits/ 64 <100000000>; 1108 1108 required-opps = <&rpmhpd_opp_svs>; 1109 + }; 1110 + 1111 + opp-128000000 { 1112 + opp-hz = /bits/ 64 <128000000>; 1113 + required-opps = <&rpmhpd_opp_nom>; 1109 1114 }; 1110 1115 }; 1111 1116
+6 -5
arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts
··· 404 404 }; 405 405 406 406 &serdes_ln_ctrl { 407 - idle-states = <SERDES0_LANE0_PCIE0_LANE0>, <SERDES0_LANE1_PCIE0_LANE1>, 408 - <SERDES1_LANE0_PCIE1_LANE0>, <SERDES1_LANE1_PCIE1_LANE1>, 409 - <SERDES2_LANE0_PCIE2_LANE0>, <SERDES2_LANE1_PCIE2_LANE1>, 410 - <SERDES3_LANE0_USB3_0_SWAP>, <SERDES3_LANE1_USB3_0>, 411 - <SERDES4_LANE0_EDP_LANE0>, <SERDES4_LANE1_EDP_LANE1>, <SERDES4_LANE2_EDP_LANE2>, <SERDES4_LANE3_EDP_LANE3>; 407 + idle-states = <J721E_SERDES0_LANE0_PCIE0_LANE0>, <J721E_SERDES0_LANE1_PCIE0_LANE1>, 408 + <J721E_SERDES1_LANE0_PCIE1_LANE0>, <J721E_SERDES1_LANE1_PCIE1_LANE1>, 409 + <J721E_SERDES2_LANE0_PCIE2_LANE0>, <J721E_SERDES2_LANE1_PCIE2_LANE1>, 410 + <J721E_SERDES3_LANE0_USB3_0_SWAP>, <J721E_SERDES3_LANE1_USB3_0>, 411 + <J721E_SERDES4_LANE0_EDP_LANE0>, <J721E_SERDES4_LANE1_EDP_LANE1>, 412 + <J721E_SERDES4_LANE2_EDP_LANE2>, <J721E_SERDES4_LANE3_EDP_LANE3>; 412 413 }; 413 414 414 415 &serdes_wiz3 {
+7 -6
arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
··· 6 6 */ 7 7 #include <dt-bindings/phy/phy.h> 8 8 #include <dt-bindings/mux/mux.h> 9 - #include <dt-bindings/mux/mux-j721e-wiz.h> 9 + #include <dt-bindings/mux/ti-serdes.h> 10 10 11 11 &cbass_main { 12 12 msmc_ram: sram@70000000 { ··· 38 38 <0x40b0 0x3>, <0x40b4 0x3>, /* SERDES3 lane0/1 select */ 39 39 <0x40c0 0x3>, <0x40c4 0x3>, <0x40c8 0x3>, <0x40cc 0x3>; 40 40 /* SERDES4 lane0/1/2/3 select */ 41 - idle-states = <SERDES0_LANE0_PCIE0_LANE0>, <SERDES0_LANE1_PCIE0_LANE1>, 42 - <SERDES1_LANE0_PCIE1_LANE0>, <SERDES1_LANE1_PCIE1_LANE1>, 43 - <SERDES2_LANE0_PCIE2_LANE0>, <SERDES2_LANE1_PCIE2_LANE1>, 44 - <MUX_IDLE_AS_IS>, <SERDES3_LANE1_USB3_0>, 45 - <SERDES4_LANE0_EDP_LANE0>, <SERDES4_LANE1_EDP_LANE1>, <SERDES4_LANE2_EDP_LANE2>, <SERDES4_LANE3_EDP_LANE3>; 41 + idle-states = <J721E_SERDES0_LANE0_PCIE0_LANE0>, <J721E_SERDES0_LANE1_PCIE0_LANE1>, 42 + <J721E_SERDES1_LANE0_PCIE1_LANE0>, <J721E_SERDES1_LANE1_PCIE1_LANE1>, 43 + <J721E_SERDES2_LANE0_PCIE2_LANE0>, <J721E_SERDES2_LANE1_PCIE2_LANE1>, 44 + <MUX_IDLE_AS_IS>, <J721E_SERDES3_LANE1_USB3_0>, 45 + <J721E_SERDES4_LANE0_EDP_LANE0>, <J721E_SERDES4_LANE1_EDP_LANE1>, 46 + <J721E_SERDES4_LANE2_EDP_LANE2>, <J721E_SERDES4_LANE3_EDP_LANE3>; 46 47 }; 47 48 48 49 usb_serdes_mux: mux-controller@4000 {
+1
drivers/soc/actions/owl-sps-helper.c
··· 10 10 11 11 #include <linux/delay.h> 12 12 #include <linux/io.h> 13 + #include <linux/soc/actions/owl-sps.h> 13 14 14 15 #define OWL_SPS_PG_CTL 0x0 15 16
+1 -1
drivers/soc/qcom/pdr_internal.h
··· 185 185 .data_type = QMI_STRUCT, 186 186 .elem_len = SERVREG_DOMAIN_LIST_LENGTH, 187 187 .elem_size = sizeof(struct servreg_location_entry), 188 - .array_type = NO_ARRAY, 188 + .array_type = VAR_LEN_ARRAY, 189 189 .tlv_type = 0x12, 190 190 .offset = offsetof(struct servreg_get_domain_list_resp, 191 191 domain_list),
+1 -1
drivers/soc/xilinx/zynqmp_power.c
··· 205 205 rx_chan = mbox_request_channel_byname(client, "rx"); 206 206 if (IS_ERR(rx_chan)) { 207 207 dev_err(&pdev->dev, "Failed to request rx channel\n"); 208 - return IS_ERR(rx_chan); 208 + return PTR_ERR(rx_chan); 209 209 } 210 210 } else if (of_find_property(pdev->dev.of_node, "interrupts", NULL)) { 211 211 irq = platform_get_irq(pdev, 0);
-53
include/dt-bindings/mux/mux-j721e-wiz.h
··· 1 - /* SPDX-License-Identifier: GPL-2.0 */ 2 - /* 3 - * This header provides constants for J721E WIZ. 4 - */ 5 - 6 - #ifndef _DT_BINDINGS_J721E_WIZ 7 - #define _DT_BINDINGS_J721E_WIZ 8 - 9 - #define SERDES0_LANE0_QSGMII_LANE1 0x0 10 - #define SERDES0_LANE0_PCIE0_LANE0 0x1 11 - #define SERDES0_LANE0_USB3_0_SWAP 0x2 12 - 13 - #define SERDES0_LANE1_QSGMII_LANE2 0x0 14 - #define SERDES0_LANE1_PCIE0_LANE1 0x1 15 - #define SERDES0_LANE1_USB3_0 0x2 16 - 17 - #define SERDES1_LANE0_QSGMII_LANE3 0x0 18 - #define SERDES1_LANE0_PCIE1_LANE0 0x1 19 - #define SERDES1_LANE0_USB3_1_SWAP 0x2 20 - #define SERDES1_LANE0_SGMII_LANE0 0x3 21 - 22 - #define SERDES1_LANE1_QSGMII_LANE4 0x0 23 - #define SERDES1_LANE1_PCIE1_LANE1 0x1 24 - #define SERDES1_LANE1_USB3_1 0x2 25 - #define SERDES1_LANE1_SGMII_LANE1 0x3 26 - 27 - #define SERDES2_LANE0_PCIE2_LANE0 0x1 28 - #define SERDES2_LANE0_SGMII_LANE0 0x3 29 - #define SERDES2_LANE0_USB3_1_SWAP 0x2 30 - 31 - #define SERDES2_LANE1_PCIE2_LANE1 0x1 32 - #define SERDES2_LANE1_USB3_1 0x2 33 - #define SERDES2_LANE1_SGMII_LANE1 0x3 34 - 35 - #define SERDES3_LANE0_PCIE3_LANE0 0x1 36 - #define SERDES3_LANE0_USB3_0_SWAP 0x2 37 - 38 - #define SERDES3_LANE1_PCIE3_LANE1 0x1 39 - #define SERDES3_LANE1_USB3_0 0x2 40 - 41 - #define SERDES4_LANE0_EDP_LANE0 0x0 42 - #define SERDES4_LANE0_QSGMII_LANE5 0x2 43 - 44 - #define SERDES4_LANE1_EDP_LANE1 0x0 45 - #define SERDES4_LANE1_QSGMII_LANE6 0x2 46 - 47 - #define SERDES4_LANE2_EDP_LANE2 0x0 48 - #define SERDES4_LANE2_QSGMII_LANE7 0x2 49 - 50 - #define SERDES4_LANE3_EDP_LANE3 0x0 51 - #define SERDES4_LANE3_QSGMII_LANE8 0x2 52 - 53 - #endif /* _DT_BINDINGS_J721E_WIZ */
+71
include/dt-bindings/mux/ti-serdes.h
··· 1 + /* SPDX-License-Identifier: GPL-2.0 */ 2 + /* 3 + * This header provides constants for SERDES MUX for TI SoCs 4 + */ 5 + 6 + #ifndef _DT_BINDINGS_MUX_TI_SERDES 7 + #define _DT_BINDINGS_MUX_TI_SERDES 8 + 9 + /* J721E */ 10 + 11 + #define J721E_SERDES0_LANE0_QSGMII_LANE1 0x0 12 + #define J721E_SERDES0_LANE0_PCIE0_LANE0 0x1 13 + #define J721E_SERDES0_LANE0_USB3_0_SWAP 0x2 14 + #define J721E_SERDES0_LANE0_IP4_UNUSED 0x3 15 + 16 + #define J721E_SERDES0_LANE1_QSGMII_LANE2 0x0 17 + #define J721E_SERDES0_LANE1_PCIE0_LANE1 0x1 18 + #define J721E_SERDES0_LANE1_USB3_0 0x2 19 + #define J721E_SERDES0_LANE1_IP4_UNUSED 0x3 20 + 21 + #define J721E_SERDES1_LANE0_QSGMII_LANE3 0x0 22 + #define J721E_SERDES1_LANE0_PCIE1_LANE0 0x1 23 + #define J721E_SERDES1_LANE0_USB3_1_SWAP 0x2 24 + #define J721E_SERDES1_LANE0_SGMII_LANE0 0x3 25 + 26 + #define J721E_SERDES1_LANE1_QSGMII_LANE4 0x0 27 + #define J721E_SERDES1_LANE1_PCIE1_LANE1 0x1 28 + #define J721E_SERDES1_LANE1_USB3_1 0x2 29 + #define J721E_SERDES1_LANE1_SGMII_LANE1 0x3 30 + 31 + #define J721E_SERDES2_LANE0_IP1_UNUSED 0x0 32 + #define J721E_SERDES2_LANE0_PCIE2_LANE0 0x1 33 + #define J721E_SERDES2_LANE0_USB3_1_SWAP 0x2 34 + #define J721E_SERDES2_LANE0_SGMII_LANE0 0x3 35 + 36 + #define J721E_SERDES2_LANE1_IP1_UNUSED 0x0 37 + #define J721E_SERDES2_LANE1_PCIE2_LANE1 0x1 38 + #define J721E_SERDES2_LANE1_USB3_1 0x2 39 + #define J721E_SERDES2_LANE1_SGMII_LANE1 0x3 40 + 41 + #define J721E_SERDES3_LANE0_IP1_UNUSED 0x0 42 + #define J721E_SERDES3_LANE0_PCIE3_LANE0 0x1 43 + #define J721E_SERDES3_LANE0_USB3_0_SWAP 0x2 44 + #define J721E_SERDES3_LANE0_IP4_UNUSED 0x3 45 + 46 + #define J721E_SERDES3_LANE1_IP1_UNUSED 0x0 47 + #define J721E_SERDES3_LANE1_PCIE3_LANE1 0x1 48 + #define J721E_SERDES3_LANE1_USB3_0 0x2 49 + #define J721E_SERDES3_LANE1_IP4_UNUSED 0x3 50 + 51 + #define J721E_SERDES4_LANE0_EDP_LANE0 0x0 52 + #define J721E_SERDES4_LANE0_IP2_UNUSED 0x1 53 + #define J721E_SERDES4_LANE0_QSGMII_LANE5 0x2 54 + #define J721E_SERDES4_LANE0_IP4_UNUSED 0x3 55 + 56 + #define J721E_SERDES4_LANE1_EDP_LANE1 0x0 57 + #define J721E_SERDES4_LANE1_IP2_UNUSED 0x1 58 + #define J721E_SERDES4_LANE1_QSGMII_LANE6 0x2 59 + #define J721E_SERDES4_LANE1_IP4_UNUSED 0x3 60 + 61 + #define J721E_SERDES4_LANE2_EDP_LANE2 0x0 62 + #define J721E_SERDES4_LANE2_IP2_UNUSED 0x1 63 + #define J721E_SERDES4_LANE2_QSGMII_LANE7 0x2 64 + #define J721E_SERDES4_LANE2_IP4_UNUSED 0x3 65 + 66 + #define J721E_SERDES4_LANE3_EDP_LANE3 0x0 67 + #define J721E_SERDES4_LANE3_IP2_UNUSED 0x1 68 + #define J721E_SERDES4_LANE3_QSGMII_LANE8 0x2 69 + #define J721E_SERDES4_LANE3_IP4_UNUSED 0x3 70 + 71 + #endif /* _DT_BINDINGS_MUX_TI_SERDES */
+1 -1
include/dt-bindings/pinctrl/omap.h
··· 64 64 #define OMAP3_WKUP_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x2a00) (val) 65 65 #define DM814X_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x0800) (val) 66 66 #define DM816X_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x0800) (val) 67 - #define AM33XX_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x0800) (val) 67 + #define AM33XX_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x0800) (val) (0) 68 68 #define AM33XX_PADCONF(pa, conf, mux) OMAP_IOPAD_OFFSET((pa), 0x0800) (conf) (mux) 69 69 70 70 /*