tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux
fork atom

drm/rockchip: vop: add the definition of dclk_pol

Some VOP's (such as px30) dclk_pol bit is at the last.
So it is necessary to distinguish dclk_pol and pin_pol.

Signed-off-by: Nickey Yang <nickey.yang@rock-chips.com>
Reviewed-by: Sandy Huang <hjc@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Link: https://patchwork.freedesktop.org/patch/msgid/20191010034452.20260-2-nickey.yang@rock-chips.com

authored by

Nickey Yang and committed by
Heiko Stuebner 1f6c62ca c7337670

+43 -22
+7 -5
drivers/gpu/drm/rockchip/rockchip_drm_vop.c
··· 1198 1198 DRM_DEV_ERROR(vop->dev, "Failed to enable vop (%d)\n", ret); 1199 1199 return; 1200 1200 } 1201 - 1202 - pin_pol = BIT(DCLK_INVERT); 1203 - pin_pol |= (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) ? 1201 + pin_pol = (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) ? 1204 1202 BIT(HSYNC_POSITIVE) : 0; 1205 1203 pin_pol |= (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) ? 1206 1204 BIT(VSYNC_POSITIVE) : 0; ··· 1207 1209 1208 1210 switch (s->output_type) { 1209 1211 case DRM_MODE_CONNECTOR_LVDS: 1210 - VOP_REG_SET(vop, output, rgb_en, 1); 1212 + VOP_REG_SET(vop, output, rgb_dclk_pol, 1); 1211 1213 VOP_REG_SET(vop, output, rgb_pin_pol, pin_pol); 1214 + VOP_REG_SET(vop, output, rgb_en, 1); 1212 1215 break; 1213 1216 case DRM_MODE_CONNECTOR_eDP: 1217 + VOP_REG_SET(vop, output, edp_dclk_pol, 1); 1214 1218 VOP_REG_SET(vop, output, edp_pin_pol, pin_pol); 1215 1219 VOP_REG_SET(vop, output, edp_en, 1); 1216 1220 break; 1217 1221 case DRM_MODE_CONNECTOR_HDMIA: 1222 + VOP_REG_SET(vop, output, hdmi_dclk_pol, 1); 1218 1223 VOP_REG_SET(vop, output, hdmi_pin_pol, pin_pol); 1219 1224 VOP_REG_SET(vop, output, hdmi_en, 1); 1220 1225 break; 1221 1226 case DRM_MODE_CONNECTOR_DSI: 1227 + VOP_REG_SET(vop, output, mipi_dclk_pol, 1); 1222 1228 VOP_REG_SET(vop, output, mipi_pin_pol, pin_pol); 1223 1229 VOP_REG_SET(vop, output, mipi_en, 1); 1224 1230 VOP_REG_SET(vop, output, mipi_dual_channel_en, 1225 1231 !!(s->output_flags & ROCKCHIP_OUTPUT_DSI_DUAL)); 1226 1232 break; 1227 1233 case DRM_MODE_CONNECTOR_DisplayPort: 1228 - pin_pol &= ~BIT(DCLK_INVERT); 1234 + VOP_REG_SET(vop, output, dp_dclk_pol, 0); 1229 1235 VOP_REG_SET(vop, output, dp_pin_pol, pin_pol); 1230 1236 VOP_REG_SET(vop, output, dp_en, 1); 1231 1237 break;
+6 -2
drivers/gpu/drm/rockchip/rockchip_drm_vop.h
··· 46 46 struct vop_output { 47 47 struct vop_reg pin_pol; 48 48 struct vop_reg dp_pin_pol; 49 + struct vop_reg dp_dclk_pol; 49 50 struct vop_reg edp_pin_pol; 51 + struct vop_reg edp_dclk_pol; 50 52 struct vop_reg hdmi_pin_pol; 53 + struct vop_reg hdmi_dclk_pol; 51 54 struct vop_reg mipi_pin_pol; 55 + struct vop_reg mipi_dclk_pol; 52 56 struct vop_reg rgb_pin_pol; 57 + struct vop_reg rgb_dclk_pol; 53 58 struct vop_reg dp_en; 54 59 struct vop_reg edp_en; 55 60 struct vop_reg hdmi_en; ··· 301 296 enum vop_pol { 302 297 HSYNC_POSITIVE = 0, 303 298 VSYNC_POSITIVE = 1, 304 - DEN_NEGATIVE = 2, 305 - DCLK_INVERT = 3 299 + DEN_NEGATIVE = 2 306 300 }; 307 301 308 302 #define FRAC_16_16(mult, div) (((mult) << 16) / (div))
+30 -15
drivers/gpu/drm/rockchip/rockchip_vop_reg.c
··· 215 215 }; 216 216 217 217 static const struct vop_output px30_output = { 218 - .rgb_pin_pol = VOP_REG(PX30_DSP_CTRL0, 0xf, 1), 219 - .mipi_pin_pol = VOP_REG(PX30_DSP_CTRL0, 0xf, 25), 218 + .rgb_dclk_pol = VOP_REG(PX30_DSP_CTRL0, 0x1, 1), 219 + .rgb_pin_pol = VOP_REG(PX30_DSP_CTRL0, 0x7, 2), 220 220 .rgb_en = VOP_REG(PX30_DSP_CTRL0, 0x1, 0), 221 + .mipi_dclk_pol = VOP_REG(PX30_DSP_CTRL0, 0x1, 25), 222 + .mipi_pin_pol = VOP_REG(PX30_DSP_CTRL0, 0x7, 26), 221 223 .mipi_en = VOP_REG(PX30_DSP_CTRL0, 0x1, 24), 222 224 }; 223 225 ··· 722 720 }; 723 721 724 722 static const struct vop_output rk3368_output = { 725 - .rgb_pin_pol = VOP_REG(RK3368_DSP_CTRL1, 0xf, 16), 726 - .hdmi_pin_pol = VOP_REG(RK3368_DSP_CTRL1, 0xf, 20), 727 - .edp_pin_pol = VOP_REG(RK3368_DSP_CTRL1, 0xf, 24), 728 - .mipi_pin_pol = VOP_REG(RK3368_DSP_CTRL1, 0xf, 28), 723 + .rgb_dclk_pol = VOP_REG(RK3368_DSP_CTRL1, 0x1, 19), 724 + .hdmi_dclk_pol = VOP_REG(RK3368_DSP_CTRL1, 0x1, 23), 725 + .edp_dclk_pol = VOP_REG(RK3368_DSP_CTRL1, 0x1, 27), 726 + .mipi_dclk_pol = VOP_REG(RK3368_DSP_CTRL1, 0x1, 31), 727 + .rgb_pin_pol = VOP_REG(RK3368_DSP_CTRL1, 0x7, 16), 728 + .hdmi_pin_pol = VOP_REG(RK3368_DSP_CTRL1, 0x7, 20), 729 + .edp_pin_pol = VOP_REG(RK3368_DSP_CTRL1, 0x7, 24), 730 + .mipi_pin_pol = VOP_REG(RK3368_DSP_CTRL1, 0x7, 28), 729 731 .rgb_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 12), 730 732 .hdmi_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 13), 731 733 .edp_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 14), ··· 773 767 }; 774 768 775 769 static const struct vop_output rk3399_output = { 776 - .dp_pin_pol = VOP_REG(RK3399_DSP_CTRL1, 0xf, 16), 777 - .rgb_pin_pol = VOP_REG(RK3368_DSP_CTRL1, 0xf, 16), 778 - .hdmi_pin_pol = VOP_REG(RK3368_DSP_CTRL1, 0xf, 20), 779 - .edp_pin_pol = VOP_REG(RK3368_DSP_CTRL1, 0xf, 24), 780 - .mipi_pin_pol = VOP_REG(RK3368_DSP_CTRL1, 0xf, 28), 770 + .dp_dclk_pol = VOP_REG(RK3399_DSP_CTRL1, 0x1, 19), 771 + .rgb_dclk_pol = VOP_REG(RK3368_DSP_CTRL1, 0x1, 19), 772 + .hdmi_dclk_pol = VOP_REG(RK3368_DSP_CTRL1, 0x1, 23), 773 + .edp_dclk_pol = VOP_REG(RK3368_DSP_CTRL1, 0x1, 27), 774 + .mipi_dclk_pol = VOP_REG(RK3368_DSP_CTRL1, 0x1, 31), 775 + .dp_pin_pol = VOP_REG(RK3399_DSP_CTRL1, 0x7, 16), 776 + .rgb_pin_pol = VOP_REG(RK3368_DSP_CTRL1, 0x7, 16), 777 + .hdmi_pin_pol = VOP_REG(RK3368_DSP_CTRL1, 0x7, 20), 778 + .edp_pin_pol = VOP_REG(RK3368_DSP_CTRL1, 0x7, 24), 779 + .mipi_pin_pol = VOP_REG(RK3368_DSP_CTRL1, 0x7, 28), 781 780 .dp_en = VOP_REG(RK3399_SYS_CTRL, 0x1, 11), 782 781 .rgb_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 12), 783 782 .hdmi_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 13), ··· 886 875 }; 887 876 888 877 static const struct vop_output rk3328_output = { 878 + .rgb_dclk_pol = VOP_REG(RK3328_DSP_CTRL1, 0x1, 19), 879 + .hdmi_dclk_pol = VOP_REG(RK3328_DSP_CTRL1, 0x1, 23), 880 + .edp_dclk_pol = VOP_REG(RK3328_DSP_CTRL1, 0x1, 27), 881 + .mipi_dclk_pol = VOP_REG(RK3328_DSP_CTRL1, 0x1, 31), 889 882 .rgb_en = VOP_REG(RK3328_SYS_CTRL, 0x1, 12), 890 883 .hdmi_en = VOP_REG(RK3328_SYS_CTRL, 0x1, 13), 891 884 .edp_en = VOP_REG(RK3328_SYS_CTRL, 0x1, 14), 892 885 .mipi_en = VOP_REG(RK3328_SYS_CTRL, 0x1, 15), 893 - .rgb_pin_pol = VOP_REG(RK3328_DSP_CTRL1, 0xf, 16), 894 - .hdmi_pin_pol = VOP_REG(RK3328_DSP_CTRL1, 0xf, 20), 895 - .edp_pin_pol = VOP_REG(RK3328_DSP_CTRL1, 0xf, 24), 896 - .mipi_pin_pol = VOP_REG(RK3328_DSP_CTRL1, 0xf, 28), 886 + .rgb_pin_pol = VOP_REG(RK3328_DSP_CTRL1, 0x7, 16), 887 + .hdmi_pin_pol = VOP_REG(RK3328_DSP_CTRL1, 0x7, 20), 888 + .edp_pin_pol = VOP_REG(RK3328_DSP_CTRL1, 0x7, 24), 889 + .mipi_pin_pol = VOP_REG(RK3328_DSP_CTRL1, 0x7, 28), 897 890 }; 898 891 899 892 static const struct vop_misc rk3328_misc = {