drm/amd/display: Fix dpstreamclk programming

Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git

kernel os linux

[WHY]
Currently programming incorrect hpo inst as well as selecting incorrect source

[HOW]
Use hpo inst instead of otg inst to select dpstreamclk inst

Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>
Acked-by: Alex Hung <alex.hung@amd.com>
Signed-off-by: Michael Strauss <michael.strauss@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

authored by

Michael Strauss and committed by

Alex Deucher 3 years ago 1f5dcb73 b5e924bd

+20 -19

6 changed files

expand all

drivers

gpu

drm

amd

display

dcn31

dcn31_dccg.c

dcn31_dccg.h

dcn314

dcn314_dccg.c

dcn32

dcn32_dccg.c

inc

dccg.h

link

link_hwss_hpo_dp.c

+5 -3

drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.c

··· 158 158 } 159 159 } 160 160 161 - void dccg31_set_dpstreamclk(struct dccg *dccg, 162 - enum streamclk_source src, 163 - int otg_inst) 161 + void dccg31_set_dpstreamclk( 162 + struct dccg *dccg, 163 + enum streamclk_source src, 164 + int otg_inst, 165 + int dp_hpo_inst) 164 166 { 165 167 if (src == REFCLK) 166 168 dccg31_disable_dpstreamclk(dccg, otg_inst);

+2 -6

drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.h

··· 161 161 162 162 void dccg31_init(struct dccg *dccg); 163 163 164 - void dccg31_set_dpstreamclk( 165 - struct dccg *dccg, 166 - enum streamclk_source src, 167 - int otg_inst); 168 - 169 164 void dccg31_enable_symclk32_se( 170 165 struct dccg *dccg, 171 166 int hpo_se_inst, ··· 202 207 void dccg31_set_dpstreamclk( 203 208 struct dccg *dccg, 204 209 enum streamclk_source src, 205 - int otg_inst); 210 + int otg_inst, 211 + int dp_hpo_inst); 206 212 207 213 void dccg31_set_dtbclk_dto( 208 214 struct dccg *dccg,

+7 -6

drivers/gpu/drm/amd/display/dc/dcn314/dcn314_dccg.c

··· 184 184 void dccg314_set_dpstreamclk( 185 185 struct dccg *dccg, 186 186 enum streamclk_source src, 187 - int otg_inst) 187 + int otg_inst, 188 + int dp_hpo_inst) 188 189 { 189 190 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); 190 191 ··· 193 192 dccg314_set_dtbclk_p_src(dccg, src, otg_inst); 194 193 195 194 /* enabled to select one of the DTBCLKs for pipe */ 196 - switch (otg_inst) { 195 + switch (dp_hpo_inst) { 197 196 case 0: 198 197 REG_UPDATE_2(DPSTREAMCLK_CNTL, 199 198 DPSTREAMCLK0_EN, (src == REFCLK) ? 0 : 1, 200 - DPSTREAMCLK0_SRC_SEL, 0); 199 + DPSTREAMCLK0_SRC_SEL, otg_inst); 201 200 break; 202 201 case 1: 203 202 REG_UPDATE_2(DPSTREAMCLK_CNTL, 204 203 DPSTREAMCLK1_EN, (src == REFCLK) ? 0 : 1, 205 - DPSTREAMCLK1_SRC_SEL, 1); 204 + DPSTREAMCLK1_SRC_SEL, otg_inst); 206 205 break; 207 206 case 2: 208 207 REG_UPDATE_2(DPSTREAMCLK_CNTL, 209 208 DPSTREAMCLK2_EN, (src == REFCLK) ? 0 : 1, 210 - DPSTREAMCLK2_SRC_SEL, 2); 209 + DPSTREAMCLK2_SRC_SEL, otg_inst); 211 210 break; 212 211 case 3: 213 212 REG_UPDATE_2(DPSTREAMCLK_CNTL, 214 213 DPSTREAMCLK3_EN, (src == REFCLK) ? 0 : 1, 215 - DPSTREAMCLK3_SRC_SEL, 3); 214 + DPSTREAMCLK3_SRC_SEL, otg_inst); 216 215 break; 217 216 default: 218 217 BREAK_TO_DEBUGGER();

+2 -1

drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dccg.c

··· 211 211 void dccg32_set_dpstreamclk( 212 212 struct dccg *dccg, 213 213 enum streamclk_source src, 214 - int otg_inst) 214 + int otg_inst, 215 + int dp_hpo_inst) 215 216 { 216 217 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); 217 218

+2 -1

drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h

··· 101 101 void (*set_dpstreamclk)( 102 102 struct dccg *dccg, 103 103 enum streamclk_source src, 104 - int otg_inst); 104 + int otg_inst, 105 + int dp_hpo_inst); 105 106 106 107 void (*enable_symclk32_se)( 107 108 struct dccg *dccg,

+2 -2

drivers/gpu/drm/amd/display/dc/link/link_hwss_hpo_dp.c

··· 116 116 dto_params.timing = &pipe_ctx->stream->timing; 117 117 dto_params.ref_dtbclk_khz = dc->clk_mgr->funcs->get_dtb_ref_clk_frequency(dc->clk_mgr); 118 118 119 - dccg->funcs->set_dpstreamclk(dccg, DTBCLK0, tg->inst); 119 + dccg->funcs->set_dpstreamclk(dccg, DTBCLK0, tg->inst, link_enc->inst); 120 120 dccg->funcs->enable_symclk32_se(dccg, stream_enc->inst, phyd32clk); 121 121 dccg->funcs->set_dtbclk_dto(dccg, &dto_params); 122 122 stream_enc->funcs->enable_stream(stream_enc); ··· 137 137 stream_enc->funcs->disable(stream_enc); 138 138 dccg->funcs->set_dtbclk_dto(dccg, &dto_params); 139 139 dccg->funcs->disable_symclk32_se(dccg, stream_enc->inst); 140 - dccg->funcs->set_dpstreamclk(dccg, REFCLK, tg->inst); 140 + dccg->funcs->set_dpstreamclk(dccg, REFCLK, tg->inst, pipe_ctx->link_res.hpo_dp_link_enc->inst); 141 141 } 142 142 143 143 static void setup_hpo_dp_stream_attribute(struct pipe_ctx *pipe_ctx)