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Documentation: Fix minor typos
Corrected a few spelling errors and improved the phrasing
changes since v1:
--corrected as per review
Signed-off-by: Ranganath V N <vnranganath.20@gmail.com>
Reviewed-by: Randy Dunlap <rdunlap@infradead.org>
Signed-off-by: Jonathan Corbet <corbet@lwn.net>
Link: https://lore.kernel.org/r/20250726063645.4156-1-vnranganath.20@gmail.com
authored by
Ranganath V N
and committed by
Jonathan Corbet
1f590377
7069b529
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Documentation/arch/loongarch/irq-chip-model.rst
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Documentation/arch/loongarch/irq-chip-model.rst
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indicates that CPU Interrupt Pin selection can be normal method rather than
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bitmap method, so interrupt can be routed to IP0 - IP15.
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Feature EXTIOI_HAS_CPU_ENCODE is entension of V-EIOINTC. If it is 1, it
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Feature EXTIOI_HAS_CPU_ENCODE is extension of V-EIOINTC. If it is 1, it
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indicates that CPU selection can be normal method rather than bitmap method,
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so interrupt can be routed to CPU0 - CPU255.
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EXTIOI_VIRT_CONFIG
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------------------
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This register is read-write register, for compatibility intterupt routed uses
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This register is read-write register, for compatibility interrupt routed uses
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the default method which is the same with standard EIOINTC. If the bit is set
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with 1, it indicated HW to use normal method rather than bitmap method.
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Documentation/arch/x86/cpuinfo.rst
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Documentation/arch/x86/cpuinfo.rst
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represents an ill-fated attempt from long time ago to put feature flags
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in an easy to find place for userspace.
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However, the amount of feature flags is growing by the CPU generation,
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However, the number of feature flags is growing with each CPU generation,
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leading to unparseable and unwieldy /proc/cpuinfo.
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What is more, those feature flags do not even need to be in that file