tjh.dev
+20
-12
arch/x86/pci/fixup.c
+20
-12
arch/x86/pci/fixup.c
···
662
662
*/
663
663
static void pci_amd_enable_64bit_bar(struct pci_dev *dev)
664
664
{
665
+
static const char *name = "PCI Bus 0000:00";
666
+
struct resource *res, *conflict;
665
667
u32 base, limit, high;
666
668
struct pci_dev *other;
667
-
struct resource *res;
668
669
unsigned i;
669
-
int r;
670
670
671
671
if (!(pci_probe & PCI_BIG_ROOT_WINDOW))
672
672
return;
···
707
707
* Allocate a 256GB window directly below the 0xfd00000000 hardware
708
708
* limit (see AMD Family 15h Models 30h-3Fh BKDG, sec 2.4.6).
709
709
*/
710
-
res->name = "PCI Bus 0000:00";
710
+
res->name = name;
711
711
res->flags = IORESOURCE_PREFETCH | IORESOURCE_MEM |
712
712
IORESOURCE_MEM_64 | IORESOURCE_WINDOW;
713
713
res->start = 0xbd00000000ull;
714
714
res->end = 0xfd00000000ull - 1;
715
715
716
-
r = request_resource(&iomem_resource, res);
717
-
if (r) {
716
+
conflict = request_resource_conflict(&iomem_resource, res);
717
+
if (conflict) {
718
718
kfree(res);
719
-
return;
720
-
}
719
+
if (conflict->name != name)
720
+
return;
721
721
722
-
dev_info(&dev->dev, "adding root bus resource %pR (tainting kernel)\n",
723
-
res);
724
-
add_taint(TAINT_FIRMWARE_WORKAROUND, LOCKDEP_STILL_OK);
722
+
/* We are resuming from suspend; just reenable the window */
723
+
res = conflict;
724
+
} else {
725
+
dev_info(&dev->dev, "adding root bus resource %pR (tainting kernel)\n",
726
+
res);
727
+
add_taint(TAINT_FIRMWARE_WORKAROUND, LOCKDEP_STILL_OK);
728
+
pci_bus_add_resource(dev->bus, res, 0);
729
+
}
725
730
726
731
base = ((res->start >> 8) & AMD_141b_MMIO_BASE_MMIOBASE_MASK) |
727
732
AMD_141b_MMIO_BASE_RE_MASK | AMD_141b_MMIO_BASE_WE_MASK;
···
738
733
pci_write_config_dword(dev, AMD_141b_MMIO_HIGH(i), high);
739
734
pci_write_config_dword(dev, AMD_141b_MMIO_LIMIT(i), limit);
740
735
pci_write_config_dword(dev, AMD_141b_MMIO_BASE(i), base);
741
-
742
-
pci_bus_add_resource(dev->bus, res, 0);
743
736
}
744
737
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x1401, pci_amd_enable_64bit_bar);
745
738
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x141b, pci_amd_enable_64bit_bar);
746
739
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x1571, pci_amd_enable_64bit_bar);
747
740
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x15b1, pci_amd_enable_64bit_bar);
748
741
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x1601, pci_amd_enable_64bit_bar);
742
+
DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, 0x1401, pci_amd_enable_64bit_bar);
743
+
DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, 0x141b, pci_amd_enable_64bit_bar);
744
+
DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, 0x1571, pci_amd_enable_64bit_bar);
745
+
DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, 0x15b1, pci_amd_enable_64bit_bar);
746
+
DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, 0x1601, pci_amd_enable_64bit_bar);
749
747
750
748
#endif