staging: rtl8723bs: hal: Correct indentation

Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git

kernel os linux

Correct random indentation to improve readability. This problem
was observed when working on other checkpatch reports in the
file Hal8723BReg.h

Signed-off-by: Beatriz Martins de Carvalho <martinsdecarvalhobeatriz@gmail.com>
Link: https://lore.kernel.org/r/68e91c54a3be0b57607101fa8b284c00bb7dff1a.1618243073.git.martinsdecarvalhobeatriz@gmail.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

authored by

Beatriz Martins de Carvalho and committed by

Greg Kroah-Hartman 5 years ago 1ec0ee05 8b7d276e

+190 -190

1 changed file

expand all

drivers

staging

rtl8723bs

hal

Hal8723BReg.h

+190 -190

drivers/staging/rtl8723bs/hal/Hal8723BReg.h

··· 31 31 #define REG_SYS_ISO_CTRL_8723B 0x0000 /* 2 Byte */ 32 32 #define REG_SYS_FUNC_EN_8723B 0x0002 /* 2 Byte */ 33 33 #define REG_APS_FSMCO_8723B 0x0004 /* 4 Byte */ 34 - #define REG_SYS_CLKR_8723B 0x0008 /* 2 Byte */ 35 - #define REG_9346CR_8723B 0x000A /* 2 Byte */ 36 - #define REG_EE_VPD_8723B 0x000C /* 2 Byte */ 37 - #define REG_AFE_MISC_8723B 0x0010 /* 1 Byte */ 38 - #define REG_SPS0_CTRL_8723B 0x0011 /* 7 Byte */ 34 + #define REG_SYS_CLKR_8723B 0x0008 /* 2 Byte */ 35 + #define REG_9346CR_8723B 0x000A /* 2 Byte */ 36 + #define REG_EE_VPD_8723B 0x000C /* 2 Byte */ 37 + #define REG_AFE_MISC_8723B 0x0010 /* 1 Byte */ 38 + #define REG_SPS0_CTRL_8723B 0x0011 /* 7 Byte */ 39 39 #define REG_SPS_OCP_CFG_8723B 0x0018 /* 4 Byte */ 40 - #define REG_RSV_CTRL_8723B 0x001C /* 3 Byte */ 41 - #define REG_RF_CTRL_8723B 0x001F /* 1 Byte */ 40 + #define REG_RSV_CTRL_8723B 0x001C /* 3 Byte */ 41 + #define REG_RF_CTRL_8723B 0x001F /* 1 Byte */ 42 42 #define REG_LPLDO_CTRL_8723B 0x0023 /* 1 Byte */ 43 - #define REG_AFE_XTAL_CTRL_8723B 0x0024 /* 4 Byte */ 43 + #define REG_AFE_XTAL_CTRL_8723B 0x0024 /* 4 Byte */ 44 44 #define REG_AFE_PLL_CTRL_8723B 0x0028 /* 4 Byte */ 45 45 #define REG_MAC_PLL_CTRL_EXT_8723B 0x002c /* 4 Byte */ 46 46 #define REG_EFUSE_CTRL_8723B 0x0030 47 47 #define REG_EFUSE_TEST_8723B 0x0034 48 - #define REG_PWR_DATA_8723B 0x0038 49 - #define REG_CAL_TIMER_8723B 0x003C 50 - #define REG_ACLK_MON_8723B 0x003E 48 + #define REG_PWR_DATA_8723B 0x0038 49 + #define REG_CAL_TIMER_8723B 0x003C 50 + #define REG_ACLK_MON_8723B 0x003E 51 51 #define REG_GPIO_MUXCFG_8723B 0x0040 52 52 #define REG_GPIO_IO_SEL_8723B 0x0042 53 53 #define REG_MAC_PINMUX_CFG_8723B 0x0043 54 54 #define REG_GPIO_PIN_CTRL_8723B 0x0044 55 - #define REG_GPIO_INTM_8723B 0x0048 56 - #define REG_LEDCFG0_8723B 0x004C 57 - #define REG_LEDCFG1_8723B 0x004D 58 - #define REG_LEDCFG2_8723B 0x004E 59 - #define REG_LEDCFG3_8723B 0x004F 60 - #define REG_FSIMR_8723B 0x0050 61 - #define REG_FSISR_8723B 0x0054 62 - #define REG_HSIMR_8723B 0x0058 63 - #define REG_HSISR_8723B 0x005c 64 - #define REG_GPIO_EXT_CTRL 0x0060 55 + #define REG_GPIO_INTM_8723B 0x0048 56 + #define REG_LEDCFG0_8723B 0x004C 57 + #define REG_LEDCFG1_8723B 0x004D 58 + #define REG_LEDCFG2_8723B 0x004E 59 + #define REG_LEDCFG3_8723B 0x004F 60 + #define REG_FSIMR_8723B 0x0050 61 + #define REG_FSISR_8723B 0x0054 62 + #define REG_HSIMR_8723B 0x0058 63 + #define REG_HSISR_8723B 0x005c 64 + #define REG_GPIO_EXT_CTRL 0x0060 65 65 #define REG_MULTI_FUNC_CTRL_8723B 0x0068 66 66 #define REG_GPIO_STATUS_8723B 0x006C 67 - #define REG_SDIO_CTRL_8723B 0x0070 68 - #define REG_OPT_CTRL_8723B 0x0074 69 - #define REG_AFE_XTAL_CTRL_EXT_8723B 0x0078 70 - #define REG_MCUFWDL_8723B 0x0080 67 + #define REG_SDIO_CTRL_8723B 0x0070 68 + #define REG_OPT_CTRL_8723B 0x0074 69 + #define REG_AFE_XTAL_CTRL_EXT_8723B 0x0078 70 + #define REG_MCUFWDL_8723B 0x0080 71 71 #define REG_BT_PATCH_STATUS_8723B 0x0088 72 - #define REG_HIMR0_8723B 0x00B0 73 - #define REG_HISR0_8723B 0x00B4 74 - #define REG_HIMR1_8723B 0x00B8 75 - #define REG_HISR1_8723B 0x00BC 72 + #define REG_HIMR0_8723B 0x00B0 73 + #define REG_HISR0_8723B 0x00B4 74 + #define REG_HIMR1_8723B 0x00B8 75 + #define REG_HISR1_8723B 0x00BC 76 76 #define REG_PMC_DBG_CTRL2_8723B 0x00CC 77 77 #define REG_EFUSE_BURN_GNT_8723B 0x00CF 78 - #define REG_HPON_FSM_8723B 0x00EC 79 - #define REG_SYS_CFG_8723B 0x00F0 80 - #define REG_SYS_CFG1_8723B 0x00FC 81 - #define REG_ROM_VERSION 0x00FD 78 + #define REG_HPON_FSM_8723B 0x00EC 79 + #define REG_SYS_CFG_8723B 0x00F0 80 + #define REG_SYS_CFG1_8723B 0x00FC 81 + #define REG_ROM_VERSION 0x00FD 82 82 83 83 /* */ 84 84 /* */ 85 85 /* 0x0100h ~ 0x01FFh MACTOP General Configuration */ 86 86 /* */ 87 87 /* */ 88 - #define REG_CR_8723B 0x0100 89 - #define REG_PBP_8723B 0x0104 90 - #define REG_PKT_BUFF_ACCESS_CTRL_8723B 0x0106 88 + #define REG_CR_8723B 0x0100 89 + #define REG_PBP_8723B 0x0104 90 + #define REG_PKT_BUFF_ACCESS_CTRL_8723B 0x0106 91 91 #define REG_TRXDMA_CTRL_8723B 0x010C 92 92 #define REG_TRXFF_BNDY_8723B 0x0114 93 93 #define REG_TRXFF_STATUS_8723B 0x0118 94 - #define REG_RXFF_PTR_8723B 0x011C 95 - #define REG_CPWM_8723B 0x012F 96 - #define REG_FWIMR_8723B 0x0130 97 - #define REG_FWISR_8723B 0x0134 98 - #define REG_FTIMR_8723B 0x0138 94 + #define REG_RXFF_PTR_8723B 0x011C 95 + #define REG_CPWM_8723B 0x012F 96 + #define REG_FWIMR_8723B 0x0130 97 + #define REG_FWISR_8723B 0x0134 98 + #define REG_FTIMR_8723B 0x0138 99 99 #define REG_PKTBUF_DBG_CTRL_8723B 0x0140 100 - #define REG_RXPKTBUF_CTRL_8723B 0x0142 101 - #define REG_PKTBUF_DBG_DATA_L_8723B 0x0144 102 - #define REG_PKTBUF_DBG_DATA_H_8723B 0x0148 100 + #define REG_RXPKTBUF_CTRL_8723B 0x0142 101 + #define REG_PKTBUF_DBG_DATA_L_8723B 0x0144 102 + #define REG_PKTBUF_DBG_DATA_H_8723B 0x0148 103 103 104 - #define REG_TC0_CTRL_8723B 0x0150 105 - #define REG_TC1_CTRL_8723B 0x0154 106 - #define REG_TC2_CTRL_8723B 0x0158 107 - #define REG_TC3_CTRL_8723B 0x015C 108 - #define REG_TC4_CTRL_8723B 0x0160 104 + #define REG_TC0_CTRL_8723B 0x0150 105 + #define REG_TC1_CTRL_8723B 0x0154 106 + #define REG_TC2_CTRL_8723B 0x0158 107 + #define REG_TC3_CTRL_8723B 0x015C 108 + #define REG_TC4_CTRL_8723B 0x0160 109 109 #define REG_TCUNIT_BASE_8723B 0x0164 110 - #define REG_RSVD3_8723B 0x0168 111 - #define REG_C2HEVT_MSG_NORMAL_8723B 0x01A0 112 - #define REG_C2HEVT_CMD_SEQ_88XX 0x01A1 113 - #define REG_C2HEVT_CMD_CONTENT_88XX 0x01A2 114 - #define REG_C2HEVT_CMD_LEN_88XX 0x01AE 110 + #define REG_RSVD3_8723B 0x0168 111 + #define REG_C2HEVT_MSG_NORMAL_8723B 0x01A0 112 + #define REG_C2HEVT_CMD_SEQ_88XX 0x01A1 113 + #define REG_C2HEVT_CMD_CONTENT_88XX 0x01A2 114 + #define REG_C2HEVT_CMD_LEN_88XX 0x01AE 115 115 #define REG_C2HEVT_CLEAR_8723B 0x01AF 116 - #define REG_MCUTST_1_8723B 0x01C0 117 - #define REG_MCUTST_WOWLAN_8723B 0x01C7 118 - #define REG_FMETHR_8723B 0x01C8 119 - #define REG_HMETFR_8723B 0x01CC 120 - #define REG_HMEBOX_0_8723B 0x01D0 121 - #define REG_HMEBOX_1_8723B 0x01D4 122 - #define REG_HMEBOX_2_8723B 0x01D8 123 - #define REG_HMEBOX_3_8723B 0x01DC 124 - #define REG_LLT_INIT_8723B 0x01E0 116 + #define REG_MCUTST_1_8723B 0x01C0 117 + #define REG_MCUTST_WOWLAN_8723B 0x01C7 118 + #define REG_FMETHR_8723B 0x01C8 119 + #define REG_HMETFR_8723B 0x01CC 120 + #define REG_HMEBOX_0_8723B 0x01D0 121 + #define REG_HMEBOX_1_8723B 0x01D4 122 + #define REG_HMEBOX_2_8723B 0x01D8 123 + #define REG_HMEBOX_3_8723B 0x01DC 124 + #define REG_LLT_INIT_8723B 0x01E0 125 125 #define REG_HMEBOX_EXT0_8723B 0x01F0 126 126 #define REG_HMEBOX_EXT1_8723B 0x01F4 127 127 #define REG_HMEBOX_EXT2_8723B 0x01F8 ··· 132 132 /* 0x0200h ~ 0x027Fh TXDMA Configuration */ 133 133 /* */ 134 134 /* */ 135 - #define REG_RQPN_8723B 0x0200 136 - #define REG_FIFOPAGE_8723B 0x0204 135 + #define REG_RQPN_8723B 0x0200 136 + #define REG_FIFOPAGE_8723B 0x0204 137 137 #define REG_DWBCN0_CTRL_8723B REG_TDECTRL 138 - #define REG_TXDMA_OFFSET_CHK_8723B 0x020C 139 - #define REG_TXDMA_STATUS_8723B 0x0210 138 + #define REG_TXDMA_OFFSET_CHK_8723B 0x020C 139 + #define REG_TXDMA_STATUS_8723B 0x0210 140 140 #define REG_RQPN_NPQ_8723B 0x0214 141 141 #define REG_DWBCN1_CTRL_8723B 0x0228 142 142 ··· 146 146 /* */ 147 147 /* */ 148 148 #define REG_RXDMA_AGG_PG_TH_8723B 0x0280 149 - #define REG_FW_UPD_RDPTR_8723B 0x0284 /* FW shall update this register before FW write RXPKT_RELEASE_POLL to 1 */ 150 - #define REG_RXDMA_CONTROL_8723B 0x0286 /* Control the RX DMA. */ 149 + #define REG_FW_UPD_RDPTR_8723B 0x0284 /* FW shall update this register before FW write RXPKT_RELEASE_POLL to 1 */ 150 + #define REG_RXDMA_CONTROL_8723B 0x0286 /* Control the RX DMA. */ 151 151 #define REG_RXPKT_NUM_8723B 0x0287 /* The number of packets in RXPKTBUF. */ 152 152 #define REG_RXDMA_STATUS_8723B 0x0288 153 153 #define REG_RXDMA_PRO_8723B 0x0290 154 - #define REG_EARLY_MODE_CONTROL_8723B 0x02BC 155 - #define REG_RSVD5_8723B 0x02F0 156 - #define REG_RSVD6_8723B 0x02F4 154 + #define REG_EARLY_MODE_CONTROL_8723B 0x02BC 155 + #define REG_RSVD5_8723B 0x02F0 156 + #define REG_RSVD6_8723B 0x02F4 157 157 158 158 /* */ 159 159 /* */ 160 160 /* 0x0300h ~ 0x03FFh PCIe */ 161 161 /* */ 162 162 /* */ 163 - #define REG_PCIE_CTRL_REG_8723B 0x0300 164 - #define REG_INT_MIG_8723B 0x0304 /* Interrupt Migration */ 163 + #define REG_PCIE_CTRL_REG_8723B 0x0300 164 + #define REG_INT_MIG_8723B 0x0304 /* Interrupt Migration */ 165 165 #define REG_BCNQ_DESA_8723B 0x0308 /* TX Beacon Descriptor Address */ 166 - #define REG_HQ_DESA_8723B 0x0310 /* TX High Queue Descriptor Address */ 166 + #define REG_HQ_DESA_8723B 0x0310 /* TX High Queue Descriptor Address */ 167 167 #define REG_MGQ_DESA_8723B 0x0318 /* TX Manage Queue Descriptor Address */ 168 168 #define REG_VOQ_DESA_8723B 0x0320 /* TX VO Queue Descriptor Address */ 169 - #define REG_VIQ_DESA_8723B 0x0328 /* TX VI Queue Descriptor Address */ 169 + #define REG_VIQ_DESA_8723B 0x0328 /* TX VI Queue Descriptor Address */ 170 170 #define REG_BEQ_DESA_8723B 0x0330 /* TX BE Queue Descriptor Address */ 171 171 #define REG_BKQ_DESA_8723B 0x0338 /* TX BK Queue Descriptor Address */ 172 - #define REG_RX_DESA_8723B 0x0340 /* RX Queue Descriptor Address */ 172 + #define REG_RX_DESA_8723B 0x0340 /* RX Queue Descriptor Address */ 173 173 #define REG_DBI_WDATA_8723B 0x0348 /* DBI Write Data */ 174 174 #define REG_DBI_RDATA_8723B 0x034C /* DBI Read Data */ 175 - #define REG_DBI_ADDR_8723B 0x0350 /* DBI Address */ 176 - #define REG_DBI_FLAG_8723B 0x0352 /* DBI Read/Write Flag */ 177 - #define REG_MDIO_WDATA_8723B 0x0354 /* MDIO for Write PCIE PHY */ 175 + #define REG_DBI_ADDR_8723B 0x0350 /* DBI Address */ 176 + #define REG_DBI_FLAG_8723B 0x0352 /* DBI Read/Write Flag */ 177 + #define REG_MDIO_WDATA_8723B 0x0354 /* MDIO for Write PCIE PHY */ 178 178 #define REG_MDIO_RDATA_8723B 0x0356 /* MDIO for Reads PCIE PHY */ 179 179 #define REG_MDIO_CTL_8723B 0x0358 /* MDIO for Control */ 180 - #define REG_DBG_SEL_8723B 0x0360 /* Debug Selection Register */ 180 + #define REG_DBG_SEL_8723B 0x0360 /* Debug Selection Register */ 181 181 #define REG_PCIE_HRPWM_8723B 0x0361 /* PCIe RPWM */ 182 182 #define REG_PCIE_HCPWM_8723B 0x0363 /* PCIe CPWM */ 183 - #define REG_PCIE_MULTIFET_CTRL_8723B 0x036A /* PCIE Multi-Fethc Control */ 183 + #define REG_PCIE_MULTIFET_CTRL_8723B 0x036A /* PCIE Multi-Fethc Control */ 184 184 185 185 /* spec version 11 */ 186 186 /* */ ··· 194 194 #define REG_BKQ_INFORMATION_8723B 0x040C 195 195 #define REG_MGQ_INFORMATION_8723B 0x0410 196 196 #define REG_HGQ_INFORMATION_8723B 0x0414 197 - #define REG_BCNQ_INFORMATION_8723B 0x0418 197 + #define REG_BCNQ_INFORMATION_8723B 0x0418 198 198 #define REG_TXPKT_EMPTY_8723B 0x041A 199 199 200 - #define REG_FWHW_TXQ_CTRL_8723B 0x0420 200 + #define REG_FWHW_TXQ_CTRL_8723B 0x0420 201 201 #define REG_HWSEQ_CTRL_8723B 0x0423 202 - #define REG_TXPKTBUF_BCNQ_BDNY_8723B 0x0424 203 - #define REG_TXPKTBUF_MGQ_BDNY_8723B 0x0425 202 + #define REG_TXPKTBUF_BCNQ_BDNY_8723B 0x0424 203 + #define REG_TXPKTBUF_MGQ_BDNY_8723B 0x0425 204 204 #define REG_LIFECTRL_CTRL_8723B 0x0426 205 - #define REG_MULTI_BCNQ_OFFSET_8723B 0x0427 206 - #define REG_SPEC_SIFS_8723B 0x0428 207 - #define REG_RL_8723B 0x042A 208 - #define REG_TXBF_CTRL_8723B 0x042C 209 - #define REG_DARFRC_8723B 0x0430 210 - #define REG_RARFRC_8723B 0x0438 211 - #define REG_RRSR_8723B 0x0440 212 - #define REG_ARFR0_8723B 0x0444 213 - #define REG_ARFR1_8723B 0x044C 214 - #define REG_CCK_CHECK_8723B 0x0454 205 + #define REG_MULTI_BCNQ_OFFSET_8723B 0x0427 206 + #define REG_SPEC_SIFS_8723B 0x0428 207 + #define REG_RL_8723B 0x042A 208 + #define REG_TXBF_CTRL_8723B 0x042C 209 + #define REG_DARFRC_8723B 0x0430 210 + #define REG_RARFRC_8723B 0x0438 211 + #define REG_RRSR_8723B 0x0440 212 + #define REG_ARFR0_8723B 0x0444 213 + #define REG_ARFR1_8723B 0x044C 214 + #define REG_CCK_CHECK_8723B 0x0454 215 215 #define REG_AMPDU_MAX_TIME_8723B 0x0456 216 - #define REG_TXPKTBUF_BCNQ_BDNY1_8723B 0x0457 216 + #define REG_TXPKTBUF_BCNQ_BDNY1_8723B 0x0457 217 217 218 - #define REG_AMPDU_MAX_LENGTH_8723B 0x0458 218 + #define REG_AMPDU_MAX_LENGTH_8723B 0x0458 219 219 #define REG_TXPKTBUF_WMAC_LBK_BF_HD_8723B 0x045D 220 - #define REG_NDPA_OPT_CTRL_8723B 0x045F 220 + #define REG_NDPA_OPT_CTRL_8723B 0x045F 221 221 #define REG_FAST_EDCA_CTRL_8723B 0x0460 222 222 #define REG_RD_RESP_PKT_TH_8723B 0x0463 223 - #define REG_DATA_SC_8723B 0x0483 224 - #define REG_TXRPT_START_OFFSET 0x04AC 225 - #define REG_POWER_STAGE1_8723B 0x04B4 226 - #define REG_POWER_STAGE2_8723B 0x04B8 227 - #define REG_AMPDU_BURST_MODE_8723B 0x04BC 228 - #define REG_PKT_VO_VI_LIFE_TIME_8723B 0x04C0 229 - #define REG_PKT_BE_BK_LIFE_TIME_8723B 0x04C2 223 + #define REG_DATA_SC_8723B 0x0483 224 + #define REG_TXRPT_START_OFFSET 0x04AC 225 + #define REG_POWER_STAGE1_8723B 0x04B4 226 + #define REG_POWER_STAGE2_8723B 0x04B8 227 + #define REG_AMPDU_BURST_MODE_8723B 0x04BC 228 + #define REG_PKT_VO_VI_LIFE_TIME_8723B 0x04C0 229 + #define REG_PKT_BE_BK_LIFE_TIME_8723B 0x04C2 230 230 #define REG_STBC_SETTING_8723B 0x04C4 231 231 #define REG_HT_SINGLE_AMPDU_8723B 0x04C7 232 232 #define REG_PROT_MODE_CTRL_8723B 0x04C8 233 - #define REG_MAX_AGGR_NUM_8723B 0x04CA 234 - #define REG_RTS_MAX_AGGR_NUM_8723B 0x04CB 235 - #define REG_BAR_MODE_CTRL_8723B 0x04CC 236 - #define REG_RA_TRY_RATE_AGG_LMT_8723B 0x04CF 233 + #define REG_MAX_AGGR_NUM_8723B 0x04CA 234 + #define REG_RTS_MAX_AGGR_NUM_8723B 0x04CB 235 + #define REG_BAR_MODE_CTRL_8723B 0x04CC 236 + #define REG_RA_TRY_RATE_AGG_LMT_8723B 0x04CF 237 237 #define REG_MACID_PKT_DROP0_8723B 0x04D0 238 238 #define REG_MACID_PKT_SLEEP_8723B 0x04D4 239 239 ··· 242 242 /* 0x0500h ~ 0x05FFh EDCA Configuration */ 243 243 /* */ 244 244 /* */ 245 - #define REG_EDCA_VO_PARAM_8723B 0x0500 246 - #define REG_EDCA_VI_PARAM_8723B 0x0504 247 - #define REG_EDCA_BE_PARAM_8723B 0x0508 248 - #define REG_EDCA_BK_PARAM_8723B 0x050C 249 - #define REG_BCNTCFG_8723B 0x0510 250 - #define REG_PIFS_8723B 0x0512 251 - #define REG_RDG_PIFS_8723B 0x0513 252 - #define REG_SIFS_CTX_8723B 0x0514 253 - #define REG_SIFS_TRX_8723B 0x0516 245 + #define REG_EDCA_VO_PARAM_8723B 0x0500 246 + #define REG_EDCA_VI_PARAM_8723B 0x0504 247 + #define REG_EDCA_BE_PARAM_8723B 0x0508 248 + #define REG_EDCA_BK_PARAM_8723B 0x050C 249 + #define REG_BCNTCFG_8723B 0x0510 250 + #define REG_PIFS_8723B 0x0512 251 + #define REG_RDG_PIFS_8723B 0x0513 252 + #define REG_SIFS_CTX_8723B 0x0514 253 + #define REG_SIFS_TRX_8723B 0x0516 254 254 #define REG_AGGR_BREAK_TIME_8723B 0x051A 255 - #define REG_SLOT_8723B 0x051B 255 + #define REG_SLOT_8723B 0x051B 256 256 #define REG_TX_PTCL_CTRL_8723B 0x0520 257 - #define REG_TXPAUSE_8723B 0x0522 258 - #define REG_DIS_TXREQ_CLR_8723B 0x0523 259 - #define REG_RD_CTRL_8723B 0x0524 257 + #define REG_TXPAUSE_8723B 0x0522 258 + #define REG_DIS_TXREQ_CLR_8723B 0x0523 259 + #define REG_RD_CTRL_8723B 0x0524 260 260 /* */ 261 261 /* Format for offset 540h-542h: */ 262 262 /* [3:0]: TBTT prohibit setup in unit of 32us. The time for HW getting beacon content before TBTT. */ ··· 272 272 /* Note: We cannot update beacon content to HW or send any AC packets during the time between Setup and Hold. */ 273 273 /* Described by Designer Tim and Bruce, 2011-01-14. */ 274 274 /* */ 275 - #define REG_TBTT_PROHIBIT_8723B 0x0540 276 - #define REG_RD_NAV_NXT_8723B 0x0544 277 - #define REG_NAV_PROT_LEN_8723B 0x0546 278 - #define REG_BCN_CTRL_8723B 0x0550 279 - #define REG_BCN_CTRL_1_8723B 0x0551 280 - #define REG_MBID_NUM_8723B 0x0552 281 - #define REG_DUAL_TSF_RST_8723B 0x0553 282 - #define REG_BCN_INTERVAL_8723B 0x0554 283 - #define REG_DRVERLYINT_8723B 0x0558 284 - #define REG_BCNDMATIM_8723B 0x0559 285 - #define REG_ATIMWND_8723B 0x055A 286 - #define REG_USTIME_TSF_8723B 0x055C 287 - #define REG_BCN_MAX_ERR_8723B 0x055D 288 - #define REG_RXTSF_OFFSET_CCK_8723B 0x055E 289 - #define REG_RXTSF_OFFSET_OFDM_8723B 0x055F 290 - #define REG_TSFTR_8723B 0x0560 291 - #define REG_CTWND_8723B 0x0572 292 - #define REG_SECONDARY_CCA_CTRL_8723B 0x0577 293 - #define REG_PSTIMER_8723B 0x0580 294 - #define REG_TIMER0_8723B 0x0584 295 - #define REG_TIMER1_8723B 0x0588 296 - #define REG_ACMHWCTRL_8723B 0x05C0 297 - #define REG_SCH_TXCMD_8723B 0x05F8 275 + #define REG_TBTT_PROHIBIT_8723B 0x0540 276 + #define REG_RD_NAV_NXT_8723B 0x0544 277 + #define REG_NAV_PROT_LEN_8723B 0x0546 278 + #define REG_BCN_CTRL_8723B 0x0550 279 + #define REG_BCN_CTRL_1_8723B 0x0551 280 + #define REG_MBID_NUM_8723B 0x0552 281 + #define REG_DUAL_TSF_RST_8723B 0x0553 282 + #define REG_BCN_INTERVAL_8723B 0x0554 283 + #define REG_DRVERLYINT_8723B 0x0558 284 + #define REG_BCNDMATIM_8723B 0x0559 285 + #define REG_ATIMWND_8723B 0x055A 286 + #define REG_USTIME_TSF_8723B 0x055C 287 + #define REG_BCN_MAX_ERR_8723B 0x055D 288 + #define REG_RXTSF_OFFSET_CCK_8723B 0x055E 289 + #define REG_RXTSF_OFFSET_OFDM_8723B 0x055F 290 + #define REG_TSFTR_8723B 0x0560 291 + #define REG_CTWND_8723B 0x0572 292 + #define REG_SECONDARY_CCA_CTRL_8723B 0x0577 293 + #define REG_PSTIMER_8723B 0x0580 294 + #define REG_TIMER0_8723B 0x0584 295 + #define REG_TIMER1_8723B 0x0588 296 + #define REG_ACMHWCTRL_8723B 0x05C0 297 + #define REG_SCH_TXCMD_8723B 0x05F8 298 298 299 299 /* 0x0600h ~ 0x07FFh WMAC Configuration */ 300 - #define REG_MAC_CR_8723B 0x0600 301 - #define REG_TCR_8723B 0x0604 302 - #define REG_RCR_8723B 0x0608 303 - #define REG_RX_PKT_LIMIT_8723B 0x060C 304 - #define REG_RX_DLK_TIME_8723B 0x060D 305 - #define REG_RX_DRVINFO_SZ_8723B 0x060F 300 + #define REG_MAC_CR_8723B 0x0600 301 + #define REG_TCR_8723B 0x0604 302 + #define REG_RCR_8723B 0x0608 303 + #define REG_RX_PKT_LIMIT_8723B 0x060C 304 + #define REG_RX_DLK_TIME_8723B 0x060D 305 + #define REG_RX_DRVINFO_SZ_8723B 0x060F 306 306 307 - #define REG_MACID_8723B 0x0610 308 - #define REG_BSSID_8723B 0x0618 309 - #define REG_MAR_8723B 0x0620 310 - #define REG_MBIDCAMCFG_8723B 0x0628 307 + #define REG_MACID_8723B 0x0610 308 + #define REG_BSSID_8723B 0x0618 309 + #define REG_MAR_8723B 0x0620 310 + #define REG_MBIDCAMCFG_8723B 0x0628 311 311 312 - #define REG_USTIME_EDCA_8723B 0x0638 313 - #define REG_MAC_SPEC_SIFS_8723B 0x063A 314 - #define REG_RESP_SIFP_CCK_8723B 0x063C 315 - #define REG_RESP_SIFS_OFDM_8723B 0x063E 316 - #define REG_ACKTO_8723B 0x0640 317 - #define REG_CTS2TO_8723B 0x0641 318 - #define REG_EIFS_8723B 0x0642 312 + #define REG_USTIME_EDCA_8723B 0x0638 313 + #define REG_MAC_SPEC_SIFS_8723B 0x063A 314 + #define REG_RESP_SIFP_CCK_8723B 0x063C 315 + #define REG_RESP_SIFS_OFDM_8723B 0x063E 316 + #define REG_ACKTO_8723B 0x0640 317 + #define REG_CTS2TO_8723B 0x0641 318 + #define REG_EIFS_8723B 0x0642 319 319 320 - #define REG_NAV_UPPER_8723B 0x0652 /* unit of 128 */ 321 - #define REG_TRXPTCL_CTL_8723B 0x0668 320 + #define REG_NAV_UPPER_8723B 0x0652 /* unit of 128 */ 321 + #define REG_TRXPTCL_CTL_8723B 0x0668 322 322 323 323 /* Security */ 324 - #define REG_CAMCMD_8723B 0x0670 325 - #define REG_CAMWRITE_8723B 0x0674 326 - #define REG_CAMREAD_8723B 0x0678 327 - #define REG_CAMDBG_8723B 0x067C 328 - #define REG_SECCFG_8723B 0x0680 324 + #define REG_CAMCMD_8723B 0x0670 325 + #define REG_CAMWRITE_8723B 0x0674 326 + #define REG_CAMREAD_8723B 0x0678 327 + #define REG_CAMDBG_8723B 0x067C 328 + #define REG_SECCFG_8723B 0x0680 329 329 330 330 /* Power */ 331 - #define REG_WOW_CTRL_8723B 0x0690 332 - #define REG_PS_RX_INFO_8723B 0x0692 333 - #define REG_UAPSD_TID_8723B 0x0693 334 - #define REG_WKFMCAM_CMD_8723B 0x0698 335 - #define REG_WKFMCAM_NUM_8723B 0x0698 336 - #define REG_WKFMCAM_RWD_8723B 0x069C 337 - #define REG_RXFLTMAP0_8723B 0x06A0 338 - #define REG_RXFLTMAP1_8723B 0x06A2 339 - #define REG_RXFLTMAP2_8723B 0x06A4 340 - #define REG_BCN_PSR_RPT_8723B 0x06A8 341 - #define REG_BT_COEX_TABLE_8723B 0x06C0 342 - #define REG_BFMER0_INFO_8723B 0x06E4 343 - #define REG_BFMER1_INFO_8723B 0x06EC 344 - #define REG_CSI_RPT_PARAM_BW20_8723B 0x06F4 345 - #define REG_CSI_RPT_PARAM_BW40_8723B 0x06F8 346 - #define REG_CSI_RPT_PARAM_BW80_8723B 0x06FC 331 + #define REG_WOW_CTRL_8723B 0x0690 332 + #define REG_PS_RX_INFO_8723B 0x0692 333 + #define REG_UAPSD_TID_8723B 0x0693 334 + #define REG_WKFMCAM_CMD_8723B 0x0698 335 + #define REG_WKFMCAM_NUM_8723B 0x0698 336 + #define REG_WKFMCAM_RWD_8723B 0x069C 337 + #define REG_RXFLTMAP0_8723B 0x06A0 338 + #define REG_RXFLTMAP1_8723B 0x06A2 339 + #define REG_RXFLTMAP2_8723B 0x06A4 340 + #define REG_BCN_PSR_RPT_8723B 0x06A8 341 + #define REG_BT_COEX_TABLE_8723B 0x06C0 342 + #define REG_BFMER0_INFO_8723B 0x06E4 343 + #define REG_BFMER1_INFO_8723B 0x06EC 344 + #define REG_CSI_RPT_PARAM_BW20_8723B 0x06F4 345 + #define REG_CSI_RPT_PARAM_BW40_8723B 0x06F8 346 + #define REG_CSI_RPT_PARAM_BW80_8723B 0x06FC 347 347 348 348 /* Hardware Port 2 */ 349 - #define REG_MACID1_8723B 0x0700 350 - #define REG_BSSID1_8723B 0x0708 351 - #define REG_BFMEE_SEL_8723B 0x0714 352 - #define REG_SND_PTCL_CTRL_8723B 0x0718 349 + #define REG_MACID1_8723B 0x0700 350 + #define REG_BSSID1_8723B 0x0708 351 + #define REG_BFMEE_SEL_8723B 0x0714 352 + #define REG_SND_PTCL_CTRL_8723B 0x0718 353 353 354 354 /* Redifine 8192C register definition for compatibility */ 355 355