tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux
fork atom

drm/amdgpu: use register distance member instead of hardcode in gfxhub v2

This patch updates to use register distance member instead of hardcode
in gfxhub v2.

Signed-off-by: Huang Rui <ray.huang@amd.com>
Tested-by: AnZhong Huang <anzhong.huang@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

authored by

Huang Rui and committed by
Alex Deucher 1e40eebe 8c471360

+24 -15
+24 -15
drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c
··· 49 49 void gfxhub_v2_0_setup_vm_pt_regs(struct amdgpu_device *adev, uint32_t vmid, 50 50 uint64_t page_table_base) 51 51 { 52 - /* two registers distance between mmGCVM_CONTEXT0_* to mmGCVM_CONTEXT1_* */ 53 - int offset = mmGCVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 54 - - mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32; 52 + struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0]; 55 53 56 54 WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32, 57 - offset * vmid, lower_32_bits(page_table_base)); 55 + hub->ctx_addr_distance * vmid, 56 + lower_32_bits(page_table_base)); 58 57 59 58 WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32, 60 - offset * vmid, upper_32_bits(page_table_base)); 59 + hub->ctx_addr_distance * vmid, 60 + upper_32_bits(page_table_base)); 61 61 } 62 62 63 63 static void gfxhub_v2_0_init_gart_aperture_regs(struct amdgpu_device *adev) ··· 218 218 219 219 static void gfxhub_v2_0_setup_vmid_config(struct amdgpu_device *adev) 220 220 { 221 + struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0]; 221 222 int i; 222 223 uint32_t tmp; 223 224 ··· 248 247 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, 249 248 RETRY_PERMISSION_OR_INVALID_PAGE_FAULT, 250 249 !amdgpu_noretry); 251 - WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT1_CNTL, i, tmp); 252 - WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32, i*2, 0); 253 - WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32, i*2, 0); 254 - WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32, i*2, 255 - lower_32_bits(adev->vm_manager.max_pfn - 1)); 256 - WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32, i*2, 257 - upper_32_bits(adev->vm_manager.max_pfn - 1)); 250 + WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT1_CNTL, 251 + i * hub->ctx_distance, tmp); 252 + WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32, 253 + i * hub->ctx_addr_distance, 0); 254 + WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32, 255 + i * hub->ctx_addr_distance, 0); 256 + WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32, 257 + i * hub->ctx_addr_distance, 258 + lower_32_bits(adev->vm_manager.max_pfn - 1)); 259 + WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32, 260 + i * hub->ctx_addr_distance, 261 + upper_32_bits(adev->vm_manager.max_pfn - 1)); 258 262 } 259 263 } 260 264 261 265 static void gfxhub_v2_0_program_invalidation(struct amdgpu_device *adev) 262 266 { 267 + struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0]; 263 268 unsigned i; 264 269 265 270 for (i = 0 ; i < 18; ++i) { 266 271 WREG32_SOC15_OFFSET(GC, 0, mmGCVM_INVALIDATE_ENG0_ADDR_RANGE_LO32, 267 - 2 * i, 0xffffffff); 272 + i * hub->eng_addr_distance, 0xffffffff); 268 273 WREG32_SOC15_OFFSET(GC, 0, mmGCVM_INVALIDATE_ENG0_ADDR_RANGE_HI32, 269 - 2 * i, 0x1f); 274 + i * hub->eng_addr_distance, 0x1f); 270 275 } 271 276 } 272 277 ··· 294 287 295 288 void gfxhub_v2_0_gart_disable(struct amdgpu_device *adev) 296 289 { 290 + struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0]; 297 291 u32 tmp; 298 292 u32 i; 299 293 300 294 /* Disable all tables */ 301 295 for (i = 0; i < 16; i++) 302 - WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT0_CNTL, i, 0); 296 + WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT0_CNTL, 297 + i * hub->ctx_distance, 0); 303 298 304 299 /* Setup TLB control */ 305 300 tmp = RREG32_SOC15(GC, 0, mmGCMC_VM_MX_L1_TLB_CNTL);