drm/i915/hotplug: convert intel_hotplug_irq.[ch] to struct intel_display

+2 -2

drivers/gpu/drm/i915/display/intel_crt.c

··· 606 606 607 607 for (i = 0; i < tries ; i++) { 608 608 /* turn on the FORCE_DETECT */ 609 - i915_hotplug_interrupt_update(dev_priv, 609 + i915_hotplug_interrupt_update(display, 610 610 CRT_HOTPLUG_FORCE_DETECT, 611 611 CRT_HOTPLUG_FORCE_DETECT); 612 612 /* wait for FORCE_DETECT to go off */ ··· 624 624 intel_de_write(display, PORT_HOTPLUG_STAT(display), 625 625 CRT_HOTPLUG_INT_STATUS); 626 626 627 - i915_hotplug_interrupt_update(dev_priv, CRT_HOTPLUG_FORCE_DETECT, 0); 627 + i915_hotplug_interrupt_update(display, CRT_HOTPLUG_FORCE_DETECT, 0); 628 628 629 629 return ret; 630 630 }

+17 -16

drivers/gpu/drm/i915/display/intel_display_irq.c

··· 675 675 enum pipe pipe; 676 676 u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK; 677 677 678 - ibx_hpd_irq_handler(dev_priv, hotplug_trigger); 678 + ibx_hpd_irq_handler(display, hotplug_trigger); 679 679 680 680 if (pch_iir & SDE_AUDIO_POWER_MASK) { 681 681 int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK) >> ··· 812 812 enum pipe pipe; 813 813 u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_CPT; 814 814 815 - ibx_hpd_irq_handler(dev_priv, hotplug_trigger); 815 + ibx_hpd_irq_handler(display, hotplug_trigger); 816 816 817 817 if (pch_iir & SDE_AUDIO_POWER_MASK_CPT) { 818 818 int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK_CPT) >> ··· 901 901 u32 hotplug_trigger = de_iir & DE_DP_A_HOTPLUG; 902 902 903 903 if (hotplug_trigger) 904 - ilk_hpd_irq_handler(dev_priv, hotplug_trigger); 904 + ilk_hpd_irq_handler(display, hotplug_trigger); 905 905 906 906 if (de_iir & DE_AUX_CHANNEL_A) 907 907 intel_dp_aux_irq_handler(display); ··· 953 953 u32 hotplug_trigger = de_iir & DE_DP_A_HOTPLUG_IVB; 954 954 955 955 if (hotplug_trigger) 956 - ilk_hpd_irq_handler(dev_priv, hotplug_trigger); 956 + ilk_hpd_irq_handler(display, hotplug_trigger); 957 957 958 958 if (de_iir & DE_ERR_INT_IVB) 959 959 ivb_err_int_handler(dev_priv); ··· 1382 1382 iir = intel_de_read(display, GEN11_DE_HPD_IIR); 1383 1383 if (iir) { 1384 1384 intel_de_write(display, GEN11_DE_HPD_IIR, iir); 1385 - gen11_hpd_irq_handler(dev_priv, iir); 1385 + gen11_hpd_irq_handler(display, iir); 1386 1386 } else { 1387 1387 drm_err_ratelimited(&dev_priv->drm, 1388 1388 "The master control interrupt lied, (DE HPD)!\n"); ··· 1405 1405 u32 hotplug_trigger = iir & BXT_DE_PORT_HOTPLUG_MASK; 1406 1406 1407 1407 if (hotplug_trigger) { 1408 - bxt_hpd_irq_handler(dev_priv, hotplug_trigger); 1408 + bxt_hpd_irq_handler(display, hotplug_trigger); 1409 1409 found = true; 1410 1410 } 1411 1411 } else if (IS_BROADWELL(dev_priv)) { 1412 1412 u32 hotplug_trigger = iir & BDW_DE_PORT_HOTPLUG_MASK; 1413 1413 1414 1414 if (hotplug_trigger) { 1415 - ilk_hpd_irq_handler(dev_priv, hotplug_trigger); 1415 + ilk_hpd_irq_handler(display, hotplug_trigger); 1416 1416 found = true; 1417 1417 } 1418 1418 } ··· 1498 1498 gen8_read_and_ack_pch_irqs(dev_priv, &iir, &pica_iir); 1499 1499 if (iir) { 1500 1500 if (pica_iir) 1501 - xelpdp_pica_irq_handler(dev_priv, pica_iir); 1501 + xelpdp_pica_irq_handler(display, pica_iir); 1502 1502 1503 1503 if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP) 1504 - icp_irq_handler(dev_priv, iir); 1504 + icp_irq_handler(display, iir); 1505 1505 else if (INTEL_PCH_TYPE(dev_priv) >= PCH_SPT) 1506 - spt_irq_handler(dev_priv, iir); 1506 + spt_irq_handler(display, iir); 1507 1507 else 1508 1508 cpt_irq_handler(dev_priv, iir); 1509 1509 } else { ··· 1904 1904 gen2_error_reset(to_intel_uncore(display->drm), 1905 1905 VLV_ERROR_REGS); 1906 1906 1907 - i915_hotplug_interrupt_update_locked(dev_priv, 0xffffffff, 0); 1907 + i915_hotplug_interrupt_update_locked(display, 0xffffffff, 0); 1908 1908 intel_de_rmw(display, PORT_HOTPLUG_STAT(dev_priv), 0, 0); 1909 1909 1910 1910 i9xx_pipestat_irq_reset(dev_priv); ··· 1924 1924 struct intel_display *display = &i915->display; 1925 1925 1926 1926 if (I915_HAS_HOTPLUG(i915)) { 1927 - i915_hotplug_interrupt_update(i915, 0xffffffff, 0); 1927 + i915_hotplug_interrupt_update(display, 0xffffffff, 0); 1928 1928 intel_de_rmw(display, PORT_HOTPLUG_STAT(i915), 0, 0); 1929 1929 } 1930 1930 ··· 2348 2348 2349 2349 void intel_display_irq_init(struct drm_i915_private *i915) 2350 2350 { 2351 - i915->drm.vblank_disable_immediate = true; 2351 + struct intel_display *display = &i915->display; 2352 2352 2353 - intel_hotplug_irq_init(i915); 2353 + display->drm->vblank_disable_immediate = true; 2354 2354 2355 - INIT_WORK(&i915->display.irq.vblank_dc_work, 2356 - intel_display_vblank_dc_work); 2355 + intel_hotplug_irq_init(display); 2356 + 2357 + INIT_WORK(&display->irq.vblank_dc_work, intel_display_vblank_dc_work); 2357 2358 }

+3 -3

drivers/gpu/drm/i915/display/intel_hotplug.c

··· 305 305 display->hotplug.stats[pin].state = HPD_ENABLED; 306 306 } 307 307 308 - intel_hpd_irq_setup(dev_priv); 308 + intel_hpd_irq_setup(display); 309 309 310 310 spin_unlock_irq(&dev_priv->irq_lock); 311 311 ··· 696 696 * happens later in our hotplug work. 697 697 */ 698 698 if (storm_detected) 699 - intel_hpd_irq_setup(dev_priv); 699 + intel_hpd_irq_setup(display); 700 700 701 701 /* 702 702 * Our hotplug handler can grab modeset locks (by calling down into the ··· 745 745 * just to make the assert_spin_locked checks happy. 746 746 */ 747 747 spin_lock_irq(&dev_priv->irq_lock); 748 - intel_hpd_irq_setup(dev_priv); 748 + intel_hpd_irq_setup(display); 749 749 spin_unlock_irq(&dev_priv->irq_lock); 750 750 } 751 751

+230 -244

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

··· 131 131 [HPD_PORT_TC4] = SDE_TC_HOTPLUG_ICP(HPD_PORT_TC4), 132 132 }; 133 133 134 - static void intel_hpd_init_pins(struct drm_i915_private *dev_priv) 134 + static void intel_hpd_init_pins(struct intel_display *display) 135 135 { 136 - struct intel_hotplug *hpd = &dev_priv->display.hotplug; 136 + struct drm_i915_private *dev_priv = to_i915(display->drm); 137 + struct intel_hotplug *hpd = &display->hotplug; 137 138 138 - if (HAS_GMCH(dev_priv)) { 139 - if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) || 140 - IS_CHERRYVIEW(dev_priv)) 139 + if (HAS_GMCH(display)) { 140 + if (display->platform.g4x || display->platform.valleyview || 141 + display->platform.cherryview) 141 142 hpd->hpd = hpd_status_g4x; 142 143 else 143 144 hpd->hpd = hpd_status_i915; 144 145 return; 145 146 } 146 147 147 - if (DISPLAY_VER(dev_priv) >= 14) 148 + if (DISPLAY_VER(display) >= 14) 148 149 hpd->hpd = hpd_xelpdp; 149 - else if (DISPLAY_VER(dev_priv) >= 11) 150 + else if (DISPLAY_VER(display) >= 11) 150 151 hpd->hpd = hpd_gen11; 151 - else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) 152 + else if (display->platform.geminilake || display->platform.broxton) 152 153 hpd->hpd = hpd_bxt; 153 - else if (DISPLAY_VER(dev_priv) == 9) 154 + else if (DISPLAY_VER(display) == 9) 154 155 hpd->hpd = NULL; /* no north HPD on SKL */ 155 - else if (DISPLAY_VER(dev_priv) >= 8) 156 + else if (DISPLAY_VER(display) >= 8) 156 157 hpd->hpd = hpd_bdw; 157 - else if (DISPLAY_VER(dev_priv) >= 7) 158 + else if (DISPLAY_VER(display) >= 7) 158 159 hpd->hpd = hpd_ivb; 159 160 else 160 161 hpd->hpd = hpd_ilk; ··· 181 180 } 182 181 183 182 /* For display hotplug interrupt */ 184 - void i915_hotplug_interrupt_update_locked(struct drm_i915_private *dev_priv, 183 + void i915_hotplug_interrupt_update_locked(struct intel_display *display, 185 184 u32 mask, u32 bits) 186 185 { 187 - struct intel_display *display = &dev_priv->display; 186 + struct drm_i915_private *dev_priv = to_i915(display->drm); 188 187 189 188 lockdep_assert_held(&dev_priv->irq_lock); 190 - drm_WARN_ON(&dev_priv->drm, bits & ~mask); 189 + drm_WARN_ON(display->drm, bits & ~mask); 191 190 192 191 intel_de_rmw(display, PORT_HOTPLUG_EN(display), mask, bits); 193 192 } 194 193 195 194 /** 196 195 * i915_hotplug_interrupt_update - update hotplug interrupt enable 197 - * @dev_priv: driver private 196 + * @display: display device 198 197 * @mask: bits to update 199 198 * @bits: bits to enable 200 199 * NOTE: the HPD enable bits are modified both inside and outside ··· 204 203 * held already, this function acquires the lock itself. A non-locking 205 204 * version is also available. 206 205 */ 207 - void i915_hotplug_interrupt_update(struct drm_i915_private *dev_priv, 206 + void i915_hotplug_interrupt_update(struct intel_display *display, 208 207 u32 mask, 209 208 u32 bits) 210 209 { 210 + struct drm_i915_private *dev_priv = to_i915(display->drm); 211 + 211 212 spin_lock_irq(&dev_priv->irq_lock); 212 - i915_hotplug_interrupt_update_locked(dev_priv, mask, bits); 213 + i915_hotplug_interrupt_update_locked(display, mask, bits); 213 214 spin_unlock_irq(&dev_priv->irq_lock); 214 215 } 215 216 ··· 343 340 * 344 341 * Note that the caller is expected to zero out the masks initially. 345 342 */ 346 - static void intel_get_hpd_pins(struct drm_i915_private *dev_priv, 343 + static void intel_get_hpd_pins(struct intel_display *display, 347 344 u32 *pin_mask, u32 *long_mask, 348 345 u32 hotplug_trigger, u32 dig_hotplug_reg, 349 346 const u32 hpd[HPD_NUM_PINS], ··· 363 360 *long_mask |= BIT(pin); 364 361 } 365 362 366 - drm_dbg(&dev_priv->drm, 367 - "hotplug event received, stat 0x%08x, dig 0x%08x, pins 0x%08x, long 0x%08x\n", 368 - hotplug_trigger, dig_hotplug_reg, *pin_mask, *long_mask); 363 + drm_dbg_kms(display->drm, 364 + "hotplug event received, stat 0x%08x, dig 0x%08x, pins 0x%08x, long 0x%08x\n", 365 + hotplug_trigger, dig_hotplug_reg, *pin_mask, *long_mask); 369 366 } 370 367 371 - static u32 intel_hpd_enabled_irqs(struct drm_i915_private *dev_priv, 368 + static u32 intel_hpd_enabled_irqs(struct intel_display *display, 372 369 const u32 hpd[HPD_NUM_PINS]) 373 370 { 374 371 struct intel_encoder *encoder; 375 372 u32 enabled_irqs = 0; 376 373 377 - for_each_intel_encoder(&dev_priv->drm, encoder) 378 - if (dev_priv->display.hotplug.stats[encoder->hpd_pin].state == HPD_ENABLED) 374 + for_each_intel_encoder(display->drm, encoder) 375 + if (display->hotplug.stats[encoder->hpd_pin].state == HPD_ENABLED) 379 376 enabled_irqs |= hpd[encoder->hpd_pin]; 380 377 381 378 return enabled_irqs; 382 379 } 383 380 384 - static u32 intel_hpd_hotplug_irqs(struct drm_i915_private *dev_priv, 381 + static u32 intel_hpd_hotplug_irqs(struct intel_display *display, 385 382 const u32 hpd[HPD_NUM_PINS]) 386 383 { 387 384 struct intel_encoder *encoder; 388 385 u32 hotplug_irqs = 0; 389 386 390 - for_each_intel_encoder(&dev_priv->drm, encoder) 387 + for_each_intel_encoder(display->drm, encoder) 391 388 hotplug_irqs |= hpd[encoder->hpd_pin]; 392 389 393 390 return hotplug_irqs; 394 391 } 395 392 396 - static u32 intel_hpd_hotplug_mask(struct drm_i915_private *i915, 393 + static u32 intel_hpd_hotplug_mask(struct intel_display *display, 397 394 hotplug_mask_func hotplug_mask) 398 395 { 399 396 enum hpd_pin pin; ··· 405 402 return hotplug; 406 403 } 407 404 408 - static u32 intel_hpd_hotplug_enables(struct drm_i915_private *i915, 405 + static u32 intel_hpd_hotplug_enables(struct intel_display *display, 409 406 hotplug_enables_func hotplug_enables) 410 407 { 411 408 struct intel_encoder *encoder; 412 409 u32 hotplug = 0; 413 410 414 - for_each_intel_encoder(&i915->drm, encoder) 411 + for_each_intel_encoder(display->drm, encoder) 415 412 hotplug |= hotplug_enables(encoder); 416 413 417 414 return hotplug; 418 415 } 419 416 420 - u32 i9xx_hpd_irq_ack(struct drm_i915_private *dev_priv) 417 + u32 i9xx_hpd_irq_ack(struct intel_display *display) 421 418 { 422 - struct intel_display *display = &dev_priv->display; 423 419 u32 hotplug_status = 0, hotplug_status_mask; 424 420 int i; 425 421 426 - if (IS_G4X(dev_priv) || 427 - IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) 422 + if (display->platform.g4x || 423 + display->platform.valleyview || display->platform.cherryview) 428 424 hotplug_status_mask = HOTPLUG_INT_STATUS_G4X | 429 425 DP_AUX_CHANNEL_MASK_INT_STATUS_G4X; 430 426 else ··· 450 448 hotplug_status); 451 449 } 452 450 453 - drm_WARN_ONCE(&dev_priv->drm, 1, 451 + drm_WARN_ONCE(display->drm, 1, 454 452 "PORT_HOTPLUG_STAT did not clear (0x%08x)\n", 455 453 intel_de_read(display, PORT_HOTPLUG_STAT(display))); 456 454 457 455 return hotplug_status; 458 456 } 459 457 460 - void i9xx_hpd_irq_handler(struct drm_i915_private *dev_priv, u32 hotplug_status) 458 + void i9xx_hpd_irq_handler(struct intel_display *display, u32 hotplug_status) 461 459 { 462 - struct intel_display *display = &dev_priv->display; 463 460 u32 pin_mask = 0, long_mask = 0; 464 461 u32 hotplug_trigger; 465 462 466 - if (IS_G4X(dev_priv) || 467 - IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) 463 + if (display->platform.g4x || 464 + display->platform.valleyview || display->platform.cherryview) 468 465 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_G4X; 469 466 else 470 467 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_I915; 471 468 472 469 if (hotplug_trigger) { 473 - intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask, 470 + intel_get_hpd_pins(display, &pin_mask, &long_mask, 474 471 hotplug_trigger, hotplug_trigger, 475 - dev_priv->display.hotplug.hpd, 472 + display->hotplug.hpd, 476 473 i9xx_port_hotplug_long_detect); 477 474 478 475 intel_hpd_irq_handler(display, pin_mask, long_mask); 479 476 } 480 477 481 - if ((IS_G4X(dev_priv) || 482 - IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && 478 + if ((display->platform.g4x || 479 + display->platform.valleyview || display->platform.cherryview) && 483 480 hotplug_status & DP_AUX_CHANNEL_MASK_INT_STATUS_G4X) 484 481 intel_dp_aux_irq_handler(display); 485 482 } 486 483 487 - void ibx_hpd_irq_handler(struct drm_i915_private *dev_priv, u32 hotplug_trigger) 484 + void ibx_hpd_irq_handler(struct intel_display *display, u32 hotplug_trigger) 488 485 { 489 - struct intel_display *display = &dev_priv->display; 490 486 u32 dig_hotplug_reg, pin_mask = 0, long_mask = 0; 491 487 492 488 /* ··· 506 506 if (!hotplug_trigger) 507 507 return; 508 508 509 - intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask, 509 + intel_get_hpd_pins(display, &pin_mask, &long_mask, 510 510 hotplug_trigger, dig_hotplug_reg, 511 - dev_priv->display.hotplug.pch_hpd, 511 + display->hotplug.pch_hpd, 512 512 pch_port_hotplug_long_detect); 513 513 514 514 intel_hpd_irq_handler(display, pin_mask, long_mask); 515 515 } 516 516 517 - void xelpdp_pica_irq_handler(struct drm_i915_private *i915, u32 iir) 517 + void xelpdp_pica_irq_handler(struct intel_display *display, u32 iir) 518 518 { 519 - struct intel_display *display = &i915->display; 520 519 enum hpd_pin pin; 521 520 u32 hotplug_trigger = iir & (XELPDP_DP_ALT_HOTPLUG_MASK | XELPDP_TBT_HOTPLUG_MASK); 522 521 u32 trigger_aux = iir & XELPDP_AUX_TC_MASK; 523 522 u32 pin_mask = 0, long_mask = 0; 524 523 525 - if (DISPLAY_VER(i915) >= 20) 524 + if (DISPLAY_VER(display) >= 20) 526 525 trigger_aux |= iir & XE2LPD_AUX_DDI_MASK; 527 526 528 527 for (pin = HPD_PORT_TC1; pin <= HPD_PORT_TC4; pin++) { 529 528 u32 val; 530 529 531 - if (!(i915->display.hotplug.hpd[pin] & hotplug_trigger)) 530 + if (!(display->hotplug.hpd[pin] & hotplug_trigger)) 532 531 continue; 533 532 534 533 pin_mask |= BIT(pin); 535 534 536 - val = intel_de_read(i915, XELPDP_PORT_HOTPLUG_CTL(pin)); 537 - intel_de_write(i915, XELPDP_PORT_HOTPLUG_CTL(pin), val); 535 + val = intel_de_read(display, XELPDP_PORT_HOTPLUG_CTL(pin)); 536 + intel_de_write(display, XELPDP_PORT_HOTPLUG_CTL(pin), val); 538 537 539 538 if (val & (XELPDP_DP_ALT_HPD_LONG_DETECT | XELPDP_TBT_HPD_LONG_DETECT)) 540 539 long_mask |= BIT(pin); 541 540 } 542 541 543 542 if (pin_mask) { 544 - drm_dbg(&i915->drm, 545 - "pica hotplug event received, stat 0x%08x, pins 0x%08x, long 0x%08x\n", 546 - hotplug_trigger, pin_mask, long_mask); 543 + drm_dbg_kms(display->drm, 544 + "pica hotplug event received, stat 0x%08x, pins 0x%08x, long 0x%08x\n", 545 + hotplug_trigger, pin_mask, long_mask); 547 546 548 547 intel_hpd_irq_handler(display, pin_mask, long_mask); 549 548 } ··· 551 552 intel_dp_aux_irq_handler(display); 552 553 553 554 if (!pin_mask && !trigger_aux) 554 - drm_err(&i915->drm, 555 + drm_err(display->drm, 555 556 "Unexpected DE HPD/AUX interrupt 0x%08x\n", iir); 556 557 } 557 558 558 - void icp_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir) 559 + void icp_irq_handler(struct intel_display *display, u32 pch_iir) 559 560 { 560 - struct intel_display *display = &dev_priv->display; 561 + struct drm_i915_private *dev_priv = to_i915(display->drm); 561 562 u32 ddi_hotplug_trigger = pch_iir & SDE_DDI_HOTPLUG_MASK_ICP; 562 563 u32 tc_hotplug_trigger = pch_iir & SDE_TC_HOTPLUG_MASK_ICP; 563 564 u32 pin_mask = 0, long_mask = 0; ··· 570 571 dig_hotplug_reg = intel_de_rmw(display, SHOTPLUG_CTL_DDI, 0, 0); 571 572 spin_unlock(&dev_priv->irq_lock); 572 573 573 - intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask, 574 + intel_get_hpd_pins(display, &pin_mask, &long_mask, 574 575 ddi_hotplug_trigger, dig_hotplug_reg, 575 - dev_priv->display.hotplug.pch_hpd, 576 + display->hotplug.pch_hpd, 576 577 icp_ddi_port_hotplug_long_detect); 577 578 } 578 579 ··· 581 582 582 583 dig_hotplug_reg = intel_de_rmw(display, SHOTPLUG_CTL_TC, 0, 0); 583 584 584 - intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask, 585 + intel_get_hpd_pins(display, &pin_mask, &long_mask, 585 586 tc_hotplug_trigger, dig_hotplug_reg, 586 - dev_priv->display.hotplug.pch_hpd, 587 + display->hotplug.pch_hpd, 587 588 icp_tc_port_hotplug_long_detect); 588 589 } 589 590 ··· 594 595 intel_gmbus_irq_handler(display); 595 596 } 596 597 597 - void spt_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir) 598 + void spt_irq_handler(struct intel_display *display, u32 pch_iir) 598 599 { 599 - struct intel_display *display = &dev_priv->display; 600 600 u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_SPT & 601 601 ~SDE_PORTE_HOTPLUG_SPT; 602 602 u32 hotplug2_trigger = pch_iir & SDE_PORTE_HOTPLUG_SPT; ··· 606 608 607 609 dig_hotplug_reg = intel_de_rmw(display, PCH_PORT_HOTPLUG, 0, 0); 608 610 609 - intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask, 611 + intel_get_hpd_pins(display, &pin_mask, &long_mask, 610 612 hotplug_trigger, dig_hotplug_reg, 611 - dev_priv->display.hotplug.pch_hpd, 613 + display->hotplug.pch_hpd, 612 614 spt_port_hotplug_long_detect); 613 615 } 614 616 ··· 617 619 618 620 dig_hotplug_reg = intel_de_rmw(display, PCH_PORT_HOTPLUG2, 0, 0); 619 621 620 - intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask, 622 + intel_get_hpd_pins(display, &pin_mask, &long_mask, 621 623 hotplug2_trigger, dig_hotplug_reg, 622 - dev_priv->display.hotplug.pch_hpd, 624 + display->hotplug.pch_hpd, 623 625 spt_port_hotplug2_long_detect); 624 626 } 625 627 ··· 630 632 intel_gmbus_irq_handler(display); 631 633 } 632 634 633 - void ilk_hpd_irq_handler(struct drm_i915_private *dev_priv, u32 hotplug_trigger) 635 + void ilk_hpd_irq_handler(struct intel_display *display, u32 hotplug_trigger) 634 636 { 635 - struct intel_display *display = &dev_priv->display; 636 637 u32 dig_hotplug_reg, pin_mask = 0, long_mask = 0; 637 638 638 639 dig_hotplug_reg = intel_de_rmw(display, DIGITAL_PORT_HOTPLUG_CNTRL, 0, 0); 639 640 640 - intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask, 641 + intel_get_hpd_pins(display, &pin_mask, &long_mask, 641 642 hotplug_trigger, dig_hotplug_reg, 642 - dev_priv->display.hotplug.hpd, 643 + display->hotplug.hpd, 643 644 ilk_port_hotplug_long_detect); 644 645 645 646 intel_hpd_irq_handler(display, pin_mask, long_mask); 646 647 } 647 648 648 - void bxt_hpd_irq_handler(struct drm_i915_private *dev_priv, u32 hotplug_trigger) 649 + void bxt_hpd_irq_handler(struct intel_display *display, u32 hotplug_trigger) 649 650 { 650 - struct intel_display *display = &dev_priv->display; 651 651 u32 dig_hotplug_reg, pin_mask = 0, long_mask = 0; 652 652 653 653 dig_hotplug_reg = intel_de_rmw(display, PCH_PORT_HOTPLUG, 0, 0); 654 654 655 - intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask, 655 + intel_get_hpd_pins(display, &pin_mask, &long_mask, 656 656 hotplug_trigger, dig_hotplug_reg, 657 - dev_priv->display.hotplug.hpd, 657 + display->hotplug.hpd, 658 658 bxt_port_hotplug_long_detect); 659 659 660 660 intel_hpd_irq_handler(display, pin_mask, long_mask); 661 661 } 662 662 663 - void gen11_hpd_irq_handler(struct drm_i915_private *dev_priv, u32 iir) 663 + void gen11_hpd_irq_handler(struct intel_display *display, u32 iir) 664 664 { 665 - struct intel_display *display = &dev_priv->display; 666 665 u32 pin_mask = 0, long_mask = 0; 667 666 u32 trigger_tc = iir & GEN11_DE_TC_HOTPLUG_MASK; 668 667 u32 trigger_tbt = iir & GEN11_DE_TBT_HOTPLUG_MASK; ··· 669 674 670 675 dig_hotplug_reg = intel_de_rmw(display, GEN11_TC_HOTPLUG_CTL, 0, 0); 671 676 672 - intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask, 677 + intel_get_hpd_pins(display, &pin_mask, &long_mask, 673 678 trigger_tc, dig_hotplug_reg, 674 - dev_priv->display.hotplug.hpd, 679 + display->hotplug.hpd, 675 680 gen11_port_hotplug_long_detect); 676 681 } 677 682 ··· 680 685 681 686 dig_hotplug_reg = intel_de_rmw(display, GEN11_TBT_HOTPLUG_CTL, 0, 0); 682 687 683 - intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask, 688 + intel_get_hpd_pins(display, &pin_mask, &long_mask, 684 689 trigger_tbt, dig_hotplug_reg, 685 - dev_priv->display.hotplug.hpd, 690 + display->hotplug.hpd, 686 691 gen11_port_hotplug_long_detect); 687 692 } 688 693 689 694 if (pin_mask) 690 695 intel_hpd_irq_handler(display, pin_mask, long_mask); 691 696 else 692 - drm_err(&dev_priv->drm, 697 + drm_err(display->drm, 693 698 "Unexpected DE HPD interrupt 0x%08x\n", iir); 694 699 } 695 700 ··· 735 740 } 736 741 } 737 742 738 - static void ibx_hpd_detection_setup(struct drm_i915_private *dev_priv) 743 + static void ibx_hpd_detection_setup(struct intel_display *display) 739 744 { 740 - struct intel_display *display = &dev_priv->display; 741 - 742 745 /* 743 746 * Enable digital hotplug on the PCH, and configure the DP short pulse 744 747 * duration to 2ms (which is the minimum in the Display Port spec). 745 748 * The pulse duration bits are reserved on LPT+. 746 749 */ 747 750 intel_de_rmw(display, PCH_PORT_HOTPLUG, 748 - intel_hpd_hotplug_mask(dev_priv, ibx_hotplug_mask), 749 - intel_hpd_hotplug_enables(dev_priv, ibx_hotplug_enables)); 751 + intel_hpd_hotplug_mask(display, ibx_hotplug_mask), 752 + intel_hpd_hotplug_enables(display, ibx_hotplug_enables)); 750 753 } 751 754 752 755 static void ibx_hpd_enable_detection(struct intel_encoder *encoder) ··· 756 763 ibx_hotplug_enables(encoder)); 757 764 } 758 765 759 - static void ibx_hpd_irq_setup(struct drm_i915_private *dev_priv) 766 + static void ibx_hpd_irq_setup(struct intel_display *display) 760 767 { 768 + struct drm_i915_private *dev_priv = to_i915(display->drm); 761 769 u32 hotplug_irqs, enabled_irqs; 762 770 763 - enabled_irqs = intel_hpd_enabled_irqs(dev_priv, dev_priv->display.hotplug.pch_hpd); 764 - hotplug_irqs = intel_hpd_hotplug_irqs(dev_priv, dev_priv->display.hotplug.pch_hpd); 771 + enabled_irqs = intel_hpd_enabled_irqs(display, display->hotplug.pch_hpd); 772 + hotplug_irqs = intel_hpd_hotplug_irqs(display, display->hotplug.pch_hpd); 765 773 766 774 ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs); 767 775 768 - ibx_hpd_detection_setup(dev_priv); 776 + ibx_hpd_detection_setup(display); 769 777 } 770 778 771 779 static u32 icp_ddi_hotplug_mask(enum hpd_pin hpd_pin) ··· 807 813 return icp_tc_hotplug_mask(encoder->hpd_pin); 808 814 } 809 815 810 - static void icp_ddi_hpd_detection_setup(struct drm_i915_private *dev_priv) 816 + static void icp_ddi_hpd_detection_setup(struct intel_display *display) 811 817 { 812 - struct intel_display *display = &dev_priv->display; 813 - 814 818 intel_de_rmw(display, SHOTPLUG_CTL_DDI, 815 - intel_hpd_hotplug_mask(dev_priv, icp_ddi_hotplug_mask), 816 - intel_hpd_hotplug_enables(dev_priv, icp_ddi_hotplug_enables)); 819 + intel_hpd_hotplug_mask(display, icp_ddi_hotplug_mask), 820 + intel_hpd_hotplug_enables(display, icp_ddi_hotplug_enables)); 817 821 } 818 822 819 823 static void icp_ddi_hpd_enable_detection(struct intel_encoder *encoder) ··· 823 831 icp_ddi_hotplug_enables(encoder)); 824 832 } 825 833 826 - static void icp_tc_hpd_detection_setup(struct drm_i915_private *dev_priv) 834 + static void icp_tc_hpd_detection_setup(struct intel_display *display) 827 835 { 828 - struct intel_display *display = &dev_priv->display; 829 - 830 836 intel_de_rmw(display, SHOTPLUG_CTL_TC, 831 - intel_hpd_hotplug_mask(dev_priv, icp_tc_hotplug_mask), 832 - intel_hpd_hotplug_enables(dev_priv, icp_tc_hotplug_enables)); 837 + intel_hpd_hotplug_mask(display, icp_tc_hotplug_mask), 838 + intel_hpd_hotplug_enables(display, icp_tc_hotplug_enables)); 833 839 } 834 840 835 841 static void icp_tc_hpd_enable_detection(struct intel_encoder *encoder) ··· 845 855 icp_tc_hpd_enable_detection(encoder); 846 856 } 847 857 848 - static void icp_hpd_irq_setup(struct drm_i915_private *dev_priv) 858 + static void icp_hpd_irq_setup(struct intel_display *display) 849 859 { 850 - struct intel_display *display = &dev_priv->display; 860 + struct drm_i915_private *dev_priv = to_i915(display->drm); 851 861 u32 hotplug_irqs, enabled_irqs; 852 862 853 - enabled_irqs = intel_hpd_enabled_irqs(dev_priv, dev_priv->display.hotplug.pch_hpd); 854 - hotplug_irqs = intel_hpd_hotplug_irqs(dev_priv, dev_priv->display.hotplug.pch_hpd); 863 + enabled_irqs = intel_hpd_enabled_irqs(display, display->hotplug.pch_hpd); 864 + hotplug_irqs = intel_hpd_hotplug_irqs(display, display->hotplug.pch_hpd); 855 865 856 866 /* 857 867 * We reduce the value to 250us to be able to detect SHPD when an external display ··· 861 871 862 872 ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs); 863 873 864 - icp_ddi_hpd_detection_setup(dev_priv); 865 - icp_tc_hpd_detection_setup(dev_priv); 874 + icp_ddi_hpd_detection_setup(display); 875 + icp_tc_hpd_detection_setup(display); 866 876 } 867 877 868 878 static u32 gen11_hotplug_mask(enum hpd_pin hpd_pin) ··· 885 895 return gen11_hotplug_mask(encoder->hpd_pin); 886 896 } 887 897 888 - static void dg1_hpd_invert(struct drm_i915_private *i915) 898 + static void dg1_hpd_invert(struct intel_display *display) 889 899 { 890 - struct intel_display *display = &i915->display; 891 900 u32 val = (INVERT_DDIA_HPD | 892 901 INVERT_DDIB_HPD | 893 902 INVERT_DDIC_HPD | ··· 896 907 897 908 static void dg1_hpd_enable_detection(struct intel_encoder *encoder) 898 909 { 899 - struct drm_i915_private *i915 = to_i915(encoder->base.dev); 910 + struct intel_display *display = to_intel_display(encoder); 900 911 901 - dg1_hpd_invert(i915); 912 + dg1_hpd_invert(display); 902 913 icp_hpd_enable_detection(encoder); 903 914 } 904 915 905 - static void dg1_hpd_irq_setup(struct drm_i915_private *dev_priv) 916 + static void dg1_hpd_irq_setup(struct intel_display *display) 906 917 { 907 - dg1_hpd_invert(dev_priv); 908 - icp_hpd_irq_setup(dev_priv); 918 + dg1_hpd_invert(display); 919 + icp_hpd_irq_setup(display); 909 920 } 910 921 911 - static void gen11_tc_hpd_detection_setup(struct drm_i915_private *dev_priv) 922 + static void gen11_tc_hpd_detection_setup(struct intel_display *display) 912 923 { 913 - struct intel_display *display = &dev_priv->display; 914 - 915 924 intel_de_rmw(display, GEN11_TC_HOTPLUG_CTL, 916 - intel_hpd_hotplug_mask(dev_priv, gen11_hotplug_mask), 917 - intel_hpd_hotplug_enables(dev_priv, gen11_hotplug_enables)); 925 + intel_hpd_hotplug_mask(display, gen11_hotplug_mask), 926 + intel_hpd_hotplug_enables(display, gen11_hotplug_enables)); 918 927 } 919 928 920 929 static void gen11_tc_hpd_enable_detection(struct intel_encoder *encoder) ··· 924 937 gen11_hotplug_enables(encoder)); 925 938 } 926 939 927 - static void gen11_tbt_hpd_detection_setup(struct drm_i915_private *dev_priv) 940 + static void gen11_tbt_hpd_detection_setup(struct intel_display *display) 928 941 { 929 - struct intel_display *display = &dev_priv->display; 930 - 931 942 intel_de_rmw(display, GEN11_TBT_HOTPLUG_CTL, 932 - intel_hpd_hotplug_mask(dev_priv, gen11_hotplug_mask), 933 - intel_hpd_hotplug_enables(dev_priv, gen11_hotplug_enables)); 943 + intel_hpd_hotplug_mask(display, gen11_hotplug_mask), 944 + intel_hpd_hotplug_enables(display, gen11_hotplug_enables)); 934 945 } 935 946 936 947 static void gen11_tbt_hpd_enable_detection(struct intel_encoder *encoder) ··· 951 966 icp_hpd_enable_detection(encoder); 952 967 } 953 968 954 - static void gen11_hpd_irq_setup(struct drm_i915_private *dev_priv) 969 + static void gen11_hpd_irq_setup(struct intel_display *display) 955 970 { 956 - struct intel_display *display = &dev_priv->display; 971 + struct drm_i915_private *dev_priv = to_i915(display->drm); 957 972 u32 hotplug_irqs, enabled_irqs; 958 973 959 - enabled_irqs = intel_hpd_enabled_irqs(dev_priv, dev_priv->display.hotplug.hpd); 960 - hotplug_irqs = intel_hpd_hotplug_irqs(dev_priv, dev_priv->display.hotplug.hpd); 974 + enabled_irqs = intel_hpd_enabled_irqs(display, display->hotplug.hpd); 975 + hotplug_irqs = intel_hpd_hotplug_irqs(display, display->hotplug.hpd); 961 976 962 977 intel_de_rmw(display, GEN11_DE_HPD_IMR, hotplug_irqs, 963 978 ~enabled_irqs & hotplug_irqs); 964 979 intel_de_posting_read(display, GEN11_DE_HPD_IMR); 965 980 966 - gen11_tc_hpd_detection_setup(dev_priv); 967 - gen11_tbt_hpd_detection_setup(dev_priv); 981 + gen11_tc_hpd_detection_setup(display); 982 + gen11_tbt_hpd_detection_setup(display); 968 983 969 984 if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP) 970 - icp_hpd_irq_setup(dev_priv); 985 + icp_hpd_irq_setup(display); 971 986 } 972 987 973 988 static u32 mtp_ddi_hotplug_mask(enum hpd_pin hpd_pin) ··· 1004 1019 return mtp_tc_hotplug_mask(encoder->hpd_pin); 1005 1020 } 1006 1021 1007 - static void mtp_ddi_hpd_detection_setup(struct drm_i915_private *i915) 1022 + static void mtp_ddi_hpd_detection_setup(struct intel_display *display) 1008 1023 { 1009 - intel_de_rmw(i915, SHOTPLUG_CTL_DDI, 1010 - intel_hpd_hotplug_mask(i915, mtp_ddi_hotplug_mask), 1011 - intel_hpd_hotplug_enables(i915, mtp_ddi_hotplug_enables)); 1024 + intel_de_rmw(display, SHOTPLUG_CTL_DDI, 1025 + intel_hpd_hotplug_mask(display, mtp_ddi_hotplug_mask), 1026 + intel_hpd_hotplug_enables(display, mtp_ddi_hotplug_enables)); 1012 1027 } 1013 1028 1014 1029 static void mtp_ddi_hpd_enable_detection(struct intel_encoder *encoder) 1015 1030 { 1016 - struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1031 + struct intel_display *display = to_intel_display(encoder); 1017 1032 1018 - intel_de_rmw(i915, SHOTPLUG_CTL_DDI, 1033 + intel_de_rmw(display, SHOTPLUG_CTL_DDI, 1019 1034 mtp_ddi_hotplug_mask(encoder->hpd_pin), 1020 1035 mtp_ddi_hotplug_enables(encoder)); 1021 1036 } 1022 1037 1023 - static void mtp_tc_hpd_detection_setup(struct drm_i915_private *i915) 1038 + static void mtp_tc_hpd_detection_setup(struct intel_display *display) 1024 1039 { 1025 - intel_de_rmw(i915, SHOTPLUG_CTL_TC, 1026 - intel_hpd_hotplug_mask(i915, mtp_tc_hotplug_mask), 1027 - intel_hpd_hotplug_enables(i915, mtp_tc_hotplug_enables)); 1040 + intel_de_rmw(display, SHOTPLUG_CTL_TC, 1041 + intel_hpd_hotplug_mask(display, mtp_tc_hotplug_mask), 1042 + intel_hpd_hotplug_enables(display, mtp_tc_hotplug_enables)); 1028 1043 } 1029 1044 1030 1045 static void mtp_tc_hpd_enable_detection(struct intel_encoder *encoder) 1031 1046 { 1032 - struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1047 + struct intel_display *display = to_intel_display(encoder); 1033 1048 1034 - intel_de_rmw(i915, SHOTPLUG_CTL_DDI, 1049 + intel_de_rmw(display, SHOTPLUG_CTL_DDI, 1035 1050 mtp_tc_hotplug_mask(encoder->hpd_pin), 1036 1051 mtp_tc_hotplug_enables(encoder)); 1037 1052 } 1038 1053 1039 - static void mtp_hpd_invert(struct drm_i915_private *i915) 1054 + static void mtp_hpd_invert(struct intel_display *display) 1040 1055 { 1041 1056 u32 val = (INVERT_DDIA_HPD | 1042 1057 INVERT_DDIB_HPD | ··· 1047 1062 INVERT_TC4_HPD | 1048 1063 INVERT_DDID_HPD_MTP | 1049 1064 INVERT_DDIE_HPD); 1050 - intel_de_rmw(i915, SOUTH_CHICKEN1, 0, val); 1065 + intel_de_rmw(display, SOUTH_CHICKEN1, 0, val); 1051 1066 } 1052 1067 1053 1068 static void mtp_hpd_enable_detection(struct intel_encoder *encoder) 1054 1069 { 1055 - struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1070 + struct intel_display *display = to_intel_display(encoder); 1056 1071 1057 - mtp_hpd_invert(i915); 1072 + mtp_hpd_invert(display); 1058 1073 mtp_ddi_hpd_enable_detection(encoder); 1059 1074 mtp_tc_hpd_enable_detection(encoder); 1060 1075 } 1061 1076 1062 - static void mtp_hpd_irq_setup(struct drm_i915_private *i915) 1077 + static void mtp_hpd_irq_setup(struct intel_display *display) 1063 1078 { 1079 + struct drm_i915_private *i915 = to_i915(display->drm); 1064 1080 u32 hotplug_irqs, enabled_irqs; 1065 1081 1066 - enabled_irqs = intel_hpd_enabled_irqs(i915, i915->display.hotplug.pch_hpd); 1067 - hotplug_irqs = intel_hpd_hotplug_irqs(i915, i915->display.hotplug.pch_hpd); 1082 + enabled_irqs = intel_hpd_enabled_irqs(display, display->hotplug.pch_hpd); 1083 + hotplug_irqs = intel_hpd_hotplug_irqs(display, display->hotplug.pch_hpd); 1068 1084 1069 1085 /* 1070 1086 * Use 250us here to align with the DP1.4a(Table 3-4) spec as to what the 1071 1087 * SHPD_FILTER_CNT value should be. 1072 1088 */ 1073 - intel_de_write(i915, SHPD_FILTER_CNT, SHPD_FILTER_CNT_250); 1089 + intel_de_write(display, SHPD_FILTER_CNT, SHPD_FILTER_CNT_250); 1074 1090 1075 - mtp_hpd_invert(i915); 1091 + mtp_hpd_invert(display); 1076 1092 ibx_display_interrupt_update(i915, hotplug_irqs, enabled_irqs); 1077 1093 1078 - mtp_ddi_hpd_detection_setup(i915); 1079 - mtp_tc_hpd_detection_setup(i915); 1094 + mtp_ddi_hpd_detection_setup(display); 1095 + mtp_tc_hpd_detection_setup(display); 1080 1096 } 1081 1097 1082 - static void xe2lpd_sde_hpd_irq_setup(struct drm_i915_private *i915) 1098 + static void xe2lpd_sde_hpd_irq_setup(struct intel_display *display) 1083 1099 { 1100 + struct drm_i915_private *i915 = to_i915(display->drm); 1084 1101 u32 hotplug_irqs, enabled_irqs; 1085 1102 1086 - enabled_irqs = intel_hpd_enabled_irqs(i915, i915->display.hotplug.pch_hpd); 1087 - hotplug_irqs = intel_hpd_hotplug_irqs(i915, i915->display.hotplug.pch_hpd); 1103 + enabled_irqs = intel_hpd_enabled_irqs(display, display->hotplug.pch_hpd); 1104 + hotplug_irqs = intel_hpd_hotplug_irqs(display, display->hotplug.pch_hpd); 1088 1105 1089 1106 ibx_display_interrupt_update(i915, hotplug_irqs, enabled_irqs); 1090 1107 1091 - mtp_ddi_hpd_detection_setup(i915); 1092 - mtp_tc_hpd_detection_setup(i915); 1108 + mtp_ddi_hpd_detection_setup(display); 1109 + mtp_tc_hpd_detection_setup(display); 1093 1110 } 1094 1111 1095 1112 static bool is_xelpdp_pica_hpd_pin(enum hpd_pin hpd_pin) ··· 1099 1112 return hpd_pin >= HPD_PORT_TC1 && hpd_pin <= HPD_PORT_TC4; 1100 1113 } 1101 1114 1102 - static void _xelpdp_pica_hpd_detection_setup(struct drm_i915_private *i915, 1115 + static void _xelpdp_pica_hpd_detection_setup(struct intel_display *display, 1103 1116 enum hpd_pin hpd_pin, bool enable) 1104 1117 { 1105 1118 u32 mask = XELPDP_TBT_HOTPLUG_ENABLE | ··· 1108 1121 if (!is_xelpdp_pica_hpd_pin(hpd_pin)) 1109 1122 return; 1110 1123 1111 - intel_de_rmw(i915, XELPDP_PORT_HOTPLUG_CTL(hpd_pin), 1124 + intel_de_rmw(display, XELPDP_PORT_HOTPLUG_CTL(hpd_pin), 1112 1125 mask, enable ? mask : 0); 1113 1126 } 1114 1127 1115 1128 static void xelpdp_pica_hpd_enable_detection(struct intel_encoder *encoder) 1116 1129 { 1117 - struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1130 + struct intel_display *display = to_intel_display(encoder); 1118 1131 1119 - _xelpdp_pica_hpd_detection_setup(i915, encoder->hpd_pin, true); 1132 + _xelpdp_pica_hpd_detection_setup(display, encoder->hpd_pin, true); 1120 1133 } 1121 1134 1122 - static void xelpdp_pica_hpd_detection_setup(struct drm_i915_private *i915) 1135 + static void xelpdp_pica_hpd_detection_setup(struct intel_display *display) 1123 1136 { 1124 1137 struct intel_encoder *encoder; 1125 1138 u32 available_pins = 0; ··· 1127 1140 1128 1141 BUILD_BUG_ON(BITS_PER_TYPE(available_pins) < HPD_NUM_PINS); 1129 1142 1130 - for_each_intel_encoder(&i915->drm, encoder) 1143 + for_each_intel_encoder(display->drm, encoder) 1131 1144 available_pins |= BIT(encoder->hpd_pin); 1132 1145 1133 1146 for_each_hpd_pin(pin) 1134 - _xelpdp_pica_hpd_detection_setup(i915, pin, available_pins & BIT(pin)); 1147 + _xelpdp_pica_hpd_detection_setup(display, pin, available_pins & BIT(pin)); 1135 1148 } 1136 1149 1137 1150 static void xelpdp_hpd_enable_detection(struct intel_encoder *encoder) ··· 1140 1153 mtp_hpd_enable_detection(encoder); 1141 1154 } 1142 1155 1143 - static void xelpdp_hpd_irq_setup(struct drm_i915_private *i915) 1156 + static void xelpdp_hpd_irq_setup(struct intel_display *display) 1144 1157 { 1145 - struct intel_display *display = &i915->display; 1158 + struct drm_i915_private *i915 = to_i915(display->drm); 1146 1159 u32 hotplug_irqs, enabled_irqs; 1147 1160 1148 - enabled_irqs = intel_hpd_enabled_irqs(i915, i915->display.hotplug.hpd); 1149 - hotplug_irqs = intel_hpd_hotplug_irqs(i915, i915->display.hotplug.hpd); 1161 + enabled_irqs = intel_hpd_enabled_irqs(display, display->hotplug.hpd); 1162 + hotplug_irqs = intel_hpd_hotplug_irqs(display, display->hotplug.hpd); 1150 1163 1151 - intel_de_rmw(i915, PICAINTERRUPT_IMR, hotplug_irqs, 1164 + intel_de_rmw(display, PICAINTERRUPT_IMR, hotplug_irqs, 1152 1165 ~enabled_irqs & hotplug_irqs); 1153 1166 intel_de_posting_read(display, PICAINTERRUPT_IMR); 1154 1167 1155 - xelpdp_pica_hpd_detection_setup(i915); 1168 + xelpdp_pica_hpd_detection_setup(display); 1156 1169 1157 1170 if (INTEL_PCH_TYPE(i915) >= PCH_LNL) 1158 - xe2lpd_sde_hpd_irq_setup(i915); 1171 + xe2lpd_sde_hpd_irq_setup(display); 1159 1172 else if (INTEL_PCH_TYPE(i915) >= PCH_MTL) 1160 - mtp_hpd_irq_setup(i915); 1173 + mtp_hpd_irq_setup(display); 1161 1174 } 1162 1175 1163 1176 static u32 spt_hotplug_mask(enum hpd_pin hpd_pin) ··· 1196 1209 return spt_hotplug2_mask(encoder->hpd_pin); 1197 1210 } 1198 1211 1199 - static void spt_hpd_detection_setup(struct drm_i915_private *dev_priv) 1212 + static void spt_hpd_detection_setup(struct intel_display *display) 1200 1213 { 1201 - struct intel_display *display = &dev_priv->display; 1214 + struct drm_i915_private *dev_priv = to_i915(display->drm); 1202 1215 1203 1216 /* Display WA #1179 WaHardHangonHotPlug: cnp */ 1204 1217 if (HAS_PCH_CNP(dev_priv)) { ··· 1208 1221 1209 1222 /* Enable digital hotplug on the PCH */ 1210 1223 intel_de_rmw(display, PCH_PORT_HOTPLUG, 1211 - intel_hpd_hotplug_mask(dev_priv, spt_hotplug_mask), 1212 - intel_hpd_hotplug_enables(dev_priv, spt_hotplug_enables)); 1224 + intel_hpd_hotplug_mask(display, spt_hotplug_mask), 1225 + intel_hpd_hotplug_enables(display, spt_hotplug_enables)); 1213 1226 1214 1227 intel_de_rmw(display, PCH_PORT_HOTPLUG2, 1215 - intel_hpd_hotplug_mask(dev_priv, spt_hotplug2_mask), 1216 - intel_hpd_hotplug_enables(dev_priv, spt_hotplug2_enables)); 1228 + intel_hpd_hotplug_mask(display, spt_hotplug2_mask), 1229 + intel_hpd_hotplug_enables(display, spt_hotplug2_enables)); 1217 1230 } 1218 1231 1219 1232 static void spt_hpd_enable_detection(struct intel_encoder *encoder) ··· 1237 1250 spt_hotplug2_enables(encoder)); 1238 1251 } 1239 1252 1240 - static void spt_hpd_irq_setup(struct drm_i915_private *dev_priv) 1253 + static void spt_hpd_irq_setup(struct intel_display *display) 1241 1254 { 1242 - struct intel_display *display = &dev_priv->display; 1255 + struct drm_i915_private *dev_priv = to_i915(display->drm); 1243 1256 u32 hotplug_irqs, enabled_irqs; 1244 1257 1245 1258 if (INTEL_PCH_TYPE(dev_priv) >= PCH_CNP) 1246 1259 intel_de_write(display, SHPD_FILTER_CNT, SHPD_FILTER_CNT_500_ADJ); 1247 1260 1248 - enabled_irqs = intel_hpd_enabled_irqs(dev_priv, dev_priv->display.hotplug.pch_hpd); 1249 - hotplug_irqs = intel_hpd_hotplug_irqs(dev_priv, dev_priv->display.hotplug.pch_hpd); 1261 + enabled_irqs = intel_hpd_enabled_irqs(display, display->hotplug.pch_hpd); 1262 + hotplug_irqs = intel_hpd_hotplug_irqs(display, display->hotplug.pch_hpd); 1250 1263 1251 1264 ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs); 1252 1265 1253 - spt_hpd_detection_setup(dev_priv); 1266 + spt_hpd_detection_setup(display); 1254 1267 } 1255 1268 1256 1269 static u32 ilk_hotplug_mask(enum hpd_pin hpd_pin) ··· 1275 1288 } 1276 1289 } 1277 1290 1278 - static void ilk_hpd_detection_setup(struct drm_i915_private *dev_priv) 1291 + static void ilk_hpd_detection_setup(struct intel_display *display) 1279 1292 { 1280 - struct intel_display *display = &dev_priv->display; 1281 - 1282 1293 /* 1283 1294 * Enable digital hotplug on the CPU, and configure the DP short pulse 1284 1295 * duration to 2ms (which is the minimum in the Display Port spec) 1285 1296 * The pulse duration bits are reserved on HSW+. 1286 1297 */ 1287 1298 intel_de_rmw(display, DIGITAL_PORT_HOTPLUG_CNTRL, 1288 - intel_hpd_hotplug_mask(dev_priv, ilk_hotplug_mask), 1289 - intel_hpd_hotplug_enables(dev_priv, ilk_hotplug_enables)); 1299 + intel_hpd_hotplug_mask(display, ilk_hotplug_mask), 1300 + intel_hpd_hotplug_enables(display, ilk_hotplug_enables)); 1290 1301 } 1291 1302 1292 1303 static void ilk_hpd_enable_detection(struct intel_encoder *encoder) ··· 1298 1313 ibx_hpd_enable_detection(encoder); 1299 1314 } 1300 1315 1301 - static void ilk_hpd_irq_setup(struct drm_i915_private *dev_priv) 1316 + static void ilk_hpd_irq_setup(struct intel_display *display) 1302 1317 { 1318 + struct drm_i915_private *dev_priv = to_i915(display->drm); 1303 1319 u32 hotplug_irqs, enabled_irqs; 1304 1320 1305 - enabled_irqs = intel_hpd_enabled_irqs(dev_priv, dev_priv->display.hotplug.hpd); 1306 - hotplug_irqs = intel_hpd_hotplug_irqs(dev_priv, dev_priv->display.hotplug.hpd); 1321 + enabled_irqs = intel_hpd_enabled_irqs(display, display->hotplug.hpd); 1322 + hotplug_irqs = intel_hpd_hotplug_irqs(display, display->hotplug.hpd); 1307 1323 1308 - if (DISPLAY_VER(dev_priv) >= 8) 1324 + if (DISPLAY_VER(display) >= 8) 1309 1325 bdw_update_port_irq(dev_priv, hotplug_irqs, enabled_irqs); 1310 1326 else 1311 1327 ilk_update_display_irq(dev_priv, hotplug_irqs, enabled_irqs); 1312 1328 1313 - ilk_hpd_detection_setup(dev_priv); 1329 + ilk_hpd_detection_setup(display); 1314 1330 1315 - ibx_hpd_irq_setup(dev_priv); 1331 + ibx_hpd_irq_setup(display); 1316 1332 } 1317 1333 1318 1334 static u32 bxt_hotplug_mask(enum hpd_pin hpd_pin) ··· 1355 1369 } 1356 1370 } 1357 1371 1358 - static void bxt_hpd_detection_setup(struct drm_i915_private *dev_priv) 1372 + static void bxt_hpd_detection_setup(struct intel_display *display) 1359 1373 { 1360 - struct intel_display *display = &dev_priv->display; 1361 - 1362 1374 intel_de_rmw(display, PCH_PORT_HOTPLUG, 1363 - intel_hpd_hotplug_mask(dev_priv, bxt_hotplug_mask), 1364 - intel_hpd_hotplug_enables(dev_priv, bxt_hotplug_enables)); 1375 + intel_hpd_hotplug_mask(display, bxt_hotplug_mask), 1376 + intel_hpd_hotplug_enables(display, bxt_hotplug_enables)); 1365 1377 } 1366 1378 1367 1379 static void bxt_hpd_enable_detection(struct intel_encoder *encoder) ··· 1371 1387 bxt_hotplug_enables(encoder)); 1372 1388 } 1373 1389 1374 - static void bxt_hpd_irq_setup(struct drm_i915_private *dev_priv) 1390 + static void bxt_hpd_irq_setup(struct intel_display *display) 1375 1391 { 1392 + struct drm_i915_private *dev_priv = to_i915(display->drm); 1376 1393 u32 hotplug_irqs, enabled_irqs; 1377 1394 1378 - enabled_irqs = intel_hpd_enabled_irqs(dev_priv, dev_priv->display.hotplug.hpd); 1379 - hotplug_irqs = intel_hpd_hotplug_irqs(dev_priv, dev_priv->display.hotplug.hpd); 1395 + enabled_irqs = intel_hpd_enabled_irqs(display, display->hotplug.hpd); 1396 + hotplug_irqs = intel_hpd_hotplug_irqs(display, display->hotplug.hpd); 1380 1397 1381 1398 bdw_update_port_irq(dev_priv, hotplug_irqs, enabled_irqs); 1382 1399 1383 - bxt_hpd_detection_setup(dev_priv); 1400 + bxt_hpd_detection_setup(display); 1384 1401 } 1385 1402 1386 - static void g45_hpd_peg_band_gap_wa(struct drm_i915_private *i915) 1403 + static void g45_hpd_peg_band_gap_wa(struct intel_display *display) 1387 1404 { 1388 1405 /* 1389 1406 * For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written 1390 1407 * 0xd. Failure to do so will result in spurious interrupts being 1391 1408 * generated on the port when a cable is not attached. 1392 1409 */ 1393 - intel_de_rmw(i915, PEG_BAND_GAP_DATA, 0xf, 0xd); 1410 + intel_de_rmw(display, PEG_BAND_GAP_DATA, 0xf, 0xd); 1394 1411 } 1395 1412 1396 1413 static void i915_hpd_enable_detection(struct intel_encoder *encoder) 1397 1414 { 1398 - struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1415 + struct intel_display *display = to_intel_display(encoder); 1399 1416 u32 hotplug_en = hpd_mask_i915[encoder->hpd_pin]; 1400 1417 1401 - if (IS_G45(i915)) 1402 - g45_hpd_peg_band_gap_wa(i915); 1418 + if (display->platform.g45) 1419 + g45_hpd_peg_band_gap_wa(display); 1403 1420 1404 1421 /* HPD sense and interrupt enable are one and the same */ 1405 - i915_hotplug_interrupt_update(i915, hotplug_en, hotplug_en); 1422 + i915_hotplug_interrupt_update(display, hotplug_en, hotplug_en); 1406 1423 } 1407 1424 1408 - static void i915_hpd_irq_setup(struct drm_i915_private *dev_priv) 1425 + static void i915_hpd_irq_setup(struct intel_display *display) 1409 1426 { 1427 + struct drm_i915_private *dev_priv = to_i915(display->drm); 1410 1428 u32 hotplug_en; 1411 1429 1412 1430 lockdep_assert_held(&dev_priv->irq_lock); ··· 1417 1431 * Note HDMI and DP share hotplug bits. Enable bits are the same for all 1418 1432 * generations. 1419 1433 */ 1420 - hotplug_en = intel_hpd_enabled_irqs(dev_priv, hpd_mask_i915); 1434 + hotplug_en = intel_hpd_enabled_irqs(display, hpd_mask_i915); 1421 1435 /* 1422 1436 * Programming the CRT detection parameters tends to generate a spurious 1423 1437 * hotplug event about three seconds later. So just do it once. 1424 1438 */ 1425 - if (IS_G4X(dev_priv)) 1439 + if (display->platform.g4x) 1426 1440 hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64; 1427 1441 hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50; 1428 1442 1429 - if (IS_G45(dev_priv)) 1430 - g45_hpd_peg_band_gap_wa(dev_priv); 1443 + if (display->platform.g45) 1444 + g45_hpd_peg_band_gap_wa(display); 1431 1445 1432 1446 /* Ignore TV since it's buggy */ 1433 - i915_hotplug_interrupt_update_locked(dev_priv, 1447 + i915_hotplug_interrupt_update_locked(display, 1434 1448 HOTPLUG_INT_EN_MASK | 1435 1449 CRT_HOTPLUG_VOLTAGE_COMPARE_MASK | 1436 1450 CRT_HOTPLUG_ACTIVATION_PERIOD_64, ··· 1439 1453 1440 1454 struct intel_hotplug_funcs { 1441 1455 /* Enable HPD sense and interrupts for all present encoders */ 1442 - void (*hpd_irq_setup)(struct drm_i915_private *i915); 1456 + void (*hpd_irq_setup)(struct intel_display *display); 1443 1457 /* Enable HPD sense for a single encoder */ 1444 1458 void (*hpd_enable_detection)(struct intel_encoder *encoder); 1445 1459 }; ··· 1462 1476 1463 1477 void intel_hpd_enable_detection(struct intel_encoder *encoder) 1464 1478 { 1465 - struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1479 + struct intel_display *display = to_intel_display(encoder); 1466 1480 1467 - if (i915->display.funcs.hotplug) 1468 - i915->display.funcs.hotplug->hpd_enable_detection(encoder); 1481 + if (display->funcs.hotplug) 1482 + display->funcs.hotplug->hpd_enable_detection(encoder); 1469 1483 } 1470 1484 1471 - void intel_hpd_irq_setup(struct drm_i915_private *i915) 1485 + void intel_hpd_irq_setup(struct intel_display *display) 1472 1486 { 1473 - if ((IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) && 1474 - !i915->display.irq.vlv_display_irqs_enabled) 1487 + if ((display->platform.valleyview || display->platform.cherryview) && 1488 + !display->irq.vlv_display_irqs_enabled) 1475 1489 return; 1476 1490 1477 - if (i915->display.funcs.hotplug) 1478 - i915->display.funcs.hotplug->hpd_irq_setup(i915); 1491 + if (display->funcs.hotplug) 1492 + display->funcs.hotplug->hpd_irq_setup(display); 1479 1493 } 1480 1494 1481 - void intel_hotplug_irq_init(struct drm_i915_private *i915) 1495 + void intel_hotplug_irq_init(struct intel_display *display) 1482 1496 { 1483 - struct intel_display *display = &i915->display; 1497 + struct drm_i915_private *i915 = to_i915(display->drm); 1484 1498 1485 - intel_hpd_init_pins(i915); 1499 + intel_hpd_init_pins(display); 1486 1500 1487 1501 intel_hpd_init_early(display); 1488 1502 1489 - if (HAS_GMCH(i915)) { 1490 - if (I915_HAS_HOTPLUG(i915)) 1491 - i915->display.funcs.hotplug = &i915_hpd_funcs; 1503 + if (HAS_GMCH(display)) { 1504 + if (I915_HAS_HOTPLUG(display)) 1505 + display->funcs.hotplug = &i915_hpd_funcs; 1492 1506 } else { 1493 1507 if (HAS_PCH_DG2(i915)) 1494 - i915->display.funcs.hotplug = &icp_hpd_funcs; 1508 + display->funcs.hotplug = &icp_hpd_funcs; 1495 1509 else if (HAS_PCH_DG1(i915)) 1496 - i915->display.funcs.hotplug = &dg1_hpd_funcs; 1497 - else if (DISPLAY_VER(i915) >= 14) 1498 - i915->display.funcs.hotplug = &xelpdp_hpd_funcs; 1499 - else if (DISPLAY_VER(i915) >= 11) 1500 - i915->display.funcs.hotplug = &gen11_hpd_funcs; 1501 - else if (IS_GEMINILAKE(i915) || IS_BROXTON(i915)) 1502 - i915->display.funcs.hotplug = &bxt_hpd_funcs; 1510 + display->funcs.hotplug = &dg1_hpd_funcs; 1511 + else if (DISPLAY_VER(display) >= 14) 1512 + display->funcs.hotplug = &xelpdp_hpd_funcs; 1513 + else if (DISPLAY_VER(display) >= 11) 1514 + display->funcs.hotplug = &gen11_hpd_funcs; 1515 + else if (display->platform.geminilake || display->platform.broxton) 1516 + display->funcs.hotplug = &bxt_hpd_funcs; 1503 1517 else if (INTEL_PCH_TYPE(i915) >= PCH_ICP) 1504 - i915->display.funcs.hotplug = &icp_hpd_funcs; 1518 + display->funcs.hotplug = &icp_hpd_funcs; 1505 1519 else if (INTEL_PCH_TYPE(i915) >= PCH_SPT) 1506 - i915->display.funcs.hotplug = &spt_hpd_funcs; 1520 + display->funcs.hotplug = &spt_hpd_funcs; 1507 1521 else 1508 - i915->display.funcs.hotplug = &ilk_hpd_funcs; 1522 + display->funcs.hotplug = &ilk_hpd_funcs; 1509 1523 } 1510 1524 }

+14 -14

drivers/gpu/drm/i915/display/intel_hotplug_irq.h

··· 8 8 9 9 #include <linux/types.h> 10 10 11 - struct drm_i915_private; 11 + struct intel_display; 12 12 struct intel_encoder; 13 13 14 - u32 i9xx_hpd_irq_ack(struct drm_i915_private *i915); 14 + u32 i9xx_hpd_irq_ack(struct intel_display *display); 15 15 16 - void i9xx_hpd_irq_handler(struct drm_i915_private *i915, u32 hotplug_status); 17 - void ibx_hpd_irq_handler(struct drm_i915_private *i915, u32 hotplug_trigger); 18 - void ilk_hpd_irq_handler(struct drm_i915_private *i915, u32 hotplug_trigger); 19 - void gen11_hpd_irq_handler(struct drm_i915_private *i915, u32 iir); 20 - void bxt_hpd_irq_handler(struct drm_i915_private *i915, u32 hotplug_trigger); 21 - void xelpdp_pica_irq_handler(struct drm_i915_private *i915, u32 iir); 22 - void icp_irq_handler(struct drm_i915_private *i915, u32 pch_iir); 23 - void spt_irq_handler(struct drm_i915_private *i915, u32 pch_iir); 16 + void i9xx_hpd_irq_handler(struct intel_display *display, u32 hotplug_status); 17 + void ibx_hpd_irq_handler(struct intel_display *display, u32 hotplug_trigger); 18 + void ilk_hpd_irq_handler(struct intel_display *display, u32 hotplug_trigger); 19 + void gen11_hpd_irq_handler(struct intel_display *display, u32 iir); 20 + void bxt_hpd_irq_handler(struct intel_display *display, u32 hotplug_trigger); 21 + void xelpdp_pica_irq_handler(struct intel_display *display, u32 iir); 22 + void icp_irq_handler(struct intel_display *display, u32 pch_iir); 23 + void spt_irq_handler(struct intel_display *display, u32 pch_iir); 24 24 25 - void i915_hotplug_interrupt_update_locked(struct drm_i915_private *i915, 25 + void i915_hotplug_interrupt_update_locked(struct intel_display *display, 26 26 u32 mask, u32 bits); 27 - void i915_hotplug_interrupt_update(struct drm_i915_private *i915, 27 + void i915_hotplug_interrupt_update(struct intel_display *display, 28 28 u32 mask, u32 bits); 29 29 30 30 void intel_hpd_enable_detection(struct intel_encoder *encoder); 31 - void intel_hpd_irq_setup(struct drm_i915_private *i915); 31 + void intel_hpd_irq_setup(struct intel_display *display); 32 32 33 - void intel_hotplug_irq_init(struct drm_i915_private *i915); 33 + void intel_hotplug_irq_init(struct intel_display *display); 34 34 35 35 #endif /* __INTEL_HOTPLUG_IRQ_H__ */

+10 -8

drivers/gpu/drm/i915/i915_irq.c

··· 277 277 intel_uncore_write(&dev_priv->uncore, GEN6_PMIIR, pm_iir); 278 278 279 279 if (iir & I915_DISPLAY_PORT_INTERRUPT) 280 - hotplug_status = i9xx_hpd_irq_ack(dev_priv); 280 + hotplug_status = i9xx_hpd_irq_ack(display); 281 281 282 282 if (iir & I915_MASTER_ERROR_INTERRUPT) 283 283 vlv_display_error_irq_ack(display, &eir, &dpinvgtt); ··· 306 306 gen6_rps_irq_handler(&to_gt(dev_priv)->rps, pm_iir); 307 307 308 308 if (hotplug_status) 309 - i9xx_hpd_irq_handler(dev_priv, hotplug_status); 309 + i9xx_hpd_irq_handler(display, hotplug_status); 310 310 311 311 if (iir & I915_MASTER_ERROR_INTERRUPT) 312 312 vlv_display_error_irq_handler(display, eir, dpinvgtt); ··· 367 367 gen8_gt_irq_handler(to_gt(dev_priv), master_ctl); 368 368 369 369 if (iir & I915_DISPLAY_PORT_INTERRUPT) 370 - hotplug_status = i9xx_hpd_irq_ack(dev_priv); 370 + hotplug_status = i9xx_hpd_irq_ack(display); 371 371 372 372 if (iir & I915_MASTER_ERROR_INTERRUPT) 373 373 vlv_display_error_irq_ack(display, &eir, &dpinvgtt); ··· 392 392 intel_uncore_write(&dev_priv->uncore, GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL); 393 393 394 394 if (hotplug_status) 395 - i9xx_hpd_irq_handler(dev_priv, hotplug_status); 395 + i9xx_hpd_irq_handler(display, hotplug_status); 396 396 397 397 if (iir & I915_MASTER_ERROR_INTERRUPT) 398 398 vlv_display_error_irq_handler(display, eir, dpinvgtt); ··· 952 952 static irqreturn_t i915_irq_handler(int irq, void *arg) 953 953 { 954 954 struct drm_i915_private *dev_priv = arg; 955 + struct intel_display *display = &dev_priv->display; 955 956 irqreturn_t ret = IRQ_NONE; 956 957 957 958 if (!intel_irqs_enabled(dev_priv)) ··· 975 974 976 975 if (I915_HAS_HOTPLUG(dev_priv) && 977 976 iir & I915_DISPLAY_PORT_INTERRUPT) 978 - hotplug_status = i9xx_hpd_irq_ack(dev_priv); 977 + hotplug_status = i9xx_hpd_irq_ack(display); 979 978 980 979 /* Call regardless, as some status bits might not be 981 980 * signalled in IIR */ ··· 993 992 i9xx_error_irq_handler(dev_priv, eir, eir_stuck); 994 993 995 994 if (hotplug_status) 996 - i9xx_hpd_irq_handler(dev_priv, hotplug_status); 995 + i9xx_hpd_irq_handler(display, hotplug_status); 997 996 998 997 i915_pipestat_irq_handler(dev_priv, iir, pipe_stats); 999 998 } while (0); ··· 1076 1075 static irqreturn_t i965_irq_handler(int irq, void *arg) 1077 1076 { 1078 1077 struct drm_i915_private *dev_priv = arg; 1078 + struct intel_display *display = &dev_priv->display; 1079 1079 irqreturn_t ret = IRQ_NONE; 1080 1080 1081 1081 if (!intel_irqs_enabled(dev_priv)) ··· 1098 1096 ret = IRQ_HANDLED; 1099 1097 1100 1098 if (iir & I915_DISPLAY_PORT_INTERRUPT) 1101 - hotplug_status = i9xx_hpd_irq_ack(dev_priv); 1099 + hotplug_status = i9xx_hpd_irq_ack(display); 1102 1100 1103 1101 /* Call regardless, as some status bits might not be 1104 1102 * signalled in IIR */ ··· 1121 1119 i9xx_error_irq_handler(dev_priv, eir, eir_stuck); 1122 1120 1123 1121 if (hotplug_status) 1124 - i9xx_hpd_irq_handler(dev_priv, hotplug_status); 1122 + i9xx_hpd_irq_handler(display, hotplug_status); 1125 1123 1126 1124 i965_pipestat_irq_handler(dev_priv, iir, pipe_stats); 1127 1125 } while (0);