ARM: dts: qcom-msm8974*: Consolidate I2C/UART/SDHCI

+17 -44

arch/arm/boot/dts/qcom-apq8074-dragonboard.dts

··· 26 26 status = "okay"; 27 27 clock-frequency = <200000>; 28 28 29 - pinctrl-0 = <&i2c11_pins>; 30 - pinctrl-names = "default"; 31 - 32 29 eeprom: eeprom@52 { 33 30 compatible = "atmel,24c128"; 34 31 reg = <0x52>; ··· 253 256 vmmc-supply = <&pm8941_l20>; 254 257 vqmmc-supply = <&pm8941_s3>; 255 258 256 - pinctrl-names = "default"; 257 - pinctrl-0 = <&sdhc1_pin_a>; 259 + pinctrl-names = "default", "sleep"; 260 + pinctrl-0 = <&sdc1_on>; 261 + pinctrl-1 = <&sdc1_off>; 258 262 }; 259 263 260 264 &sdhc_2 { 261 265 status = "okay"; 262 - cd-gpios = <&tlmm 62 0x1>; 263 - pinctrl-names = "default"; 264 - pinctrl-0 = <&sdhc2_pin_a>, <&sdhc2_cd_pin_a>; 265 266 267 + cd-gpios = <&tlmm 62 0x1>; 266 268 vmmc-supply = <&pm8941_l21>; 267 269 vqmmc-supply = <&pm8941_l13>; 270 + 271 + pinctrl-names = "default", "sleep"; 272 + pinctrl-0 = <&sdc2_on>; 273 + pinctrl-1 = <&sdc2_off>; 268 274 }; 269 275 270 276 &tlmm { 271 - i2c11_pins: i2c11 { 272 - mux { 273 - pins = "gpio83", "gpio84"; 274 - function = "blsp_i2c11"; 275 - }; 276 - }; 277 - 278 - spi8_default: spi8_default { 279 - mosi { 280 - pins = "gpio45"; 281 - function = "blsp_spi8"; 282 - }; 283 - miso { 284 - pins = "gpio46"; 285 - function = "blsp_spi8"; 286 - }; 287 - cs { 288 - pins = "gpio47"; 289 - function = "blsp_spi8"; 290 - }; 291 - clk { 292 - pins = "gpio48"; 293 - function = "blsp_spi8"; 294 - }; 295 - }; 296 - 297 - sdhc1_pin_a: sdhc1-pin-active { 277 + sdc1_on: sdc1-on { 298 278 clk { 299 279 pins = "sdc1_clk"; 300 280 drive-strength = <16>; ··· 285 311 }; 286 312 }; 287 313 288 - sdhc2_cd_pin_a: sdhc2-cd-pin-active { 289 - pins = "gpio62"; 290 - function = "gpio"; 291 - 292 - drive-strength = <2>; 293 - bias-disable; 294 - }; 295 - 296 - sdhc2_pin_a: sdhc2-pin-active { 314 + sdc2_on: sdc2-on { 297 315 clk { 298 316 pins = "sdc2_clk"; 299 317 drive-strength = <10>; ··· 296 330 pins = "sdc2_cmd", "sdc2_data"; 297 331 drive-strength = <6>; 298 332 bias-pull-up; 333 + }; 334 + 335 + cd { 336 + pins = "gpio62"; 337 + function = "gpio"; 338 + drive-strength = <2>; 339 + bias-disable; 299 340 }; 300 341 }; 301 342 };

+8 -6

arch/arm/boot/dts/qcom-msm8974-fairphone-fp2.dts

··· 321 321 vmmc-supply = <&pm8941_l20>; 322 322 vqmmc-supply = <&pm8941_s3>; 323 323 324 - pinctrl-names = "default"; 325 - pinctrl-0 = <&sdhc1_pin_a>; 324 + pinctrl-names = "default", "sleep"; 325 + pinctrl-0 = <&sdc1_on>; 326 + pinctrl-1 = <&sdc1_off>; 326 327 }; 327 328 328 329 &sdhc_2 { ··· 332 331 vmmc-supply = <&pm8941_l21>; 333 332 vqmmc-supply = <&pm8941_l13>; 334 333 335 - pinctrl-names = "default"; 336 - pinctrl-0 = <&sdhc2_pin_a>; 334 + pinctrl-names = "default", "sleep"; 335 + pinctrl-0 = <&sdc2_on>; 336 + pinctrl-1 = <&sdc2_off>; 337 337 }; 338 338 339 339 &tlmm { 340 - sdhc1_pin_a: sdhc1-pin-active { 340 + sdc1_on: sdc1-on { 341 341 clk { 342 342 pins = "sdc1_clk"; 343 343 drive-strength = <16>; ··· 352 350 }; 353 351 }; 354 352 355 - sdhc2_pin_a: sdhc2-pin-active { 353 + sdc2_on: sdc2-on { 356 354 clk { 357 355 pins = "sdc2_clk"; 358 356 drive-strength = <10>;

+8 -109

arch/arm/boot/dts/qcom-msm8974-lge-nexus5-hammerhead.dts

··· 59 59 status = "okay"; 60 60 clock-frequency = <100000>; 61 61 62 - pinctrl-names = "default"; 63 - pinctrl-0 = <&i2c1_pins>; 64 - 65 62 charger: bq24192@6b { 66 63 compatible = "ti,bq24192"; 67 64 reg = <0x6b>; ··· 90 93 status = "okay"; 91 94 clock-frequency = <355000>; 92 95 93 - pinctrl-names = "default"; 94 - pinctrl-0 = <&i2c2_pins>; 95 - 96 96 synaptics@70 { 97 97 compatible = "syna,rmi4-i2c"; 98 98 reg = <0x70>; ··· 120 126 status = "okay"; 121 127 clock-frequency = <100000>; 122 128 123 - pinctrl-names = "default"; 124 - pinctrl-0 = <&i2c3_pins>; 125 - 126 129 avago_apds993@39 { 127 130 compatible = "avago,apds9930"; 128 131 reg = <0x39>; ··· 134 143 &blsp2_i2c5 { 135 144 status = "okay"; 136 145 clock-frequency = <355000>; 137 - 138 - pinctrl-names = "default"; 139 - pinctrl-0 = <&i2c11_pins>; 140 146 141 147 led-controller@38 { 142 148 compatible = "ti,lm3630a"; ··· 155 167 &blsp2_i2c6 { 156 168 status = "okay"; 157 169 clock-frequency = <100000>; 158 - 159 - pinctrl-names = "default"; 160 - pinctrl-0 = <&i2c12_pins>; 161 170 162 171 mpu6515@68 { 163 172 compatible = "invensense,mpu6515"; ··· 196 211 197 212 &blsp2_uart4 { 198 213 status = "okay"; 199 - 200 - pinctrl-names = "default"; 201 - pinctrl-0 = <&blsp2_uart4_pin_a>; 202 214 203 215 bluetooth { 204 216 compatible = "brcm,bcm43438-bt"; ··· 515 533 vmmc-supply = <&pm8941_l20>; 516 534 vqmmc-supply = <&pm8941_s3>; 517 535 518 - pinctrl-names = "default"; 519 - pinctrl-0 = <&sdhc1_pin_a>; 536 + pinctrl-names = "default", "sleep"; 537 + pinctrl-0 = <&sdc1_on>; 538 + pinctrl-1 = <&sdc1_off>; 520 539 }; 521 540 522 541 &sdhc_2 { ··· 528 545 vqmmc-supply = <&pm8941_s3>; 529 546 non-removable; 530 547 531 - pinctrl-names = "default"; 532 - pinctrl-0 = <&sdhc2_pin_a>; 533 - 534 - #address-cells = <1>; 535 - #size-cells = <0>; 548 + pinctrl-names = "default", "sleep"; 549 + pinctrl-0 = <&sdc2_on>; 550 + pinctrl-1 = <&sdc2_off>; 536 551 537 552 bcrmf@1 { 538 553 compatible = "brcm,bcm4339-fmac", "brcm,bcm4329-fmac"; ··· 544 563 }; 545 564 546 565 &tlmm { 547 - sdhc1_pin_a: sdhc1-pin-active { 566 + sdc1_on: sdc1-on { 548 567 clk { 549 568 pins = "sdc1_clk"; 550 569 drive-strength = <16>; ··· 558 577 }; 559 578 }; 560 579 561 - sdhc2_pin_a: sdhc2-pin-active { 580 + sdc2_on: sdc2-on { 562 581 clk { 563 582 pins = "sdc2_clk"; 564 583 drive-strength = <6>; ··· 569 588 pins = "sdc2_cmd", "sdc2_data"; 570 589 drive-strength = <6>; 571 590 bias-pull-up; 572 - }; 573 - }; 574 - 575 - i2c1_pins: i2c1 { 576 - mux { 577 - pins = "gpio2", "gpio3"; 578 - function = "blsp_i2c1"; 579 - 580 - drive-strength = <2>; 581 - bias-disable; 582 - }; 583 - }; 584 - 585 - i2c2_pins: i2c2 { 586 - mux { 587 - pins = "gpio6", "gpio7"; 588 - function = "blsp_i2c2"; 589 - 590 - drive-strength = <2>; 591 - bias-disable; 592 - }; 593 - }; 594 - 595 - i2c3_pins: i2c3 { 596 - mux { 597 - pins = "gpio10", "gpio11"; 598 - function = "blsp_i2c3"; 599 - drive-strength = <2>; 600 - bias-disable; 601 - }; 602 - }; 603 - 604 - i2c11_pins: i2c11 { 605 - mux { 606 - pins = "gpio83", "gpio84"; 607 - function = "blsp_i2c11"; 608 - 609 - drive-strength = <2>; 610 - bias-disable; 611 - }; 612 - }; 613 - 614 - i2c12_pins: i2c12 { 615 - mux { 616 - pins = "gpio87", "gpio88"; 617 - function = "blsp_i2c12"; 618 - drive-strength = <2>; 619 - bias-disable; 620 591 }; 621 592 }; 622 593 ··· 624 691 shutdown { 625 692 pins = "gpio41"; 626 693 function = "gpio"; 627 - }; 628 - }; 629 - 630 - blsp2_uart4_pin_a: blsp2-uart4-pin-active { 631 - tx { 632 - pins = "gpio53"; 633 - function = "blsp_uart10"; 634 - 635 - drive-strength = <2>; 636 - bias-disable; 637 - }; 638 - 639 - rx { 640 - pins = "gpio54"; 641 - function = "blsp_uart10"; 642 - 643 - drive-strength = <2>; 644 - bias-pull-up; 645 - }; 646 - 647 - cts { 648 - pins = "gpio55"; 649 - function = "blsp_uart10"; 650 - 651 - drive-strength = <2>; 652 - bias-pull-up; 653 - }; 654 - 655 - rts { 656 - pins = "gpio56"; 657 - function = "blsp_uart10"; 658 - 659 - drive-strength = <2>; 660 - bias-disable; 661 694 }; 662 695 }; 663 696 };

+15 -48

arch/arm/boot/dts/qcom-msm8974-sony-xperia-rhine.dtsi

··· 55 55 status = "okay"; 56 56 clock-frequency = <355000>; 57 57 58 - pinctrl-names = "default"; 59 - pinctrl-0 = <&i2c2_pins>; 60 - 61 58 synaptics@2c { 62 59 compatible = "syna,rmi4-i2c"; 63 60 reg = <0x2c>; ··· 87 90 88 91 &blsp1_uart2 { 89 92 status = "okay"; 90 - 91 - pinctrl-names = "default"; 92 - pinctrl-0 = <&blsp1_uart2_pin_a>; 93 93 }; 94 94 95 95 &blsp2_dma { ··· 344 350 vmmc-supply = <&pm8941_l20>; 345 351 vqmmc-supply = <&pm8941_s3>; 346 352 347 - pinctrl-names = "default"; 348 - pinctrl-0 = <&sdhc1_pin_a>; 353 + pinctrl-names = "default", "sleep"; 354 + pinctrl-0 = <&sdc1_on>; 355 + pinctrl-1 = <&sdc1_off>; 349 356 }; 350 357 351 358 &sdhc_2 { ··· 357 362 358 363 cd-gpios = <&tlmm 62 GPIO_ACTIVE_LOW>; 359 364 360 - pinctrl-names = "default"; 361 - pinctrl-0 = <&sdhc2_pin_a>, <&sdhc2_cd_pin_a>; 365 + pinctrl-names = "default", "sleep"; 366 + pinctrl-0 = <&sdc2_on>; 367 + pinctrl-1 = <&sdc2_off>; 362 368 }; 363 369 364 370 &smbb { ··· 385 389 }; 386 390 }; 387 391 388 - blsp1_uart2_pin_a: blsp1-uart2-pin-active { 389 - rx { 390 - pins = "gpio5"; 391 - function = "blsp_uart2"; 392 - 393 - drive-strength = <2>; 394 - bias-pull-up; 395 - }; 396 - 397 - tx { 398 - pins = "gpio4"; 399 - function = "blsp_uart2"; 400 - 401 - drive-strength = <4>; 402 - bias-disable; 403 - }; 404 - }; 405 - 406 - i2c2_pins: i2c2 { 407 - mux { 408 - pins = "gpio6", "gpio7"; 409 - function = "blsp_i2c2"; 410 - 411 - drive-strength = <2>; 412 - bias-disable; 413 - }; 414 - }; 415 - 416 - sdhc1_pin_a: sdhc1-pin-active { 392 + sdc1_on: sdc1-on { 417 393 clk { 418 394 pins = "sdc1_clk"; 419 395 drive-strength = <16>; ··· 399 431 }; 400 432 }; 401 433 402 - sdhc2_cd_pin_a: sdhc2-cd-pin-active { 403 - pins = "gpio62"; 404 - function = "gpio"; 405 - 406 - drive-strength = <2>; 407 - bias-disable; 408 - }; 409 - 410 - sdhc2_pin_a: sdhc2-pin-active { 434 + sdc2_on: sdc-on { 411 435 clk { 412 436 pins = "sdc2_clk"; 413 437 drive-strength = <10>; ··· 410 450 pins = "sdc2_cmd", "sdc2_data"; 411 451 drive-strength = <6>; 412 452 bias-pull-up; 453 + }; 454 + 455 + cd { 456 + pins = "gpio62"; 457 + function = "gpio"; 458 + drive-strength = <2>; 459 + bias-disable; 413 460 }; 414 461 }; 415 462 };

+243 -2

arch/arm/boot/dts/qcom-msm8974.dtsi

··· 466 466 clock-names = "core", "iface", "xo"; 467 467 bus-width = <4>; 468 468 469 + #address-cells = <1>; 470 + #size-cells = <0>; 471 + 469 472 status = "disabled"; 470 473 }; 471 474 ··· 484 481 <&xo_board>; 485 482 clock-names = "core", "iface", "xo"; 486 483 bus-width = <4>; 484 + 485 + #address-cells = <1>; 486 + #size-cells = <0>; 487 487 488 488 status = "disabled"; 489 489 }; ··· 516 510 interrupts = <0 95 IRQ_TYPE_LEVEL_HIGH>; 517 511 clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; 518 512 clock-names = "core", "iface"; 513 + pinctrl-names = "default", "sleep"; 514 + pinctrl-0 = <&blsp1_i2c1_default>; 515 + pinctrl-1 = <&blsp1_i2c1_sleep>; 519 516 #address-cells = <1>; 520 517 #size-cells = <0>; 521 518 }; ··· 530 521 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 531 522 clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; 532 523 clock-names = "core", "iface"; 524 + pinctrl-names = "default", "sleep"; 525 + pinctrl-0 = <&blsp1_i2c2_default>; 526 + pinctrl-1 = <&blsp1_i2c2_sleep>; 533 527 #address-cells = <1>; 534 528 #size-cells = <0>; 535 529 }; ··· 544 532 interrupts = <0 97 IRQ_TYPE_LEVEL_HIGH>; 545 533 clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; 546 534 clock-names = "core", "iface"; 535 + pinctrl-names = "default", "sleep"; 536 + pinctrl-0 = <&blsp1_i2c3_default>; 537 + pinctrl-1 = <&blsp1_i2c3_sleep>; 547 538 #address-cells = <1>; 548 539 #size-cells = <0>; 549 540 }; ··· 558 543 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 559 544 clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; 560 545 clock-names = "core", "iface"; 546 + pinctrl-names = "default", "sleep"; 547 + pinctrl-0 = <&blsp1_i2c6_default>; 548 + pinctrl-1 = <&blsp1_i2c6_sleep>; 561 549 #address-cells = <1>; 562 550 #size-cells = <0>; 563 551 }; ··· 609 591 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 610 592 clocks = <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>; 611 593 clock-names = "core", "iface"; 594 + pinctrl-names = "default", "sleep"; 595 + pinctrl-0 = <&blsp2_i2c2_default>; 596 + pinctrl-1 = <&blsp2_i2c2_sleep>; 612 597 #address-cells = <1>; 613 598 #size-cells = <0>; 614 599 }; ··· 623 602 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 624 603 clocks = <&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>; 625 604 clock-names = "core", "iface"; 626 - #address-cells = <1>; 627 - #size-cells = <0>; 628 605 dmas = <&blsp2_dma 20>, <&blsp2_dma 21>; 629 606 dma-names = "tx", "rx"; 607 + pinctrl-names = "default", "sleep"; 608 + pinctrl-0 = <&blsp2_i2c5_default>; 609 + pinctrl-1 = <&blsp2_i2c5_sleep>; 610 + #address-cells = <1>; 611 + #size-cells = <0>; 630 612 }; 631 613 632 614 blsp2_i2c6: i2c@f9968000 { ··· 1209 1185 interrupt-controller; 1210 1186 #interrupt-cells = <2>; 1211 1187 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 1188 + 1189 + sdc1_off: sdc1-off { 1190 + clk { 1191 + pins = "sdc1_clk"; 1192 + bias-disable; 1193 + drive-strength = <2>; 1194 + }; 1195 + 1196 + cmd { 1197 + pins = "sdc1_cmd"; 1198 + bias-pull-up; 1199 + drive-strength = <2>; 1200 + }; 1201 + 1202 + data { 1203 + pins = "sdc1_data"; 1204 + bias-pull-up; 1205 + drive-strength = <2>; 1206 + }; 1207 + }; 1208 + 1209 + sdc2_off: sdc2-off { 1210 + clk { 1211 + pins = "sdc2_clk"; 1212 + bias-disable; 1213 + drive-strength = <2>; 1214 + }; 1215 + 1216 + cmd { 1217 + pins = "sdc2_cmd"; 1218 + bias-pull-up; 1219 + drive-strength = <2>; 1220 + }; 1221 + 1222 + data { 1223 + pins = "sdc2_data"; 1224 + bias-pull-up; 1225 + drive-strength = <2>; 1226 + }; 1227 + 1228 + cd { 1229 + pins = "gpio54"; 1230 + bias-disable; 1231 + drive-strength = <2>; 1232 + }; 1233 + }; 1234 + 1235 + blsp1_uart2_active: blsp1-uart2-active { 1236 + rx { 1237 + pins = "gpio5"; 1238 + function = "blsp_uart2"; 1239 + drive-strength = <2>; 1240 + bias-pull-up; 1241 + }; 1242 + 1243 + tx { 1244 + pins = "gpio4"; 1245 + function = "blsp_uart2"; 1246 + drive-strength = <4>; 1247 + bias-disable; 1248 + }; 1249 + }; 1250 + 1251 + blsp2_uart1_active: blsp2-uart1-active { 1252 + tx-rts { 1253 + pins = "gpio41", "gpio44"; 1254 + function = "blsp_uart7"; 1255 + drive-strength = <2>; 1256 + bias-disable; 1257 + }; 1258 + 1259 + rx-cts { 1260 + pins = "gpio42", "gpio43"; 1261 + function = "blsp_uart7"; 1262 + drive-strength = <2>; 1263 + bias-pull-up; 1264 + }; 1265 + }; 1266 + 1267 + blsp2_uart1_sleep: blsp2-uart1-sleep { 1268 + pins = "gpio41", "gpio42", "gpio43", "gpio44"; 1269 + function = "gpio"; 1270 + drive-strength = <2>; 1271 + bias-pull-down; 1272 + }; 1273 + 1274 + blsp2_uart4_active: blsp2-uart4-active { 1275 + tx-rts { 1276 + pins = "gpio53", "gpio56"; 1277 + function = "blsp_uart10"; 1278 + drive-strength = <2>; 1279 + bias-disable; 1280 + }; 1281 + 1282 + rx-cts { 1283 + pins = "gpio54", "gpio55"; 1284 + function = "blsp_uart10"; 1285 + drive-strength = <2>; 1286 + bias-pull-up; 1287 + }; 1288 + }; 1289 + 1290 + blsp1_i2c1_default: blsp1-i2c1-default { 1291 + pins = "gpio2", "gpio3"; 1292 + function = "blsp_i2c1"; 1293 + drive-strength = <2>; 1294 + bias-disable; 1295 + }; 1296 + 1297 + blsp1_i2c1_sleep: blsp1-i2c1-sleep { 1298 + pins = "gpio2", "gpio3"; 1299 + function = "blsp_i2c1"; 1300 + drive-strength = <2>; 1301 + bias-pull-up; 1302 + }; 1303 + 1304 + blsp1_i2c2_default: blsp1-i2c2-default { 1305 + pins = "gpio6", "gpio7"; 1306 + function = "blsp_i2c2"; 1307 + drive-strength = <2>; 1308 + bias-disable; 1309 + }; 1310 + 1311 + blsp1_i2c2_sleep: blsp1-i2c2-sleep { 1312 + pins = "gpio6", "gpio7"; 1313 + function = "blsp_i2c2"; 1314 + drive-strength = <2>; 1315 + bias-pull-up; 1316 + }; 1317 + 1318 + blsp1_i2c3_default: blsp1-i2c3-default { 1319 + pins = "gpio10", "gpio11"; 1320 + function = "blsp_i2c3"; 1321 + drive-strength = <2>; 1322 + bias-disable; 1323 + }; 1324 + 1325 + blsp1_i2c3_sleep: blsp1-i2c3-sleep { 1326 + pins = "gpio10", "gpio11"; 1327 + function = "blsp_i2c3"; 1328 + drive-strength = <2>; 1329 + bias-pull-up; 1330 + }; 1331 + 1332 + /* BLSP1_I2C4 info is missing */ 1333 + 1334 + /* BLSP1_I2C5 info is missing */ 1335 + 1336 + blsp1_i2c6_default: blsp1-i2c6-default { 1337 + pins = "gpio29", "gpio30"; 1338 + function = "blsp_i2c6"; 1339 + drive-strength = <2>; 1340 + bias-disable; 1341 + }; 1342 + 1343 + blsp1_i2c6_sleep: blsp1-i2c6-sleep { 1344 + pins = "gpio29", "gpio30"; 1345 + function = "blsp_i2c6"; 1346 + drive-strength = <2>; 1347 + bias-pull-up; 1348 + }; 1349 + /* 6 interfaces per QUP, BLSP2 indexes are numbered (n)+6 */ 1350 + 1351 + /* BLSP2_I2C1 info is missing */ 1352 + 1353 + blsp2_i2c2_default: blsp2-i2c2-default { 1354 + pins = "gpio47", "gpio48"; 1355 + function = "blsp_i2c8"; 1356 + drive-strength = <2>; 1357 + bias-disable; 1358 + }; 1359 + 1360 + blsp2_i2c2_sleep: blsp2-i2c2-sleep { 1361 + pins = "gpio47", "gpio48"; 1362 + function = "blsp_i2c8"; 1363 + drive-strength = <2>; 1364 + bias-pull-up; 1365 + }; 1366 + 1367 + /* BLSP2_I2C3 info is missing */ 1368 + 1369 + /* BLSP2_I2C4 info is missing */ 1370 + 1371 + blsp2_i2c5_default: blsp2-i2c5-default { 1372 + pins = "gpio83", "gpio84"; 1373 + function = "blsp_i2c11"; 1374 + drive-strength = <2>; 1375 + bias-disable; 1376 + }; 1377 + 1378 + blsp2_i2c5_sleep: blsp2-i2c5-sleep { 1379 + pins = "gpio83", "gpio84"; 1380 + function = "blsp_i2c11"; 1381 + drive-strength = <2>; 1382 + bias-pull-up; 1383 + }; 1384 + 1385 + /* BLSP2_I2C6 info is missing - nobody uses it though? */ 1386 + 1387 + spi8_default: spi8_default { 1388 + mosi { 1389 + pins = "gpio45"; 1390 + function = "blsp_spi8"; 1391 + }; 1392 + miso { 1393 + pins = "gpio46"; 1394 + function = "blsp_spi8"; 1395 + }; 1396 + cs { 1397 + pins = "gpio47"; 1398 + function = "blsp_spi8"; 1399 + }; 1400 + clk { 1401 + pins = "gpio48"; 1402 + function = "blsp_spi8"; 1403 + }; 1404 + }; 1212 1405 }; 1213 1406 1214 1407 mmcc: clock-controller@fd8c0000 {

+16 -61

arch/arm/boot/dts/qcom-msm8974pro-samsung-klte.dts

··· 161 161 &blsp1_i2c2 { 162 162 status = "okay"; 163 163 164 - pinctrl-names = "default"; 165 - pinctrl-0 = <&i2c2_pins>; 166 - 167 164 touchscreen@20 { 168 165 compatible = "syna,rmi4-i2c"; 169 166 reg = <0x20>; ··· 193 196 194 197 &blsp1_i2c6 { 195 198 status = "okay"; 196 - 197 - pinctrl-names = "default"; 198 - pinctrl-0 = <&i2c6_pins>; 199 199 200 200 pmic@60 { 201 201 reg = <0x60>; ··· 293 299 294 300 &blsp2_i2c6 { 295 301 status = "okay"; 296 - 297 - pinctrl-names = "default"; 298 - pinctrl-0 = <&i2c12_pins>; 299 302 300 303 fuelgauge@36 { 301 304 compatible = "maxim,max17048"; ··· 658 667 vmmc-supply = <&pma8084_l20>; 659 668 vqmmc-supply = <&pma8084_s4>; 660 669 661 - pinctrl-names = "default"; 662 - pinctrl-0 = <&sdhc1_pin_a>; 670 + pinctrl-names = "default", "sleep"; 671 + pinctrl-0 = <&sdc1_on>; 672 + pinctrl-1 = <&sdc1_off>; 663 673 }; 664 674 665 675 &sdhc_2 { 666 676 status = "okay"; 667 677 max-frequency = <100000000>; 668 - 669 - pinctrl-names = "default"; 670 - pinctrl-0 = <&sdhc3_pin_a>; 671 - 672 678 vmmc-supply = <&vreg_wlan>; 673 679 vqmmc-supply = <&pma8084_s4>; 674 - 675 680 non-removable; 676 681 677 - #address-cells = <1>; 678 - #size-cells = <0>; 682 + pinctrl-names = "default", "sleep"; 683 + pinctrl-0 = <&sdc2_on>; 684 + pinctrl-1 = <&sdc2_off>; 679 685 680 686 wifi@1 { 681 687 reg = <1>; ··· 690 702 &sdhc_3 { 691 703 status = "okay"; 692 704 max-frequency = <100000000>; 693 - 694 705 vmmc-supply = <&pma8084_l21>; 695 706 vqmmc-supply = <&pma8084_l13>; 696 707 ··· 699 712 * cd-gpios the driver resorts to polling, so hotplug works. 700 713 */ 701 714 pinctrl-names = "default"; 702 - pinctrl-0 = <&sdhc2_pin_a /* &sdhc2_cd_pin */>; 715 + pinctrl-0 = <&sdc3_on /* &sdhc3_cd_pin */>; 703 716 /* cd-gpios = <&tlmm 62 GPIO_ACTIVE_LOW>; */ 704 717 }; 705 718 706 719 &tlmm { 720 + /* This seems suspicious, but somebody with this device should look into it. */ 707 721 blsp2_uart2_pins_active: blsp2-uart2-pins-active { 708 722 pins = "gpio45", "gpio46", "gpio47", "gpio48"; 709 723 function = "blsp_uart8"; ··· 734 746 }; 735 747 }; 736 748 737 - sdhc1_pin_a: sdhc1-pin-active { 749 + sdc1_on: sdhc1-on { 738 750 clk { 739 751 pins = "sdc1_clk"; 740 752 drive-strength = <4>; ··· 748 760 }; 749 761 }; 750 762 751 - sdhc2_pin_a: sdhc2-pin-active { 752 - clk-cmd-data { 753 - pins = "gpio35", "gpio36", "gpio37", "gpio38", 754 - "gpio39", "gpio40"; 755 - function = "sdc3"; 756 - drive-strength = <8>; 757 - bias-disable; 758 - }; 763 + sdc3_on: sdc3-on { 764 + pins = "gpio35", "gpio36", "gpio37", "gpio38", "gpio39", "gpio40"; 765 + function = "sdc3"; 766 + drive-strength = <8>; 767 + bias-disable; 759 768 }; 760 769 761 - sdhc2_cd_pin: sdhc2-cd { 770 + sdhc3_cd_pin: sdc3-cd-on { 762 771 pins = "gpio62"; 763 772 function = "gpio"; 764 773 ··· 763 778 bias-disable; 764 779 }; 765 780 766 - sdhc3_pin_a: sdhc3-pin-active { 781 + sdc2_on: sdhc2-on { 767 782 clk { 768 783 pins = "sdc2_clk"; 769 784 drive-strength = <6>; ··· 774 789 pins = "sdc2_cmd", "sdc2_data"; 775 790 drive-strength = <6>; 776 791 bias-pull-up; 777 - }; 778 - }; 779 - 780 - i2c2_pins: i2c2 { 781 - mux { 782 - pins = "gpio6", "gpio7"; 783 - function = "blsp_i2c2"; 784 - 785 - drive-strength = <2>; 786 - bias-disable; 787 - }; 788 - }; 789 - 790 - i2c6_pins: i2c6 { 791 - mux { 792 - pins = "gpio29", "gpio30"; 793 - function = "blsp_i2c6"; 794 - 795 - drive-strength = <2>; 796 - bias-disable; 797 - }; 798 - }; 799 - 800 - i2c12_pins: i2c12 { 801 - mux { 802 - pins = "gpio87", "gpio88"; 803 - function = "blsp_i2c12"; 804 - 805 - drive-strength = <2>; 806 - bias-disable; 807 792 }; 808 793 }; 809 794

+24 -117

arch/arm/boot/dts/qcom-msm8974pro-sony-xperia-shinano-castor.dts

··· 99 99 100 100 &blsp1_uart2 { 101 101 status = "okay"; 102 - 103 - pinctrl-names = "default"; 104 - pinctrl-0 = <&blsp1_uart2_pin_a>; 105 102 }; 106 103 107 104 &blsp2_i2c2 { 108 105 status = "okay"; 109 106 clock-frequency = <355000>; 110 - 111 - pinctrl-names = "default"; 112 - pinctrl-0 = <&i2c8_pins>; 113 107 114 108 synaptics@2c { 115 109 compatible = "syna,rmi4-i2c"; ··· 139 145 &blsp2_i2c5 { 140 146 status = "okay"; 141 147 clock-frequency = <355000>; 142 - 143 - pinctrl-names = "default"; 144 - pinctrl-0 = <&i2c11_pins>; 145 148 146 149 lp8566_wled: backlight@2c { 147 150 compatible = "ti,lp8556"; ··· 198 207 &blsp2_uart1 { 199 208 status = "okay"; 200 209 201 - pinctrl-names = "default"; 202 - pinctrl-0 = <&blsp2_uart7_pin_a>; 203 - 204 210 bluetooth { 205 211 compatible = "brcm,bcm43438-bt"; 206 212 max-speed = <3000000>; 207 213 208 214 pinctrl-names = "default"; 209 - pinctrl-0 = <&bt_host_wake_pin>, 210 - <&bt_dev_wake_pin>, 211 - <&bt_reg_on_pin>; 215 + pinctrl-0 = <&bt_host_wake_pin>, <&bt_dev_wake_pin>, <&bt_reg_on_pin>; 212 216 213 217 host-wakeup-gpios = <&tlmm 95 GPIO_ACTIVE_HIGH>; 214 218 device-wakeup-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>; ··· 464 478 vmmc-supply = <&pm8941_l20>; 465 479 vqmmc-supply = <&pm8941_s3>; 466 480 467 - pinctrl-names = "default"; 468 - pinctrl-0 = <&sdhc1_pin_a>; 481 + pinctrl-names = "default", "sleep"; 482 + pinctrl-0 = <&sdc1_on>; 483 + pinctrl-1 = <&sdc1_off>; 469 484 }; 470 485 471 486 &sdhc_2 { ··· 477 490 478 491 cd-gpios = <&tlmm 62 GPIO_ACTIVE_LOW>; 479 492 480 - pinctrl-names = "default"; 481 - pinctrl-0 = <&sdhc2_pin_a>, <&sdhc2_cd_pin_a>; 493 + pinctrl-names = "default", "sleep"; 494 + pinctrl-0 = <&sdc2_on>; 495 + pinctrl-1 = <&sdc2_off>; 482 496 }; 483 497 484 498 &sdhc_3 { ··· 490 502 non-removable; 491 503 492 504 pinctrl-names = "default"; 493 - pinctrl-0 = <&sdhc3_pin_a>; 505 + pinctrl-0 = <&sdc3_on>; 494 506 495 507 #address-cells = <1>; 496 508 #size-cells = <0>; ··· 518 530 }; 519 531 520 532 &tlmm { 521 - blsp1_uart2_pin_a: blsp1-uart2-pin-active { 522 - rx { 523 - pins = "gpio5"; 524 - function = "blsp_uart2"; 525 - 526 - drive-strength = <2>; 527 - bias-pull-up; 528 - }; 529 - 530 - tx { 531 - pins = "gpio4"; 532 - function = "blsp_uart2"; 533 - 534 - drive-strength = <4>; 535 - bias-disable; 536 - }; 537 - }; 538 - 539 - blsp2_uart7_pin_a: blsp2-uart7-pin-active { 540 - tx { 541 - pins = "gpio41"; 542 - function = "blsp_uart7"; 543 - 544 - drive-strength = <2>; 545 - bias-disable; 546 - }; 547 - 548 - rx { 549 - pins = "gpio42"; 550 - function = "blsp_uart7"; 551 - 552 - drive-strength = <2>; 553 - bias-pull-up; 554 - }; 555 - 556 - cts { 557 - pins = "gpio43"; 558 - function = "blsp_uart7"; 559 - 560 - drive-strength = <2>; 561 - bias-pull-up; 562 - }; 563 - 564 - rts { 565 - pins = "gpio44"; 566 - function = "blsp_uart7"; 567 - 568 - drive-strength = <2>; 569 - bias-disable; 570 - }; 571 - }; 572 - 573 - i2c8_pins: i2c8 { 574 - mux { 575 - pins = "gpio47", "gpio48"; 576 - function = "blsp_i2c8"; 577 - 578 - drive-strength = <2>; 579 - bias-disable; 580 - }; 581 - }; 582 - 583 - i2c11_pins: i2c11 { 584 - mux { 585 - pins = "gpio83", "gpio84"; 586 - function = "blsp_i2c11"; 587 - 588 - drive-strength = <2>; 589 - bias-disable; 590 - }; 591 - }; 592 - 593 533 lcd_backlight_en_pin_a: lcd-backlight-vddio { 594 534 pins = "gpio69"; 595 535 drive-strength = <10>; ··· 525 609 bias-disable; 526 610 }; 527 611 528 - sdhc1_pin_a: sdhc1-pin-active { 612 + sdc1_on: sdc1-on { 529 613 clk { 530 614 pins = "sdc1_clk"; 531 615 drive-strength = <16>; ··· 539 623 }; 540 624 }; 541 625 542 - sdhc2_cd_pin_a: sdhc2-cd-pin-active { 543 - pins = "gpio62"; 544 - function = "gpio"; 545 - 546 - drive-strength = <2>; 547 - bias-disable; 548 - }; 549 - 550 - sdhc2_pin_a: sdhc2-pin-active { 626 + sdc2_on: sdc2-on { 551 627 clk { 552 628 pins = "sdc2_clk"; 553 629 drive-strength = <6>; ··· 551 643 drive-strength = <6>; 552 644 bias-pull-up; 553 645 }; 646 + 647 + cd { 648 + pins = "gpio62"; 649 + function = "gpio"; 650 + drive-strength = <2>; 651 + bias-disable; 652 + }; 554 653 }; 555 654 556 - sdhc3_pin_a: sdhc3-pin-active { 655 + sdc3_on: sdc3-on { 557 656 clk { 558 657 pins = "gpio40"; 559 658 function = "sdc3"; 560 - 561 659 drive-strength = <10>; 562 660 bias-disable; 563 661 }; ··· 571 657 cmd { 572 658 pins = "gpio39"; 573 659 function = "sdc3"; 574 - 575 660 drive-strength = <10>; 576 661 bias-pull-up; 577 662 }; ··· 578 665 data { 579 666 pins = "gpio35", "gpio36", "gpio37", "gpio38"; 580 667 function = "sdc3"; 581 - 582 668 drive-strength = <10>; 583 669 bias-pull-up; 584 670 }; 585 671 }; 586 672 587 - ts_int_pin: synaptics { 588 - pin { 589 - pins = "gpio86"; 590 - function = "gpio"; 591 - 592 - drive-strength = <2>; 593 - bias-disable; 594 - input-enable; 595 - }; 673 + ts_int_pin: ts-int-pin { 674 + pins = "gpio86"; 675 + function = "gpio"; 676 + drive-strength = <2>; 677 + bias-disable; 678 + input-enable; 596 679 }; 597 680 598 681 bt_host_wake_pin: bt-host-wake { 599 682 pins = "gpio95"; 600 683 function = "gpio"; 601 - 602 684 drive-strength = <2>; 603 685 bias-disable; 604 686 output-low; ··· 602 694 bt_dev_wake_pin: bt-dev-wake { 603 695 pins = "gpio96"; 604 696 function = "gpio"; 605 - 606 697 drive-strength = <2>; 607 698 bias-disable; 608 699 };