commit 1dfa2e77bbd5053d11f8f3f8987b4503badafb09 · tjh.dev/kernel

tjh.dev / kernel

Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git

kernel os linux

Merge tag 'char-misc-5.13-rc6' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc

Pull char/misc driver fixes from Greg KH:
"Here are some small misc driver fixes for 5.13-rc6 that fix some
reported problems:

- Tiny phy driver fixes for reported issues

- rtsx regression for when the device suspended

- mhi driver fix for a use-after-free

All of these have been in linux-next for a few days with no reported
issues"

* tag 'char-misc-5.13-rc6' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc:
misc: rtsx: separate aspm mode into MODE_REG and MODE_CFG
bus: mhi: pci-generic: Fix hibernation
bus: mhi: pci_generic: Fix possible use-after-free in mhi_pci_remove()
bus: mhi: pci_generic: T99W175: update channel name from AT to DUN
phy: Sparx5 Eth SerDes: check return value after calling platform_get_resource()
phy: ralink: phy-mt7621-pci: drop 'of_match_ptr' to fix -Wunused-const-variable
phy: ti: Fix an error code in wiz_probe()
phy: phy-mtk-tphy: Fix some resource leaks in mtk_phy_init()
phy: cadence: Sierra: Fix error return code in cdns_sierra_phy_probe()
phy: usb: Fix misuse of IS_ENABLED

Linus Torvalds 4 years ago 1dfa2e77 141415d7

+93 -20

17 changed files

expand all

unified split

drivers

bus

mhi

pci_generic.c

misc

cardreader

rtl8411.c

rts5209.c

rts5227.c

rts5228.c

rts5229.c

rts5249.c

rts5260.c

rts5261.c

rtsx_pcr.c

phy

broadcom

phy-brcm-usb-init.h

cadence

phy-cadence-sierra.c

mediatek

phy-mtk-tphy.c

microchip

sparx5_serdes.c

ralink

phy-mt7621-pci.c

phy-j721e-wiz.c

include

linux

rtsx_pci.h

+38 -4

drivers/bus/mhi/pci_generic.c

··· 311 MHI_CHANNEL_CONFIG_DL(5, "DIAG", 32, 1), 312 MHI_CHANNEL_CONFIG_UL(12, "MBIM", 32, 0), 313 MHI_CHANNEL_CONFIG_DL(13, "MBIM", 32, 0), 314 - MHI_CHANNEL_CONFIG_UL(32, "AT", 32, 0), 315 - MHI_CHANNEL_CONFIG_DL(33, "AT", 32, 0), 316 MHI_CHANNEL_CONFIG_HW_UL(100, "IP_HW0_MBIM", 128, 2), 317 MHI_CHANNEL_CONFIG_HW_DL(101, "IP_HW0_MBIM", 128, 3), 318 }; ··· 708 struct mhi_pci_device *mhi_pdev = pci_get_drvdata(pdev); 709 struct mhi_controller *mhi_cntrl = &mhi_pdev->mhi_cntrl; 710 711 - del_timer(&mhi_pdev->health_check_timer); 712 cancel_work_sync(&mhi_pdev->recovery_work); 713 714 if (test_and_clear_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status)) { ··· 935 return ret; 936 } 937 938 static const struct dev_pm_ops mhi_pci_pm_ops = { 939 SET_RUNTIME_PM_OPS(mhi_pci_runtime_suspend, mhi_pci_runtime_resume, NULL) 940 - SET_SYSTEM_SLEEP_PM_OPS(mhi_pci_suspend, mhi_pci_resume) 941 }; 942 943 static struct pci_driver mhi_pci_driver = {

··· 311 MHI_CHANNEL_CONFIG_DL(5, "DIAG", 32, 1), 312 MHI_CHANNEL_CONFIG_UL(12, "MBIM", 32, 0), 313 MHI_CHANNEL_CONFIG_DL(13, "MBIM", 32, 0), 314 + MHI_CHANNEL_CONFIG_UL(32, "DUN", 32, 0), 315 + MHI_CHANNEL_CONFIG_DL(33, "DUN", 32, 0), 316 MHI_CHANNEL_CONFIG_HW_UL(100, "IP_HW0_MBIM", 128, 2), 317 MHI_CHANNEL_CONFIG_HW_DL(101, "IP_HW0_MBIM", 128, 3), 318 }; ··· 708 struct mhi_pci_device *mhi_pdev = pci_get_drvdata(pdev); 709 struct mhi_controller *mhi_cntrl = &mhi_pdev->mhi_cntrl; 710 711 + del_timer_sync(&mhi_pdev->health_check_timer); 712 cancel_work_sync(&mhi_pdev->recovery_work); 713 714 if (test_and_clear_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status)) { ··· 935 return ret; 936 } 937 938 + static int __maybe_unused mhi_pci_freeze(struct device *dev) 939 + { 940 + struct mhi_pci_device *mhi_pdev = dev_get_drvdata(dev); 941 + struct mhi_controller *mhi_cntrl = &mhi_pdev->mhi_cntrl; 942 + 943 + /* We want to stop all operations, hibernation does not guarantee that 944 + * device will be in the same state as before freezing, especially if 945 + * the intermediate restore kernel reinitializes MHI device with new 946 + * context. 947 + */ 948 + if (test_and_clear_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status)) { 949 + mhi_power_down(mhi_cntrl, false); 950 + mhi_unprepare_after_power_down(mhi_cntrl); 951 + } 952 + 953 + return 0; 954 + } 955 + 956 + static int __maybe_unused mhi_pci_restore(struct device *dev) 957 + { 958 + struct mhi_pci_device *mhi_pdev = dev_get_drvdata(dev); 959 + 960 + /* Reinitialize the device */ 961 + queue_work(system_long_wq, &mhi_pdev->recovery_work); 962 + 963 + return 0; 964 + } 965 + 966 static const struct dev_pm_ops mhi_pci_pm_ops = { 967 SET_RUNTIME_PM_OPS(mhi_pci_runtime_suspend, mhi_pci_runtime_resume, NULL) 968 + #ifdef CONFIG_PM_SLEEP 969 + .suspend = mhi_pci_suspend, 970 + .resume = mhi_pci_resume, 971 + .freeze = mhi_pci_freeze, 972 + .thaw = mhi_pci_restore, 973 + .restore = mhi_pci_restore, 974 + #endif 975 }; 976 977 static struct pci_driver mhi_pci_driver = {

drivers/misc/cardreader/rtl8411.c

··· 468 pcr->sd30_drive_sel_1v8 = DRIVER_TYPE_B; 469 pcr->sd30_drive_sel_3v3 = DRIVER_TYPE_D; 470 pcr->aspm_en = ASPM_L1_EN; 471 pcr->tx_initial_phase = SET_CLOCK_PHASE(23, 7, 14); 472 pcr->rx_initial_phase = SET_CLOCK_PHASE(4, 3, 10); 473 pcr->ic_version = rtl8411_get_ic_version(pcr);

··· 468 pcr->sd30_drive_sel_1v8 = DRIVER_TYPE_B; 469 pcr->sd30_drive_sel_3v3 = DRIVER_TYPE_D; 470 pcr->aspm_en = ASPM_L1_EN; 471 + pcr->aspm_mode = ASPM_MODE_CFG; 472 pcr->tx_initial_phase = SET_CLOCK_PHASE(23, 7, 14); 473 pcr->rx_initial_phase = SET_CLOCK_PHASE(4, 3, 10); 474 pcr->ic_version = rtl8411_get_ic_version(pcr);

drivers/misc/cardreader/rts5209.c

··· 255 pcr->sd30_drive_sel_1v8 = DRIVER_TYPE_B; 256 pcr->sd30_drive_sel_3v3 = DRIVER_TYPE_D; 257 pcr->aspm_en = ASPM_L1_EN; 258 pcr->tx_initial_phase = SET_CLOCK_PHASE(27, 27, 16); 259 pcr->rx_initial_phase = SET_CLOCK_PHASE(24, 6, 5); 260

··· 255 pcr->sd30_drive_sel_1v8 = DRIVER_TYPE_B; 256 pcr->sd30_drive_sel_3v3 = DRIVER_TYPE_D; 257 pcr->aspm_en = ASPM_L1_EN; 258 + pcr->aspm_mode = ASPM_MODE_CFG; 259 pcr->tx_initial_phase = SET_CLOCK_PHASE(27, 27, 16); 260 pcr->rx_initial_phase = SET_CLOCK_PHASE(24, 6, 5); 261

drivers/misc/cardreader/rts5227.c

··· 358 pcr->sd30_drive_sel_1v8 = CFG_DRIVER_TYPE_B; 359 pcr->sd30_drive_sel_3v3 = CFG_DRIVER_TYPE_B; 360 pcr->aspm_en = ASPM_L1_EN; 361 pcr->tx_initial_phase = SET_CLOCK_PHASE(27, 27, 15); 362 pcr->rx_initial_phase = SET_CLOCK_PHASE(30, 7, 7); 363 ··· 484 485 rts5227_init_params(pcr); 486 pcr->ops = &rts522a_pcr_ops; 487 pcr->tx_initial_phase = SET_CLOCK_PHASE(20, 20, 11); 488 pcr->reg_pm_ctrl3 = RTS522A_PM_CTRL3; 489

··· 358 pcr->sd30_drive_sel_1v8 = CFG_DRIVER_TYPE_B; 359 pcr->sd30_drive_sel_3v3 = CFG_DRIVER_TYPE_B; 360 pcr->aspm_en = ASPM_L1_EN; 361 + pcr->aspm_mode = ASPM_MODE_CFG; 362 pcr->tx_initial_phase = SET_CLOCK_PHASE(27, 27, 15); 363 pcr->rx_initial_phase = SET_CLOCK_PHASE(30, 7, 7); 364 ··· 483 484 rts5227_init_params(pcr); 485 pcr->ops = &rts522a_pcr_ops; 486 + pcr->aspm_mode = ASPM_MODE_REG; 487 pcr->tx_initial_phase = SET_CLOCK_PHASE(20, 20, 11); 488 pcr->reg_pm_ctrl3 = RTS522A_PM_CTRL3; 489

drivers/misc/cardreader/rts5228.c

··· 718 pcr->sd30_drive_sel_1v8 = CFG_DRIVER_TYPE_B; 719 pcr->sd30_drive_sel_3v3 = CFG_DRIVER_TYPE_B; 720 pcr->aspm_en = ASPM_L1_EN; 721 pcr->tx_initial_phase = SET_CLOCK_PHASE(28, 27, 11); 722 pcr->rx_initial_phase = SET_CLOCK_PHASE(24, 6, 5); 723

··· 718 pcr->sd30_drive_sel_1v8 = CFG_DRIVER_TYPE_B; 719 pcr->sd30_drive_sel_3v3 = CFG_DRIVER_TYPE_B; 720 pcr->aspm_en = ASPM_L1_EN; 721 + pcr->aspm_mode = ASPM_MODE_REG; 722 pcr->tx_initial_phase = SET_CLOCK_PHASE(28, 27, 11); 723 pcr->rx_initial_phase = SET_CLOCK_PHASE(24, 6, 5); 724

drivers/misc/cardreader/rts5229.c

··· 246 pcr->sd30_drive_sel_1v8 = DRIVER_TYPE_B; 247 pcr->sd30_drive_sel_3v3 = DRIVER_TYPE_D; 248 pcr->aspm_en = ASPM_L1_EN; 249 pcr->tx_initial_phase = SET_CLOCK_PHASE(27, 27, 15); 250 pcr->rx_initial_phase = SET_CLOCK_PHASE(30, 6, 6); 251

··· 246 pcr->sd30_drive_sel_1v8 = DRIVER_TYPE_B; 247 pcr->sd30_drive_sel_3v3 = DRIVER_TYPE_D; 248 pcr->aspm_en = ASPM_L1_EN; 249 + pcr->aspm_mode = ASPM_MODE_CFG; 250 pcr->tx_initial_phase = SET_CLOCK_PHASE(27, 27, 15); 251 pcr->rx_initial_phase = SET_CLOCK_PHASE(30, 6, 6); 252

drivers/misc/cardreader/rts5249.c

··· 566 pcr->sd30_drive_sel_1v8 = CFG_DRIVER_TYPE_B; 567 pcr->sd30_drive_sel_3v3 = CFG_DRIVER_TYPE_B; 568 pcr->aspm_en = ASPM_L1_EN; 569 pcr->tx_initial_phase = SET_CLOCK_PHASE(1, 29, 16); 570 pcr->rx_initial_phase = SET_CLOCK_PHASE(24, 6, 5); 571 ··· 730 void rts524a_init_params(struct rtsx_pcr *pcr) 731 { 732 rts5249_init_params(pcr); 733 pcr->tx_initial_phase = SET_CLOCK_PHASE(27, 29, 11); 734 pcr->option.ltr_l1off_sspwrgate = LTR_L1OFF_SSPWRGATE_5250_DEF; 735 pcr->option.ltr_l1off_snooze_sspwrgate = ··· 847 void rts525a_init_params(struct rtsx_pcr *pcr) 848 { 849 rts5249_init_params(pcr); 850 pcr->tx_initial_phase = SET_CLOCK_PHASE(25, 29, 11); 851 pcr->option.ltr_l1off_sspwrgate = LTR_L1OFF_SSPWRGATE_5250_DEF; 852 pcr->option.ltr_l1off_snooze_sspwrgate =

··· 566 pcr->sd30_drive_sel_1v8 = CFG_DRIVER_TYPE_B; 567 pcr->sd30_drive_sel_3v3 = CFG_DRIVER_TYPE_B; 568 pcr->aspm_en = ASPM_L1_EN; 569 + pcr->aspm_mode = ASPM_MODE_CFG; 570 pcr->tx_initial_phase = SET_CLOCK_PHASE(1, 29, 16); 571 pcr->rx_initial_phase = SET_CLOCK_PHASE(24, 6, 5); 572 ··· 729 void rts524a_init_params(struct rtsx_pcr *pcr) 730 { 731 rts5249_init_params(pcr); 732 + pcr->aspm_mode = ASPM_MODE_REG; 733 pcr->tx_initial_phase = SET_CLOCK_PHASE(27, 29, 11); 734 pcr->option.ltr_l1off_sspwrgate = LTR_L1OFF_SSPWRGATE_5250_DEF; 735 pcr->option.ltr_l1off_snooze_sspwrgate = ··· 845 void rts525a_init_params(struct rtsx_pcr *pcr) 846 { 847 rts5249_init_params(pcr); 848 + pcr->aspm_mode = ASPM_MODE_REG; 849 pcr->tx_initial_phase = SET_CLOCK_PHASE(25, 29, 11); 850 pcr->option.ltr_l1off_sspwrgate = LTR_L1OFF_SSPWRGATE_5250_DEF; 851 pcr->option.ltr_l1off_snooze_sspwrgate =

drivers/misc/cardreader/rts5260.c

··· 628 pcr->sd30_drive_sel_1v8 = CFG_DRIVER_TYPE_B; 629 pcr->sd30_drive_sel_3v3 = CFG_DRIVER_TYPE_B; 630 pcr->aspm_en = ASPM_L1_EN; 631 pcr->tx_initial_phase = SET_CLOCK_PHASE(27, 29, 11); 632 pcr->rx_initial_phase = SET_CLOCK_PHASE(24, 6, 5); 633

··· 628 pcr->sd30_drive_sel_1v8 = CFG_DRIVER_TYPE_B; 629 pcr->sd30_drive_sel_3v3 = CFG_DRIVER_TYPE_B; 630 pcr->aspm_en = ASPM_L1_EN; 631 + pcr->aspm_mode = ASPM_MODE_REG; 632 pcr->tx_initial_phase = SET_CLOCK_PHASE(27, 29, 11); 633 pcr->rx_initial_phase = SET_CLOCK_PHASE(24, 6, 5); 634

drivers/misc/cardreader/rts5261.c

··· 783 pcr->sd30_drive_sel_1v8 = 0x00; 784 pcr->sd30_drive_sel_3v3 = 0x00; 785 pcr->aspm_en = ASPM_L1_EN; 786 pcr->tx_initial_phase = SET_CLOCK_PHASE(27, 27, 11); 787 pcr->rx_initial_phase = SET_CLOCK_PHASE(24, 6, 5); 788

··· 783 pcr->sd30_drive_sel_1v8 = 0x00; 784 pcr->sd30_drive_sel_3v3 = 0x00; 785 pcr->aspm_en = ASPM_L1_EN; 786 + pcr->aspm_mode = ASPM_MODE_REG; 787 pcr->tx_initial_phase = SET_CLOCK_PHASE(27, 27, 11); 788 pcr->rx_initial_phase = SET_CLOCK_PHASE(24, 6, 5); 789

+31 -13

drivers/misc/cardreader/rtsx_pcr.c

··· 85 if (pcr->aspm_enabled == enable) 86 return; 87 88 - if (pcr->aspm_en & 0x02) 89 - rtsx_pci_write_register(pcr, ASPM_FORCE_CTL, FORCE_ASPM_CTL0 | 90 - FORCE_ASPM_CTL1, enable ? 0 : FORCE_ASPM_CTL0 | FORCE_ASPM_CTL1); 91 - else 92 - rtsx_pci_write_register(pcr, ASPM_FORCE_CTL, FORCE_ASPM_CTL0 | 93 - FORCE_ASPM_CTL1, FORCE_ASPM_CTL0 | FORCE_ASPM_CTL1); 94 95 if (!enable && (pcr->aspm_en & 0x02)) 96 mdelay(10); ··· 1400 return err; 1401 } 1402 1403 - rtsx_pci_write_register(pcr, ASPM_FORCE_CTL, 0x30, 0x30); 1404 1405 /* No CD interrupt if probing driver with card inserted. 1406 * So we need to initialize pcr->card_exist here. ··· 1417 static int rtsx_pci_init_chip(struct rtsx_pcr *pcr) 1418 { 1419 int err; 1420 1421 spin_lock_init(&pcr->lock); 1422 mutex_init(&pcr->pcr_mutex); ··· 1486 if (!pcr->slots) 1487 return -ENOMEM; 1488 1489 if (pcr->ops->fetch_vendor_settings) 1490 pcr->ops->fetch_vendor_settings(pcr); 1491 ··· 1530 struct pcr_handle *handle; 1531 u32 base, len; 1532 int ret, i, bar = 0; 1533 - u8 val; 1534 1535 dev_dbg(&(pcidev->dev), 1536 ": Realtek PCI-E Card Reader found at %s [%04x:%04x] (rev %x)\n", ··· 1595 pcr->host_cmds_addr = pcr->rtsx_resv_buf_addr; 1596 pcr->host_sg_tbl_ptr = pcr->rtsx_resv_buf + HOST_CMDS_BUF_LEN; 1597 pcr->host_sg_tbl_addr = pcr->rtsx_resv_buf_addr + HOST_CMDS_BUF_LEN; 1598 - rtsx_pci_read_register(pcr, ASPM_FORCE_CTL, &val); 1599 - if (val & FORCE_ASPM_CTL0 && val & FORCE_ASPM_CTL1) 1600 - pcr->aspm_enabled = false; 1601 - else 1602 - pcr->aspm_enabled = true; 1603 pcr->card_inserted = 0; 1604 pcr->card_removed = 0; 1605 INIT_DELAYED_WORK(&pcr->carddet_work, rtsx_pci_card_detect);

··· 85 if (pcr->aspm_enabled == enable) 86 return; 87 88 + if (pcr->aspm_mode == ASPM_MODE_CFG) { 89 + pcie_capability_clear_and_set_word(pcr->pci, PCI_EXP_LNKCTL, 90 + PCI_EXP_LNKCTL_ASPMC, 91 + enable ? pcr->aspm_en : 0); 92 + } else if (pcr->aspm_mode == ASPM_MODE_REG) { 93 + if (pcr->aspm_en & 0x02) 94 + rtsx_pci_write_register(pcr, ASPM_FORCE_CTL, FORCE_ASPM_CTL0 | 95 + FORCE_ASPM_CTL1, enable ? 0 : FORCE_ASPM_CTL0 | FORCE_ASPM_CTL1); 96 + else 97 + rtsx_pci_write_register(pcr, ASPM_FORCE_CTL, FORCE_ASPM_CTL0 | 98 + FORCE_ASPM_CTL1, FORCE_ASPM_CTL0 | FORCE_ASPM_CTL1); 99 + } 100 101 if (!enable && (pcr->aspm_en & 0x02)) 102 mdelay(10); ··· 1394 return err; 1395 } 1396 1397 + if (pcr->aspm_mode == ASPM_MODE_REG) 1398 + rtsx_pci_write_register(pcr, ASPM_FORCE_CTL, 0x30, 0x30); 1399 1400 /* No CD interrupt if probing driver with card inserted. 1401 * So we need to initialize pcr->card_exist here. ··· 1410 static int rtsx_pci_init_chip(struct rtsx_pcr *pcr) 1411 { 1412 int err; 1413 + u16 cfg_val; 1414 + u8 val; 1415 1416 spin_lock_init(&pcr->lock); 1417 mutex_init(&pcr->pcr_mutex); ··· 1477 if (!pcr->slots) 1478 return -ENOMEM; 1479 1480 + if (pcr->aspm_mode == ASPM_MODE_CFG) { 1481 + pcie_capability_read_word(pcr->pci, PCI_EXP_LNKCTL, &cfg_val); 1482 + if (cfg_val & PCI_EXP_LNKCTL_ASPM_L1) 1483 + pcr->aspm_enabled = true; 1484 + else 1485 + pcr->aspm_enabled = false; 1486 + 1487 + } else if (pcr->aspm_mode == ASPM_MODE_REG) { 1488 + rtsx_pci_read_register(pcr, ASPM_FORCE_CTL, &val); 1489 + if (val & FORCE_ASPM_CTL0 && val & FORCE_ASPM_CTL1) 1490 + pcr->aspm_enabled = false; 1491 + else 1492 + pcr->aspm_enabled = true; 1493 + } 1494 + 1495 if (pcr->ops->fetch_vendor_settings) 1496 pcr->ops->fetch_vendor_settings(pcr); 1497 ··· 1506 struct pcr_handle *handle; 1507 u32 base, len; 1508 int ret, i, bar = 0; 1509 1510 dev_dbg(&(pcidev->dev), 1511 ": Realtek PCI-E Card Reader found at %s [%04x:%04x] (rev %x)\n", ··· 1572 pcr->host_cmds_addr = pcr->rtsx_resv_buf_addr; 1573 pcr->host_sg_tbl_ptr = pcr->rtsx_resv_buf + HOST_CMDS_BUF_LEN; 1574 pcr->host_sg_tbl_addr = pcr->rtsx_resv_buf_addr + HOST_CMDS_BUF_LEN; 1575 pcr->card_inserted = 0; 1576 pcr->card_removed = 0; 1577 INIT_DELAYED_WORK(&pcr->carddet_work, rtsx_pci_card_detect);

+2 -2

drivers/phy/broadcom/phy-brcm-usb-init.h

··· 78 * Other architectures (e.g., ARM) either do not support big endian, or 79 * else leave I/O in little endian mode. 80 */ 81 - if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(__BIG_ENDIAN)) 82 return __raw_readl(addr); 83 else 84 return readl_relaxed(addr); ··· 87 static inline void brcm_usb_writel(u32 val, void __iomem *addr) 88 { 89 /* See brcmnand_readl() comments */ 90 - if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(__BIG_ENDIAN)) 91 __raw_writel(val, addr); 92 else 93 writel_relaxed(val, addr);

··· 78 * Other architectures (e.g., ARM) either do not support big endian, or 79 * else leave I/O in little endian mode. 80 */ 81 + if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN)) 82 return __raw_readl(addr); 83 else 84 return readl_relaxed(addr); ··· 87 static inline void brcm_usb_writel(u32 val, void __iomem *addr) 88 { 89 /* See brcmnand_readl() comments */ 90 + if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN)) 91 __raw_writel(val, addr); 92 else 93 writel_relaxed(val, addr);

drivers/phy/cadence/phy-cadence-sierra.c

··· 940 sp->nsubnodes = node; 941 942 if (sp->num_lanes > SIERRA_MAX_LANES) { 943 dev_err(dev, "Invalid lane configuration\n"); 944 goto put_child2; 945 }

··· 940 sp->nsubnodes = node; 941 942 if (sp->num_lanes > SIERRA_MAX_LANES) { 943 + ret = -EINVAL; 944 dev_err(dev, "Invalid lane configuration\n"); 945 goto put_child2; 946 }

drivers/phy/mediatek/phy-mtk-tphy.c

··· 949 break; 950 default: 951 dev_err(tphy->dev, "incompatible PHY type\n"); 952 return -EINVAL; 953 } 954

··· 949 break; 950 default: 951 dev_err(tphy->dev, "incompatible PHY type\n"); 952 + clk_disable_unprepare(instance->ref_clk); 953 + clk_disable_unprepare(instance->da_ref_clk); 954 return -EINVAL; 955 } 956

drivers/phy/microchip/sparx5_serdes.c

··· 2470 priv->coreclock = clock; 2471 2472 iores = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2473 iomem = devm_ioremap(priv->dev, iores->start, resource_size(iores)); 2474 if (IS_ERR(iomem)) { 2475 dev_err(priv->dev, "Unable to get serdes registers: %s\n",

··· 2470 priv->coreclock = clock; 2471 2472 iores = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2473 + if (!iores) { 2474 + dev_err(priv->dev, "Invalid resource\n"); 2475 + return -EINVAL; 2476 + } 2477 iomem = devm_ioremap(priv->dev, iores->start, resource_size(iores)); 2478 if (IS_ERR(iomem)) { 2479 dev_err(priv->dev, "Unable to get serdes registers: %s\n",

+1 -1

drivers/phy/ralink/phy-mt7621-pci.c

··· 341 .probe = mt7621_pci_phy_probe, 342 .driver = { 343 .name = "mt7621-pci-phy", 344 - .of_match_table = of_match_ptr(mt7621_pci_phy_ids), 345 }, 346 }; 347

··· 341 .probe = mt7621_pci_phy_probe, 342 .driver = { 343 .name = "mt7621-pci-phy", 344 + .of_match_table = mt7621_pci_phy_ids, 345 }, 346 }; 347

drivers/phy/ti/phy-j721e-wiz.c

··· 1212 1213 if (wiz->typec_dir_delay < WIZ_TYPEC_DIR_DEBOUNCE_MIN || 1214 wiz->typec_dir_delay > WIZ_TYPEC_DIR_DEBOUNCE_MAX) { 1215 dev_err(dev, "Invalid typec-dir-debounce property\n"); 1216 goto err_addr_to_resource; 1217 }

··· 1212 1213 if (wiz->typec_dir_delay < WIZ_TYPEC_DIR_DEBOUNCE_MIN || 1214 wiz->typec_dir_delay > WIZ_TYPEC_DIR_DEBOUNCE_MAX) { 1215 + ret = -EINVAL; 1216 dev_err(dev, "Invalid typec-dir-debounce property\n"); 1217 goto err_addr_to_resource; 1218 }

include/linux/rtsx_pci.h

··· 1109 }; 1110 1111 enum PDEV_STAT {PDEV_STAT_IDLE, PDEV_STAT_RUN}; 1112 1113 #define ASPM_L1_1_EN BIT(0) 1114 #define ASPM_L1_2_EN BIT(1) ··· 1235 u8 card_drive_sel; 1236 #define ASPM_L1_EN 0x02 1237 u8 aspm_en; 1238 bool aspm_enabled; 1239 1240 #define PCR_MS_PMOS (1 << 0)

··· 1109 }; 1110 1111 enum PDEV_STAT {PDEV_STAT_IDLE, PDEV_STAT_RUN}; 1112 + enum ASPM_MODE {ASPM_MODE_CFG, ASPM_MODE_REG}; 1113 1114 #define ASPM_L1_1_EN BIT(0) 1115 #define ASPM_L1_2_EN BIT(1) ··· 1234 u8 card_drive_sel; 1235 #define ASPM_L1_EN 0x02 1236 u8 aspm_en; 1237 + enum ASPM_MODE aspm_mode; 1238 bool aspm_enabled; 1239 1240 #define PCR_MS_PMOS (1 << 0)