tjh.dev / kernel
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drm/amd/powerplay: move clockgating to after ungating power in pp for uvd/vce

Cannot set clockgating state before ungating power.

Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
Reviewed-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

authored by

Tom St Denis and committed by
Alex Deucher 1ddeb625 09fc7eff

+7 -7
+7 -7
drivers/gpu/drm/amd/powerplay/hwmgr/cz_clockpowergating.c
··· 177 177 cz_dpm_powerdown_uvd(hwmgr); 178 178 } else { 179 179 cz_dpm_powerup_uvd(hwmgr); 180 - cgs_set_clockgating_state(hwmgr->device, 181 - AMD_IP_BLOCK_TYPE_UVD, 182 - AMD_PG_STATE_GATE); 183 180 cgs_set_powergating_state(hwmgr->device, 184 181 AMD_IP_BLOCK_TYPE_UVD, 185 182 AMD_CG_STATE_UNGATE); 183 + cgs_set_clockgating_state(hwmgr->device, 184 + AMD_IP_BLOCK_TYPE_UVD, 185 + AMD_PG_STATE_GATE); 186 186 cz_dpm_update_uvd_dpm(hwmgr, false); 187 187 } 188 188 ··· 211 211 } else { 212 212 cz_dpm_powerup_vce(hwmgr); 213 213 cz_hwmgr->vce_power_gated = false; 214 - cgs_set_clockgating_state( 215 - hwmgr->device, 216 - AMD_IP_BLOCK_TYPE_VCE, 217 - AMD_PG_STATE_GATE); 218 214 cgs_set_powergating_state( 219 215 hwmgr->device, 220 216 AMD_IP_BLOCK_TYPE_VCE, 221 217 AMD_CG_STATE_UNGATE); 218 + cgs_set_clockgating_state( 219 + hwmgr->device, 220 + AMD_IP_BLOCK_TYPE_VCE, 221 + AMD_PG_STATE_GATE); 222 222 cz_dpm_update_vce_dpm(hwmgr); 223 223 cz_enable_disable_vce_dpm(hwmgr, true); 224 224 return 0;