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Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
net: xpcs: rearrange register definitions
Place register number definitions immediately above their field
definitions and order by register number.
Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Link: https://patch.msgid.link/E1tjblS-00448F-8v@rmk-PC.armlinux.org.uk
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
authored by
Russell King (Oracle)
and committed by
Jakub Kicinski
1dd1bf50
0784d83d
+8
-17
+8
-17
drivers/net/pcs/pcs-xpcs.h
+8
-17
drivers/net/pcs/pcs-xpcs.h
···
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/* Clause 37 Defines */
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/* VR MII MMD registers offsets */
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#define DW_VR_MII_DIG_CTRL1 0x8000
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-
#define DW_VR_MII_AN_CTRL 0x8001
59
-
#define DW_VR_MII_AN_INTR_STS 0x8002
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-
/* EEE Mode Control Register */
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-
#define DW_VR_MII_EEE_MCTRL0 0x8006
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-
#define DW_VR_MII_EEE_MCTRL1 0x800b
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-
#define DW_VR_MII_DIG_CTRL2 0x80e1
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-
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-
/* VR_MII_DIG_CTRL1 */
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#define DW_VR_MII_DIG_CTRL1_MAC_AUTO_SW BIT(9)
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#define DW_VR_MII_DIG_CTRL1_2G5_EN BIT(2)
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#define DW_VR_MII_DIG_CTRL1_PHY_MODE_CTRL BIT(0)
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61
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-
/* VR_MII_DIG_CTRL2 */
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-
#define DW_VR_MII_DIG_CTRL2_TX_POL_INV BIT(4)
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-
#define DW_VR_MII_DIG_CTRL2_RX_POL_INV BIT(0)
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-
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-
/* VR_MII_AN_CTRL */
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+
#define DW_VR_MII_AN_CTRL 0x8001
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#define DW_VR_MII_AN_CTRL_8BIT BIT(8)
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#define DW_VR_MII_TX_CONFIG_MASK BIT(3)
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#define DW_VR_MII_TX_CONFIG_PHY_SIDE_SGMII 0x1
···
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#define DW_VR_MII_PCS_MODE_C37_SGMII 0x2
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#define DW_VR_MII_AN_INTR_EN BIT(0)
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-
/* VR_MII_AN_INTR_STS */
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+
#define DW_VR_MII_AN_INTR_STS 0x8002
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#define DW_VR_MII_AN_STS_C37_ANCMPLT_INTR BIT(0)
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#define DW_VR_MII_AN_STS_C37_ANSGM_FD BIT(1)
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#define DW_VR_MII_AN_STS_C37_ANSGM_SP GENMASK(3, 2)
···
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#define DW_VR_MII_C37_ANSGM_SP_1000 0x2
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#define DW_VR_MII_C37_ANSGM_SP_LNKSTS BIT(4)
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92
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-
/* VR MII EEE Control 0 defines */
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+
#define DW_VR_MII_EEE_MCTRL0 0x8006
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#define DW_VR_MII_EEE_LTX_EN BIT(0) /* LPI Tx Enable */
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#define DW_VR_MII_EEE_LRX_EN BIT(1) /* LPI Rx Enable */
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#define DW_VR_MII_EEE_TX_QUIET_EN BIT(2) /* Tx Quiet Enable */
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#define DW_VR_MII_EEE_RX_QUIET_EN BIT(3) /* Rx Quiet Enable */
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#define DW_VR_MII_EEE_TX_EN_CTRL BIT(4) /* Tx Control Enable */
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#define DW_VR_MII_EEE_RX_EN_CTRL BIT(7) /* Rx Control Enable */
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-
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100
#define DW_VR_MII_EEE_MULT_FACT_100NS GENMASK(11, 8)
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101
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-
/* VR MII EEE Control 1 defines */
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+
#define DW_VR_MII_EEE_MCTRL1 0x800b
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#define DW_VR_MII_EEE_TRN_LPI BIT(0) /* Transparent Mode Enable */
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+
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+
#define DW_VR_MII_DIG_CTRL2 0x80e1
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+
#define DW_VR_MII_DIG_CTRL2_TX_POL_INV BIT(4)
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+
#define DW_VR_MII_DIG_CTRL2_RX_POL_INV BIT(0)
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108
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#define DW_XPCS_INFO_DECLARE(_name, _pcs, _pma) \
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static const struct dw_xpcs_info _name = { .pcs = _pcs, .pma = _pma }