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dt-bindings: PCI: rockchip: Add DT bindings for Rockchip PCIe EP driver
This patch documents the DT bindings for the Rockchip PCIe controller
when configured in EP mode.
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Reviewed-by: Rob Herring <robh@kernel.org>
authored by
Shawn Lin
and committed by
Lorenzo Pieralisi
1dca7a63
cf590b07
+62
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Documentation/devicetree/bindings/pci/rockchip-pcie-ep.txt
+62
Documentation/devicetree/bindings/pci/rockchip-pcie-ep.txt
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* Rockchip AXI PCIe Endpoint Controller DT description
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Required properties:
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- compatible: Should contain "rockchip,rk3399-pcie-ep"
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- reg: Two register ranges as listed in the reg-names property
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- reg-names: Must include the following names
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- "apb-base"
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- "mem-base"
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- clocks: Must contain an entry for each entry in clock-names.
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See ../clocks/clock-bindings.txt for details.
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- clock-names: Must include the following entries:
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- "aclk"
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- "aclk-perf"
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- "hclk"
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- "pm"
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- resets: Must contain seven entries for each entry in reset-names.
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See ../reset/reset.txt for details.
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- reset-names: Must include the following names
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- "core"
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- "mgmt"
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- "mgmt-sticky"
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- "pipe"
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- "pm"
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- "aclk"
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- "pclk"
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- pinctrl-names : The pin control state names
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- pinctrl-0: The "default" pinctrl state
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- phys: Must contain an phandle to a PHY for each entry in phy-names.
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- phy-names: Must include 4 entries for all 4 lanes even if some of
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them won't be used for your cases. Entries are of the form "pcie-phy-N":
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where N ranges from 0 to 3.
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(see example below and you MUST also refer to ../phy/rockchip-pcie-phy.txt
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for changing the #phy-cells of phy node to support it)
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- rockchip,max-outbound-regions: Maximum number of outbound regions
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Optional Property:
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- num-lanes: number of lanes to use
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- max-functions: Maximum number of functions that can be configured (default 1).
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pcie0-ep: pcie@f8000000 {
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compatible = "rockchip,rk3399-pcie-ep";
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#address-cells = <3>;
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#size-cells = <2>;
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rockchip,max-outbound-regions = <16>;
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clocks = <&cru ACLK_PCIE>, <&cru ACLK_PERF_PCIE>,
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<&cru PCLK_PCIE>, <&cru SCLK_PCIE_PM>;
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clock-names = "aclk", "aclk-perf",
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"hclk", "pm";
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max-functions = /bits/ 8 <8>;
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num-lanes = <4>;
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reg = <0x0 0xfd000000 0x0 0x1000000>, <0x0 0x80000000 0x0 0x20000>;
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reg-names = "apb-base", "mem-base";
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resets = <&cru SRST_PCIE_CORE>, <&cru SRST_PCIE_MGMT>,
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<&cru SRST_PCIE_MGMT_STICKY>, <&cru SRST_PCIE_PIPE> ,
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<&cru SRST_PCIE_PM>, <&cru SRST_P_PCIE>, <&cru SRST_A_PCIE>;
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reset-names = "core", "mgmt", "mgmt-sticky", "pipe",
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"pm", "pclk", "aclk";
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phys = <&pcie_phy 0>, <&pcie_phy 1>, <&pcie_phy 2>, <&pcie_phy 3>;
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phy-names = "pcie-phy-0", "pcie-phy-1", "pcie-phy-2", "pcie-phy-3";
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pinctrl-names = "default";
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pinctrl-0 = <&pcie_clkreq>;
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};