Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux

regulator: axp20x-regulator: add support for AXP803

AXP803 PMIC also have a series of regulators (DCDCs and LDOs)
controllable via I2C/RSB bus.

Add support for them.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Acked-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Mark Brown <broonie@kernel.org>

authored by

Icenowy Zheng and committed by
Mark Brown
1dbe0ccb 2ea659a9

+169 -23
+132 -23
drivers/regulator/axp20x-regulator.c
··· 244 244 .ops = &axp20x_ops_sw, 245 245 }; 246 246 247 + static const struct regulator_linear_range axp803_dcdc234_ranges[] = { 248 + REGULATOR_LINEAR_RANGE(500000, 0x0, 0x46, 10000), 249 + REGULATOR_LINEAR_RANGE(1220000, 0x47, 0x4b, 20000), 250 + }; 251 + 252 + static const struct regulator_linear_range axp803_dcdc5_ranges[] = { 253 + REGULATOR_LINEAR_RANGE(800000, 0x0, 0x20, 10000), 254 + REGULATOR_LINEAR_RANGE(1140000, 0x21, 0x44, 20000), 255 + }; 256 + 257 + static const struct regulator_linear_range axp803_dcdc6_ranges[] = { 258 + REGULATOR_LINEAR_RANGE(600000, 0x0, 0x32, 10000), 259 + REGULATOR_LINEAR_RANGE(1120000, 0x33, 0x47, 20000), 260 + }; 261 + 262 + /* AXP806's CLDO2 and AXP809's DLDO1 shares the same range */ 263 + static const struct regulator_linear_range axp803_dldo2_ranges[] = { 264 + REGULATOR_LINEAR_RANGE(700000, 0x0, 0x1a, 100000), 265 + REGULATOR_LINEAR_RANGE(3400000, 0x1b, 0x1f, 200000), 266 + }; 267 + 268 + static const struct regulator_desc axp803_regulators[] = { 269 + AXP_DESC(AXP803, DCDC1, "dcdc1", "vin1", 1600, 3400, 100, 270 + AXP803_DCDC1_V_OUT, 0x1f, AXP22X_PWR_OUT_CTRL1, BIT(0)), 271 + AXP_DESC_RANGES(AXP803, DCDC2, "dcdc2", "vin2", axp803_dcdc234_ranges, 272 + 76, AXP803_DCDC2_V_OUT, 0x7f, AXP22X_PWR_OUT_CTRL1, 273 + BIT(1)), 274 + AXP_DESC_RANGES(AXP803, DCDC3, "dcdc3", "vin3", axp803_dcdc234_ranges, 275 + 76, AXP803_DCDC3_V_OUT, 0x7f, AXP22X_PWR_OUT_CTRL1, 276 + BIT(2)), 277 + AXP_DESC_RANGES(AXP803, DCDC4, "dcdc4", "vin4", axp803_dcdc234_ranges, 278 + 76, AXP803_DCDC4_V_OUT, 0x7f, AXP22X_PWR_OUT_CTRL1, 279 + BIT(3)), 280 + AXP_DESC_RANGES(AXP803, DCDC5, "dcdc5", "vin5", axp803_dcdc5_ranges, 281 + 68, AXP803_DCDC5_V_OUT, 0x7f, AXP22X_PWR_OUT_CTRL1, 282 + BIT(4)), 283 + AXP_DESC_RANGES(AXP803, DCDC6, "dcdc6", "vin6", axp803_dcdc6_ranges, 284 + 72, AXP803_DCDC6_V_OUT, 0x7f, AXP22X_PWR_OUT_CTRL1, 285 + BIT(5)), 286 + /* secondary switchable output of DCDC1 */ 287 + AXP_DESC_SW(AXP803, DC1SW, "dc1sw", NULL, AXP22X_PWR_OUT_CTRL2, 288 + BIT(7)), 289 + AXP_DESC(AXP803, ALDO1, "aldo1", "aldoin", 700, 3300, 100, 290 + AXP22X_ALDO1_V_OUT, 0x1f, AXP22X_PWR_OUT_CTRL3, BIT(5)), 291 + AXP_DESC(AXP803, ALDO2, "aldo2", "aldoin", 700, 3300, 100, 292 + AXP22X_ALDO2_V_OUT, 0x1f, AXP22X_PWR_OUT_CTRL3, BIT(6)), 293 + AXP_DESC(AXP803, ALDO3, "aldo3", "aldoin", 700, 3300, 100, 294 + AXP22X_ALDO3_V_OUT, 0x1f, AXP22X_PWR_OUT_CTRL3, BIT(7)), 295 + AXP_DESC(AXP803, DLDO1, "dldo1", "dldoin", 700, 3300, 100, 296 + AXP22X_DLDO1_V_OUT, 0x1f, AXP22X_PWR_OUT_CTRL2, BIT(3)), 297 + AXP_DESC_RANGES(AXP803, DLDO2, "dldo2", "dldoin", axp803_dldo2_ranges, 298 + 32, AXP22X_DLDO2_V_OUT, 0x1f, AXP22X_PWR_OUT_CTRL2, 299 + BIT(4)), 300 + AXP_DESC(AXP803, DLDO3, "dldo3", "dldoin", 700, 3300, 100, 301 + AXP22X_DLDO3_V_OUT, 0x1f, AXP22X_PWR_OUT_CTRL2, BIT(5)), 302 + AXP_DESC(AXP803, DLDO4, "dldo4", "dldoin", 700, 3300, 100, 303 + AXP22X_DLDO4_V_OUT, 0x1f, AXP22X_PWR_OUT_CTRL2, BIT(6)), 304 + AXP_DESC(AXP803, ELDO1, "eldo1", "eldoin", 700, 1900, 50, 305 + AXP22X_ELDO1_V_OUT, 0x1f, AXP22X_PWR_OUT_CTRL2, BIT(0)), 306 + AXP_DESC(AXP803, ELDO2, "eldo2", "eldoin", 700, 1900, 50, 307 + AXP22X_ELDO2_V_OUT, 0x1f, AXP22X_PWR_OUT_CTRL2, BIT(1)), 308 + AXP_DESC(AXP803, ELDO3, "eldo3", "eldoin", 700, 1900, 50, 309 + AXP22X_ELDO3_V_OUT, 0x1f, AXP22X_PWR_OUT_CTRL2, BIT(2)), 310 + AXP_DESC(AXP803, FLDO1, "fldo1", "fldoin", 700, 1450, 50, 311 + AXP803_FLDO1_V_OUT, 0x0f, AXP22X_PWR_OUT_CTRL3, BIT(2)), 312 + AXP_DESC(AXP803, FLDO2, "fldo2", "fldoin", 700, 1450, 50, 313 + AXP803_FLDO2_V_OUT, 0x0f, AXP22X_PWR_OUT_CTRL3, BIT(3)), 314 + AXP_DESC_IO(AXP803, LDO_IO0, "ldo-io0", "ips", 700, 3300, 100, 315 + AXP22X_LDO_IO0_V_OUT, 0x1f, AXP20X_GPIO0_CTRL, 0x07, 316 + AXP22X_IO_ENABLED, AXP22X_IO_DISABLED), 317 + AXP_DESC_IO(AXP803, LDO_IO1, "ldo-io1", "ips", 700, 3300, 100, 318 + AXP22X_LDO_IO1_V_OUT, 0x1f, AXP20X_GPIO1_CTRL, 0x07, 319 + AXP22X_IO_ENABLED, AXP22X_IO_DISABLED), 320 + AXP_DESC_FIXED(AXP803, RTC_LDO, "rtc-ldo", "ips", 3000), 321 + }; 322 + 247 323 static const struct regulator_linear_range axp806_dcdca_ranges[] = { 248 324 REGULATOR_LINEAR_RANGE(600000, 0x0, 0x32, 10000), 249 325 REGULATOR_LINEAR_RANGE(1120000, 0x33, 0x47, 20000), ··· 328 252 static const struct regulator_linear_range axp806_dcdcd_ranges[] = { 329 253 REGULATOR_LINEAR_RANGE(600000, 0x0, 0x2d, 20000), 330 254 REGULATOR_LINEAR_RANGE(1600000, 0x2e, 0x3f, 100000), 331 - }; 332 - 333 - static const struct regulator_linear_range axp806_cldo2_ranges[] = { 334 - REGULATOR_LINEAR_RANGE(700000, 0x0, 0x1a, 100000), 335 - REGULATOR_LINEAR_RANGE(3400000, 0x1b, 0x1f, 200000), 336 255 }; 337 256 338 257 static const struct regulator_desc axp806_regulators[] = { ··· 360 289 AXP806_BLDO4_V_CTRL, 0x0f, AXP806_PWR_OUT_CTRL2, BIT(3)), 361 290 AXP_DESC(AXP806, CLDO1, "cldo1", "cldoin", 700, 3300, 100, 362 291 AXP806_CLDO1_V_CTRL, 0x1f, AXP806_PWR_OUT_CTRL2, BIT(4)), 363 - AXP_DESC_RANGES(AXP806, CLDO2, "cldo2", "cldoin", axp806_cldo2_ranges, 292 + AXP_DESC_RANGES(AXP806, CLDO2, "cldo2", "cldoin", axp803_dldo2_ranges, 364 293 32, AXP806_CLDO2_V_CTRL, 0x1f, AXP806_PWR_OUT_CTRL2, 365 294 BIT(5)), 366 295 AXP_DESC(AXP806, CLDO3, "cldo3", "cldoin", 700, 3300, 100, ··· 397 326 AXP22X_ALDO2_V_OUT, 0x1f, AXP22X_PWR_OUT_CTRL1, BIT(7)), 398 327 AXP_DESC(AXP809, ALDO3, "aldo3", "aldoin", 700, 3300, 100, 399 328 AXP22X_ALDO3_V_OUT, 0x1f, AXP22X_PWR_OUT_CTRL2, BIT(5)), 400 - AXP_DESC_RANGES(AXP809, DLDO1, "dldo1", "dldoin", axp806_cldo2_ranges, 329 + AXP_DESC_RANGES(AXP809, DLDO1, "dldo1", "dldoin", axp803_dldo2_ranges, 401 330 32, AXP22X_DLDO1_V_OUT, 0x1f, AXP22X_PWR_OUT_CTRL2, 402 331 BIT(3)), 403 332 AXP_DESC(AXP809, DLDO2, "dldo2", "dldoin", 700, 3300, 100, ··· 440 369 def = 1500; 441 370 step = 75; 442 371 break; 443 - case AXP806_ID: 372 + case AXP803_ID: 444 373 /* 445 - * AXP806 DCDC work frequency setting has the same range and 374 + * AXP803 DCDC work frequency setting has the same range and 446 375 * step as AXP22X, but at a different register. 447 376 * Fall through to the check below. 448 377 * (See include/linux/mfd/axp20x.h) 449 378 */ 450 - reg = AXP806_DCDC_FREQ_CTRL; 379 + reg = AXP803_DCDC_FREQ_CTRL; 380 + case AXP806_ID: 381 + /* 382 + * AXP806 also have DCDC work frequency setting register at a 383 + * different position. 384 + */ 385 + if (axp20x->variant == AXP806_ID) 386 + reg = AXP806_DCDC_FREQ_CTRL; 451 387 case AXP221_ID: 452 388 case AXP223_ID: 453 389 case AXP809_ID: ··· 553 475 workmode <<= id - AXP22X_DCDC1; 554 476 break; 555 477 478 + case AXP803_ID: 479 + if (id < AXP803_DCDC1 || id > AXP803_DCDC6) 480 + return -EINVAL; 481 + 482 + mask = AXP22X_WORKMODE_DCDCX_MASK(id - AXP803_DCDC1); 483 + workmode <<= id - AXP803_DCDC1; 484 + break; 485 + 556 486 default: 557 487 /* should not happen */ 558 488 WARN_ON(1); ··· 578 492 { 579 493 u32 reg = 0; 580 494 581 - /* Only AXP806 has poly-phase outputs */ 582 - if (axp20x->variant != AXP806_ID) 495 + /* 496 + * Currently in our supported AXP variants, only AXP803 and AXP806 497 + * have polyphase regulators. 498 + */ 499 + switch (axp20x->variant) { 500 + case AXP803_ID: 501 + regmap_read(axp20x->regmap, AXP803_POLYPHASE_CTRL, &reg); 502 + 503 + switch (id) { 504 + case AXP803_DCDC3: 505 + return !!(reg & BIT(6)); 506 + case AXP803_DCDC6: 507 + return !!(reg & BIT(7)); 508 + } 509 + break; 510 + 511 + case AXP806_ID: 512 + regmap_read(axp20x->regmap, AXP806_DCDC_MODE_CTRL2, &reg); 513 + 514 + switch (id) { 515 + case AXP806_DCDCB: 516 + return (((reg & GENMASK(7, 6)) == BIT(6)) || 517 + ((reg & GENMASK(7, 6)) == BIT(7))); 518 + case AXP806_DCDCC: 519 + return ((reg & GENMASK(7, 6)) == BIT(7)); 520 + case AXP806_DCDCE: 521 + return !!(reg & BIT(5)); 522 + } 523 + break; 524 + 525 + default: 583 526 return false; 584 - 585 - regmap_read(axp20x->regmap, AXP806_DCDC_MODE_CTRL2, &reg); 586 - 587 - switch (id) { 588 - case AXP806_DCDCB: 589 - return (((reg & GENMASK(7, 6)) == BIT(6)) || 590 - ((reg & GENMASK(7, 6)) == BIT(7))); 591 - case AXP806_DCDCC: 592 - return ((reg & GENMASK(7, 6)) == BIT(7)); 593 - case AXP806_DCDCE: 594 - return !!(reg & BIT(5)); 595 527 } 596 528 597 529 return false; ··· 643 539 nregulators = AXP22X_REG_ID_MAX; 644 540 drivevbus = of_property_read_bool(pdev->dev.parent->of_node, 645 541 "x-powers,drive-vbus-en"); 542 + break; 543 + case AXP803_ID: 544 + regulators = axp803_regulators; 545 + nregulators = AXP803_REG_ID_MAX; 646 546 break; 647 547 case AXP806_ID: 648 548 regulators = axp806_regulators; ··· 687 579 * name. 688 580 */ 689 581 if ((regulators == axp22x_regulators && i == AXP22X_DC1SW) || 582 + (regulators == axp803_regulators && i == AXP803_DC1SW) || 690 583 (regulators == axp809_regulators && i == AXP809_DC1SW)) { 691 584 new_desc = devm_kzalloc(&pdev->dev, sizeof(*desc), 692 585 GFP_KERNEL);
+37
include/linux/mfd/axp20x.h
··· 119 119 #define AXP806_BUS_ADDR_EXT 0xfe 120 120 #define AXP806_REG_ADDR_EXT 0xff 121 121 122 + #define AXP803_POLYPHASE_CTRL 0x14 123 + #define AXP803_FLDO1_V_OUT 0x1c 124 + #define AXP803_FLDO2_V_OUT 0x1d 125 + #define AXP803_DCDC1_V_OUT 0x20 126 + #define AXP803_DCDC2_V_OUT 0x21 127 + #define AXP803_DCDC3_V_OUT 0x22 128 + #define AXP803_DCDC4_V_OUT 0x23 129 + #define AXP803_DCDC5_V_OUT 0x24 130 + #define AXP803_DCDC6_V_OUT 0x25 131 + #define AXP803_DCDC_FREQ_CTRL 0x3b 132 + 122 133 /* Interrupt */ 123 134 #define AXP152_IRQ1_EN 0x40 124 135 #define AXP152_IRQ2_EN 0x41 ··· 359 348 AXP809_LDO_IO1, 360 349 AXP809_SW, 361 350 AXP809_REG_ID_MAX, 351 + }; 352 + 353 + enum { 354 + AXP803_DCDC1 = 0, 355 + AXP803_DCDC2, 356 + AXP803_DCDC3, 357 + AXP803_DCDC4, 358 + AXP803_DCDC5, 359 + AXP803_DCDC6, 360 + AXP803_DC1SW, 361 + AXP803_ALDO1, 362 + AXP803_ALDO2, 363 + AXP803_ALDO3, 364 + AXP803_DLDO1, 365 + AXP803_DLDO2, 366 + AXP803_DLDO3, 367 + AXP803_DLDO4, 368 + AXP803_ELDO1, 369 + AXP803_ELDO2, 370 + AXP803_ELDO3, 371 + AXP803_FLDO1, 372 + AXP803_FLDO2, 373 + AXP803_RTC_LDO, 374 + AXP803_LDO_IO0, 375 + AXP803_LDO_IO1, 376 + AXP803_REG_ID_MAX, 362 377 }; 363 378 364 379 /* IRQs */