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kernel
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linux
net: ipa: add a parameter to aggregation registers
Starting with IPA v5.0, a single IPA instance can have more than 32
endpoints defined. To handle this, each register that holds a
bitmap of IPA endpoints is replicated as needed to represent the
available endpoints.
To prepare for this, registers that represent endpoint IDs in a bit
mask will be defined to have a parameter, with a stride value of 4
bytes. The first 32 endpoints are represented in the first 32-bit
register, then the next (up to) 32 endpoints at an offset 4 bytes
higher. When accessing such a register, the endpoint ID divided
by 32 determines the offset, and the endpoint ID modulo 32 defines
the endpoint's bit position within the register.
The first two registers we'll update for this are STATE_AGGR_ACTIVE
and AGGR_FORCE_CLOSE.
Until more than 32 endpoints are supported, this change has no
practical effect.
Signed-off-by: Alex Elder <elder@linaro.org>
Signed-off-by: David S. Miller <davem@davemloft.net>
authored by
Alex Elder
and committed by
David S. Miller
1d8f16db
6337b147
+22
-16
+10
-4
drivers/net/ipa/ipa_endpoint.c
+10
-4
drivers/net/ipa/ipa_endpoint.c
···
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static bool ipa_endpoint_aggr_active(struct ipa_endpoint *endpoint)
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{
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-
u32 mask = BIT(endpoint->endpoint_id);
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+
u32 endpoint_id = endpoint->endpoint_id;
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+
u32 mask = BIT(endpoint_id % 32);
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struct ipa *ipa = endpoint->ipa;
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+
u32 unit = endpoint_id / 32;
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const struct ipa_reg *reg;
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u32 val;
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+
/* This works until we actually have more than 32 endpoints */
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WARN_ON(!(mask & ipa->available));
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reg = ipa_reg(ipa, STATE_AGGR_ACTIVE);
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-
val = ioread32(ipa->reg_virt + ipa_reg_offset(reg));
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+
val = ioread32(ipa->reg_virt + ipa_reg_n_offset(reg, unit));
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return !!(val & mask);
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}
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static void ipa_endpoint_force_close(struct ipa_endpoint *endpoint)
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{
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-
u32 mask = BIT(endpoint->endpoint_id);
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+
u32 endpoint_id = endpoint->endpoint_id;
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+
u32 mask = BIT(endpoint_id % 32);
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struct ipa *ipa = endpoint->ipa;
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+
u32 unit = endpoint_id / 32;
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const struct ipa_reg *reg;
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+
/* This works until we actually have more than 32 endpoints */
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WARN_ON(!(mask & ipa->available));
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reg = ipa_reg(ipa, AGGR_FORCE_CLOSE);
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-
iowrite32(mask, ipa->reg_virt + ipa_reg_offset(reg));
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+
iowrite32(mask, ipa->reg_virt + ipa_reg_n_offset(reg, unit));
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}
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/**
+2
-2
drivers/net/ipa/reg/ipa_reg-v3.1.c
+2
-2
drivers/net/ipa/reg/ipa_reg-v3.1.c
···
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IPA_REG_FIELDS(FILT_ROUT_HASH_FLUSH, filt_rout_hash_flush, 0x0000090);
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/* Valid bits defined by ipa->available */
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-
IPA_REG(STATE_AGGR_ACTIVE, state_aggr_active, 0x0000010c);
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+
IPA_REG_STRIDE(STATE_AGGR_ACTIVE, state_aggr_active, 0x0000010c, 0x0004);
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IPA_REG(IPA_BCR, ipa_bcr, 0x000001d0);
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···
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IPA_REG_FIELDS(LOCAL_PKT_PROC_CNTXT, local_pkt_proc_cntxt, 0x000001e8);
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/* Valid bits defined by ipa->available */
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-
IPA_REG(AGGR_FORCE_CLOSE, aggr_force_close, 0x000001ec);
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+
IPA_REG_STRIDE(AGGR_FORCE_CLOSE, aggr_force_close, 0x000001ec, 0x0004);
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static const u32 ipa_reg_counter_cfg_fmask[] = {
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[EOT_COAL_GRANULARITY] = GENMASK(3, 0),
+2
-2
drivers/net/ipa/reg/ipa_reg-v3.5.1.c
+2
-2
drivers/net/ipa/reg/ipa_reg-v3.5.1.c
···
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IPA_REG_FIELDS(FILT_ROUT_HASH_FLUSH, filt_rout_hash_flush, 0x0000090);
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/* Valid bits defined by ipa->available */
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-
IPA_REG(STATE_AGGR_ACTIVE, state_aggr_active, 0x0000010c);
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+
IPA_REG_STRIDE(STATE_AGGR_ACTIVE, state_aggr_active, 0x0000010c, 0x0004);
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IPA_REG(IPA_BCR, ipa_bcr, 0x000001d0);
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···
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IPA_REG_FIELDS(LOCAL_PKT_PROC_CNTXT, local_pkt_proc_cntxt, 0x000001e8);
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/* Valid bits defined by ipa->available */
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-
IPA_REG(AGGR_FORCE_CLOSE, aggr_force_close, 0x000001ec);
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+
IPA_REG_STRIDE(AGGR_FORCE_CLOSE, aggr_force_close, 0x000001ec, 0x0004);
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static const u32 ipa_reg_counter_cfg_fmask[] = {
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/* Bits 0-3 reserved */
+2
-2
drivers/net/ipa/reg/ipa_reg-v4.11.c
+2
-2
drivers/net/ipa/reg/ipa_reg-v4.11.c
···
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IPA_REG_FIELDS(FILT_ROUT_HASH_FLUSH, filt_rout_hash_flush, 0x000014c);
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/* Valid bits defined by ipa->available */
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-
IPA_REG(STATE_AGGR_ACTIVE, state_aggr_active, 0x000000b4);
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+
IPA_REG_STRIDE(STATE_AGGR_ACTIVE, state_aggr_active, 0x000000b4, 0x0004);
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static const u32 ipa_reg_local_pkt_proc_cntxt_fmask[] = {
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[IPA_BASE_ADDR] = GENMASK(17, 0),
···
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IPA_REG_FIELDS(LOCAL_PKT_PROC_CNTXT, local_pkt_proc_cntxt, 0x000001e8);
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/* Valid bits defined by ipa->available */
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-
IPA_REG(AGGR_FORCE_CLOSE, aggr_force_close, 0x000001ec);
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+
IPA_REG_STRIDE(AGGR_FORCE_CLOSE, aggr_force_close, 0x000001ec, 0x0004);
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static const u32 ipa_reg_ipa_tx_cfg_fmask[] = {
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/* Bits 0-1 reserved */
+2
-2
drivers/net/ipa/reg/ipa_reg-v4.2.c
+2
-2
drivers/net/ipa/reg/ipa_reg-v4.2.c
···
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IPA_REG_FIELDS(FILT_ROUT_HASH_FLUSH, filt_rout_hash_flush, 0x000014c);
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/* Valid bits defined by ipa->available */
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-
IPA_REG(STATE_AGGR_ACTIVE, state_aggr_active, 0x000000b4);
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+
IPA_REG_STRIDE(STATE_AGGR_ACTIVE, state_aggr_active, 0x000000b4, 0x0004);
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IPA_REG(IPA_BCR, ipa_bcr, 0x000001d0);
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···
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IPA_REG_FIELDS(LOCAL_PKT_PROC_CNTXT, local_pkt_proc_cntxt, 0x000001e8);
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/* Valid bits defined by ipa->available */
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-
IPA_REG(AGGR_FORCE_CLOSE, aggr_force_close, 0x000001ec);
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+
IPA_REG_STRIDE(AGGR_FORCE_CLOSE, aggr_force_close, 0x000001ec, 0x0004);
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static const u32 ipa_reg_counter_cfg_fmask[] = {
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/* Bits 0-3 reserved */
+2
-2
drivers/net/ipa/reg/ipa_reg-v4.5.c
+2
-2
drivers/net/ipa/reg/ipa_reg-v4.5.c
···
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IPA_REG_FIELDS(FILT_ROUT_HASH_FLUSH, filt_rout_hash_flush, 0x000014c);
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/* Valid bits defined by ipa->available */
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-
IPA_REG(STATE_AGGR_ACTIVE, state_aggr_active, 0x000000b4);
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+
IPA_REG_STRIDE(STATE_AGGR_ACTIVE, state_aggr_active, 0x000000b4, 0x0004);
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static const u32 ipa_reg_local_pkt_proc_cntxt_fmask[] = {
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[IPA_BASE_ADDR] = GENMASK(17, 0),
···
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IPA_REG_FIELDS(LOCAL_PKT_PROC_CNTXT, local_pkt_proc_cntxt, 0x000001e8);
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/* Valid bits defined by ipa->available */
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-
IPA_REG(AGGR_FORCE_CLOSE, aggr_force_close, 0x000001ec);
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+
IPA_REG_STRIDE(AGGR_FORCE_CLOSE, aggr_force_close, 0x000001ec, 0x0004);
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static const u32 ipa_reg_ipa_tx_cfg_fmask[] = {
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/* Bits 0-1 reserved */
+2
-2
drivers/net/ipa/reg/ipa_reg-v4.9.c
+2
-2
drivers/net/ipa/reg/ipa_reg-v4.9.c
···
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IPA_REG_FIELDS(FILT_ROUT_HASH_FLUSH, filt_rout_hash_flush, 0x000014c);
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/* Valid bits defined by ipa->available */
142
-
IPA_REG(STATE_AGGR_ACTIVE, state_aggr_active, 0x000000b4);
142
+
IPA_REG_STRIDE(STATE_AGGR_ACTIVE, state_aggr_active, 0x000000b4, 0x0004);
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static const u32 ipa_reg_local_pkt_proc_cntxt_fmask[] = {
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[IPA_BASE_ADDR] = GENMASK(17, 0),
···
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IPA_REG_FIELDS(LOCAL_PKT_PROC_CNTXT, local_pkt_proc_cntxt, 0x000001e8);
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/* Valid bits defined by ipa->available */
153
-
IPA_REG(AGGR_FORCE_CLOSE, aggr_force_close, 0x000001ec);
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+
IPA_REG_STRIDE(AGGR_FORCE_CLOSE, aggr_force_close, 0x000001ec, 0x0004);
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static const u32 ipa_reg_ipa_tx_cfg_fmask[] = {
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/* Bits 0-1 reserved */