Merge branch 'mellanox/mlx5-next' into rdma.git for-next

+4

drivers/net/ethernet/mellanox/mlx5/core/cq.c

··· 109 109 cq->cons_index = 0; 110 110 cq->arm_sn = 0; 111 111 cq->eq = eq; 112 + cq->uid = MLX5_GET(create_cq_in, in, uid); 112 113 refcount_set(&cq->refcount, 1); 113 114 init_completion(&cq->free); 114 115 if (!cq->comp) ··· 145 144 memset(dout, 0, sizeof(dout)); 146 145 MLX5_SET(destroy_cq_in, din, opcode, MLX5_CMD_OP_DESTROY_CQ); 147 146 MLX5_SET(destroy_cq_in, din, cqn, cq->cqn); 147 + MLX5_SET(destroy_cq_in, din, uid, cq->uid); 148 148 mlx5_cmd_exec(dev, din, sizeof(din), dout, sizeof(dout)); 149 149 return err; 150 150 } ··· 167 165 168 166 MLX5_SET(destroy_cq_in, in, opcode, MLX5_CMD_OP_DESTROY_CQ); 169 167 MLX5_SET(destroy_cq_in, in, cqn, cq->cqn); 168 + MLX5_SET(destroy_cq_in, in, uid, cq->uid); 170 169 err = mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out)); 171 170 if (err) 172 171 return err; ··· 199 196 u32 out[MLX5_ST_SZ_DW(modify_cq_out)] = {0}; 200 197 201 198 MLX5_SET(modify_cq_in, in, opcode, MLX5_CMD_OP_MODIFY_CQ); 199 + MLX5_SET(modify_cq_in, in, uid, cq->uid); 202 200 return mlx5_cmd_exec(dev, in, inlen, out, sizeof(out)); 203 201 } 204 202 EXPORT_SYMBOL(mlx5_core_modify_cq);

+58 -21

drivers/net/ethernet/mellanox/mlx5/core/qp.c

··· 211 211 } 212 212 213 213 qp->qpn = MLX5_GET(create_dct_out, out, dctn); 214 + qp->uid = MLX5_GET(create_dct_in, in, uid); 214 215 err = create_resource_common(dev, qp, MLX5_RES_DCT); 215 216 if (err) 216 217 goto err_cmd; ··· 220 219 err_cmd: 221 220 MLX5_SET(destroy_dct_in, din, opcode, MLX5_CMD_OP_DESTROY_DCT); 222 221 MLX5_SET(destroy_dct_in, din, dctn, qp->qpn); 222 + MLX5_SET(destroy_dct_in, din, uid, qp->uid); 223 223 mlx5_cmd_exec(dev, (void *)&in, sizeof(din), 224 224 (void *)&out, sizeof(dout)); 225 225 return err; ··· 242 240 if (err) 243 241 return err; 244 242 243 + qp->uid = MLX5_GET(create_qp_in, in, uid); 245 244 qp->qpn = MLX5_GET(create_qp_out, out, qpn); 246 245 mlx5_core_dbg(dev, "qpn = 0x%x\n", qp->qpn); 247 246 ··· 264 261 memset(dout, 0, sizeof(dout)); 265 262 MLX5_SET(destroy_qp_in, din, opcode, MLX5_CMD_OP_DESTROY_QP); 266 263 MLX5_SET(destroy_qp_in, din, qpn, qp->qpn); 264 + MLX5_SET(destroy_qp_in, din, uid, qp->uid); 267 265 mlx5_cmd_exec(dev, din, sizeof(din), dout, sizeof(dout)); 268 266 return err; 269 267 } ··· 279 275 280 276 MLX5_SET(drain_dct_in, in, opcode, MLX5_CMD_OP_DRAIN_DCT); 281 277 MLX5_SET(drain_dct_in, in, dctn, qp->qpn); 278 + MLX5_SET(drain_dct_in, in, uid, qp->uid); 282 279 return mlx5_cmd_exec(dev, (void *)&in, sizeof(in), 283 280 (void *)&out, sizeof(out)); 284 281 } ··· 306 301 destroy_resource_common(dev, &dct->mqp); 307 302 MLX5_SET(destroy_dct_in, in, opcode, MLX5_CMD_OP_DESTROY_DCT); 308 303 MLX5_SET(destroy_dct_in, in, dctn, qp->qpn); 304 + MLX5_SET(destroy_dct_in, in, uid, qp->uid); 309 305 err = mlx5_cmd_exec(dev, (void *)&in, sizeof(in), 310 306 (void *)&out, sizeof(out)); 311 307 return err; ··· 326 320 327 321 MLX5_SET(destroy_qp_in, in, opcode, MLX5_CMD_OP_DESTROY_QP); 328 322 MLX5_SET(destroy_qp_in, in, qpn, qp->qpn); 323 + MLX5_SET(destroy_qp_in, in, uid, qp->uid); 329 324 err = mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out)); 330 325 if (err) 331 326 return err; ··· 380 373 381 374 static int modify_qp_mbox_alloc(struct mlx5_core_dev *dev, u16 opcode, int qpn, 382 375 u32 opt_param_mask, void *qpc, 383 - struct mbox_info *mbox) 376 + struct mbox_info *mbox, u16 uid) 384 377 { 385 378 mbox->out = NULL; 386 379 mbox->in = NULL; ··· 388 381 #define MBOX_ALLOC(mbox, typ) \ 389 382 mbox_alloc(mbox, MLX5_ST_SZ_BYTES(typ##_in), MLX5_ST_SZ_BYTES(typ##_out)) 390 383 391 - #define MOD_QP_IN_SET(typ, in, _opcode, _qpn) \ 392 - MLX5_SET(typ##_in, in, opcode, _opcode); \ 393 - MLX5_SET(typ##_in, in, qpn, _qpn) 384 + #define MOD_QP_IN_SET(typ, in, _opcode, _qpn, _uid) \ 385 + do { \ 386 + MLX5_SET(typ##_in, in, opcode, _opcode); \ 387 + MLX5_SET(typ##_in, in, qpn, _qpn); \ 388 + MLX5_SET(typ##_in, in, uid, _uid); \ 389 + } while (0) 394 390 395 - #define MOD_QP_IN_SET_QPC(typ, in, _opcode, _qpn, _opt_p, _qpc) \ 396 - MOD_QP_IN_SET(typ, in, _opcode, _qpn); \ 397 - MLX5_SET(typ##_in, in, opt_param_mask, _opt_p); \ 398 - memcpy(MLX5_ADDR_OF(typ##_in, in, qpc), _qpc, MLX5_ST_SZ_BYTES(qpc)) 391 + #define MOD_QP_IN_SET_QPC(typ, in, _opcode, _qpn, _opt_p, _qpc, _uid) \ 392 + do { \ 393 + MOD_QP_IN_SET(typ, in, _opcode, _qpn, _uid); \ 394 + MLX5_SET(typ##_in, in, opt_param_mask, _opt_p); \ 395 + memcpy(MLX5_ADDR_OF(typ##_in, in, qpc), _qpc, \ 396 + MLX5_ST_SZ_BYTES(qpc)); \ 397 + } while (0) 399 398 400 399 switch (opcode) { 401 400 /* 2RST & 2ERR */ 402 401 case MLX5_CMD_OP_2RST_QP: 403 402 if (MBOX_ALLOC(mbox, qp_2rst)) 404 403 return -ENOMEM; 405 - MOD_QP_IN_SET(qp_2rst, mbox->in, opcode, qpn); 404 + MOD_QP_IN_SET(qp_2rst, mbox->in, opcode, qpn, uid); 406 405 break; 407 406 case MLX5_CMD_OP_2ERR_QP: 408 407 if (MBOX_ALLOC(mbox, qp_2err)) 409 408 return -ENOMEM; 410 - MOD_QP_IN_SET(qp_2err, mbox->in, opcode, qpn); 409 + MOD_QP_IN_SET(qp_2err, mbox->in, opcode, qpn, uid); 411 410 break; 412 411 413 412 /* MODIFY with QPC */ ··· 421 408 if (MBOX_ALLOC(mbox, rst2init_qp)) 422 409 return -ENOMEM; 423 410 MOD_QP_IN_SET_QPC(rst2init_qp, mbox->in, opcode, qpn, 424 - opt_param_mask, qpc); 411 + opt_param_mask, qpc, uid); 425 412 break; 426 413 case MLX5_CMD_OP_INIT2RTR_QP: 427 414 if (MBOX_ALLOC(mbox, init2rtr_qp)) 428 415 return -ENOMEM; 429 416 MOD_QP_IN_SET_QPC(init2rtr_qp, mbox->in, opcode, qpn, 430 - opt_param_mask, qpc); 417 + opt_param_mask, qpc, uid); 431 418 break; 432 419 case MLX5_CMD_OP_RTR2RTS_QP: 433 420 if (MBOX_ALLOC(mbox, rtr2rts_qp)) 434 421 return -ENOMEM; 435 422 MOD_QP_IN_SET_QPC(rtr2rts_qp, mbox->in, opcode, qpn, 436 - opt_param_mask, qpc); 423 + opt_param_mask, qpc, uid); 437 424 break; 438 425 case MLX5_CMD_OP_RTS2RTS_QP: 439 426 if (MBOX_ALLOC(mbox, rts2rts_qp)) 440 427 return -ENOMEM; 441 428 MOD_QP_IN_SET_QPC(rts2rts_qp, mbox->in, opcode, qpn, 442 - opt_param_mask, qpc); 429 + opt_param_mask, qpc, uid); 443 430 break; 444 431 case MLX5_CMD_OP_SQERR2RTS_QP: 445 432 if (MBOX_ALLOC(mbox, sqerr2rts_qp)) 446 433 return -ENOMEM; 447 434 MOD_QP_IN_SET_QPC(sqerr2rts_qp, mbox->in, opcode, qpn, 448 - opt_param_mask, qpc); 435 + opt_param_mask, qpc, uid); 449 436 break; 450 437 case MLX5_CMD_OP_INIT2INIT_QP: 451 438 if (MBOX_ALLOC(mbox, init2init_qp)) 452 439 return -ENOMEM; 453 440 MOD_QP_IN_SET_QPC(init2init_qp, mbox->in, opcode, qpn, 454 - opt_param_mask, qpc); 441 + opt_param_mask, qpc, uid); 455 442 break; 456 443 default: 457 444 mlx5_core_err(dev, "Unknown transition for modify QP: OP(0x%x) QPN(0x%x)\n", ··· 469 456 int err; 470 457 471 458 err = modify_qp_mbox_alloc(dev, opcode, qp->qpn, 472 - opt_param_mask, qpc, &mbox); 459 + opt_param_mask, qpc, &mbox, qp->uid); 473 460 if (err) 474 461 return err; 475 462 ··· 544 531 } 545 532 EXPORT_SYMBOL_GPL(mlx5_core_xrcd_dealloc); 546 533 534 + static void destroy_rq_tracked(struct mlx5_core_dev *dev, u32 rqn, u16 uid) 535 + { 536 + u32 in[MLX5_ST_SZ_DW(destroy_rq_in)] = {}; 537 + u32 out[MLX5_ST_SZ_DW(destroy_rq_out)] = {}; 538 + 539 + MLX5_SET(destroy_rq_in, in, opcode, MLX5_CMD_OP_DESTROY_RQ); 540 + MLX5_SET(destroy_rq_in, in, rqn, rqn); 541 + MLX5_SET(destroy_rq_in, in, uid, uid); 542 + mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out)); 543 + } 544 + 547 545 int mlx5_core_create_rq_tracked(struct mlx5_core_dev *dev, u32 *in, int inlen, 548 546 struct mlx5_core_qp *rq) 549 547 { ··· 565 541 if (err) 566 542 return err; 567 543 544 + rq->uid = MLX5_GET(create_rq_in, in, uid); 568 545 rq->qpn = rqn; 569 546 err = create_resource_common(dev, rq, MLX5_RES_RQ); 570 547 if (err) ··· 574 549 return 0; 575 550 576 551 err_destroy_rq: 577 - mlx5_core_destroy_rq(dev, rq->qpn); 552 + destroy_rq_tracked(dev, rq->qpn, rq->uid); 578 553 579 554 return err; 580 555 } ··· 584 559 struct mlx5_core_qp *rq) 585 560 { 586 561 destroy_resource_common(dev, rq); 587 - mlx5_core_destroy_rq(dev, rq->qpn); 562 + destroy_rq_tracked(dev, rq->qpn, rq->uid); 588 563 } 589 564 EXPORT_SYMBOL(mlx5_core_destroy_rq_tracked); 565 + 566 + static void destroy_sq_tracked(struct mlx5_core_dev *dev, u32 sqn, u16 uid) 567 + { 568 + u32 in[MLX5_ST_SZ_DW(destroy_sq_in)] = {}; 569 + u32 out[MLX5_ST_SZ_DW(destroy_sq_out)] = {}; 570 + 571 + MLX5_SET(destroy_sq_in, in, opcode, MLX5_CMD_OP_DESTROY_SQ); 572 + MLX5_SET(destroy_sq_in, in, sqn, sqn); 573 + MLX5_SET(destroy_sq_in, in, uid, uid); 574 + mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out)); 575 + } 590 576 591 577 int mlx5_core_create_sq_tracked(struct mlx5_core_dev *dev, u32 *in, int inlen, 592 578 struct mlx5_core_qp *sq) ··· 609 573 if (err) 610 574 return err; 611 575 576 + sq->uid = MLX5_GET(create_sq_in, in, uid); 612 577 sq->qpn = sqn; 613 578 err = create_resource_common(dev, sq, MLX5_RES_SQ); 614 579 if (err) ··· 618 581 return 0; 619 582 620 583 err_destroy_sq: 621 - mlx5_core_destroy_sq(dev, sq->qpn); 584 + destroy_sq_tracked(dev, sq->qpn, sq->uid); 622 585 623 586 return err; 624 587 } ··· 628 591 struct mlx5_core_qp *sq) 629 592 { 630 593 destroy_resource_common(dev, sq); 631 - mlx5_core_destroy_sq(dev, sq->qpn); 594 + destroy_sq_tracked(dev, sq->qpn, sq->uid); 632 595 } 633 596 EXPORT_SYMBOL(mlx5_core_destroy_sq_tracked); 634 597

+27 -3

drivers/net/ethernet/mellanox/mlx5/core/srq.c

··· 166 166 if (!create_in) 167 167 return -ENOMEM; 168 168 169 + MLX5_SET(create_srq_in, create_in, uid, in->uid); 169 170 srqc = MLX5_ADDR_OF(create_srq_in, create_in, srq_context_entry); 170 171 pas = MLX5_ADDR_OF(create_srq_in, create_in, pas); 171 172 ··· 179 178 err = mlx5_cmd_exec(dev, create_in, inlen, create_out, 180 179 sizeof(create_out)); 181 180 kvfree(create_in); 182 - if (!err) 181 + if (!err) { 183 182 srq->srqn = MLX5_GET(create_srq_out, create_out, srqn); 183 + srq->uid = in->uid; 184 + } 184 185 185 186 return err; 186 187 } ··· 196 193 MLX5_SET(destroy_srq_in, srq_in, opcode, 197 194 MLX5_CMD_OP_DESTROY_SRQ); 198 195 MLX5_SET(destroy_srq_in, srq_in, srqn, srq->srqn); 196 + MLX5_SET(destroy_srq_in, srq_in, uid, srq->uid); 199 197 200 198 return mlx5_cmd_exec(dev, srq_in, sizeof(srq_in), 201 199 srq_out, sizeof(srq_out)); ··· 212 208 MLX5_SET(arm_rq_in, srq_in, op_mod, MLX5_ARM_RQ_IN_OP_MOD_SRQ); 213 209 MLX5_SET(arm_rq_in, srq_in, srq_number, srq->srqn); 214 210 MLX5_SET(arm_rq_in, srq_in, lwm, lwm); 211 + MLX5_SET(arm_rq_in, srq_in, uid, srq->uid); 215 212 216 213 return mlx5_cmd_exec(dev, srq_in, sizeof(srq_in), 217 214 srq_out, sizeof(srq_out)); ··· 265 260 if (!create_in) 266 261 return -ENOMEM; 267 262 263 + MLX5_SET(create_xrc_srq_in, create_in, uid, in->uid); 268 264 xrc_srqc = MLX5_ADDR_OF(create_xrc_srq_in, create_in, 269 265 xrc_srq_context_entry); 270 266 pas = MLX5_ADDR_OF(create_xrc_srq_in, create_in, pas); ··· 283 277 goto out; 284 278 285 279 srq->srqn = MLX5_GET(create_xrc_srq_out, create_out, xrc_srqn); 280 + srq->uid = in->uid; 286 281 out: 287 282 kvfree(create_in); 288 283 return err; ··· 298 291 MLX5_SET(destroy_xrc_srq_in, xrcsrq_in, opcode, 299 292 MLX5_CMD_OP_DESTROY_XRC_SRQ); 300 293 MLX5_SET(destroy_xrc_srq_in, xrcsrq_in, xrc_srqn, srq->srqn); 294 + MLX5_SET(destroy_xrc_srq_in, xrcsrq_in, uid, srq->uid); 301 295 302 296 return mlx5_cmd_exec(dev, xrcsrq_in, sizeof(xrcsrq_in), 303 297 xrcsrq_out, sizeof(xrcsrq_out)); ··· 314 306 MLX5_SET(arm_xrc_srq_in, xrcsrq_in, op_mod, MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ); 315 307 MLX5_SET(arm_xrc_srq_in, xrcsrq_in, xrc_srqn, srq->srqn); 316 308 MLX5_SET(arm_xrc_srq_in, xrcsrq_in, lwm, lwm); 309 + MLX5_SET(arm_xrc_srq_in, xrcsrq_in, uid, srq->uid); 317 310 318 311 return mlx5_cmd_exec(dev, xrcsrq_in, sizeof(xrcsrq_in), 319 312 xrcsrq_out, sizeof(xrcsrq_out)); ··· 374 365 wq = MLX5_ADDR_OF(rmpc, rmpc, wq); 375 366 376 367 MLX5_SET(rmpc, rmpc, state, MLX5_RMPC_STATE_RDY); 368 + MLX5_SET(create_rmp_in, create_in, uid, in->uid); 377 369 set_wq(wq, in); 378 370 memcpy(MLX5_ADDR_OF(rmpc, rmpc, wq.pas), in->pas, pas_size); 379 371 380 372 err = mlx5_core_create_rmp(dev, create_in, inlen, &srq->srqn); 373 + if (!err) 374 + srq->uid = in->uid; 381 375 382 376 kvfree(create_in); 383 377 return err; ··· 389 377 static int destroy_rmp_cmd(struct mlx5_core_dev *dev, 390 378 struct mlx5_core_srq *srq) 391 379 { 392 - return mlx5_core_destroy_rmp(dev, srq->srqn); 380 + u32 in[MLX5_ST_SZ_DW(destroy_rmp_in)] = {}; 381 + u32 out[MLX5_ST_SZ_DW(destroy_rmp_out)] = {}; 382 + 383 + MLX5_SET(destroy_rmp_in, in, opcode, MLX5_CMD_OP_DESTROY_RMP); 384 + MLX5_SET(destroy_rmp_in, in, rmpn, srq->srqn); 385 + MLX5_SET(destroy_rmp_in, in, uid, srq->uid); 386 + return mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out)); 393 387 } 394 388 395 389 static int arm_rmp_cmd(struct mlx5_core_dev *dev, ··· 418 400 419 401 MLX5_SET(modify_rmp_in, in, rmp_state, MLX5_RMPC_STATE_RDY); 420 402 MLX5_SET(modify_rmp_in, in, rmpn, srq->srqn); 403 + MLX5_SET(modify_rmp_in, in, uid, srq->uid); 421 404 MLX5_SET(wq, wq, lwm, lwm); 422 405 MLX5_SET(rmp_bitmask, bitmask, lwm, 1); 423 406 MLX5_SET(rmpc, rmpc, state, MLX5_RMPC_STATE_RDY); ··· 488 469 MLX5_SET(xrqc, xrqc, user_index, in->user_index); 489 470 MLX5_SET(xrqc, xrqc, cqn, in->cqn); 490 471 MLX5_SET(create_xrq_in, create_in, opcode, MLX5_CMD_OP_CREATE_XRQ); 472 + MLX5_SET(create_xrq_in, create_in, uid, in->uid); 491 473 err = mlx5_cmd_exec(dev, create_in, inlen, create_out, 492 474 sizeof(create_out)); 493 475 kvfree(create_in); 494 - if (!err) 476 + if (!err) { 495 477 srq->srqn = MLX5_GET(create_xrq_out, create_out, xrqn); 478 + srq->uid = in->uid; 479 + } 496 480 497 481 return err; 498 482 } ··· 507 485 508 486 MLX5_SET(destroy_xrq_in, in, opcode, MLX5_CMD_OP_DESTROY_XRQ); 509 487 MLX5_SET(destroy_xrq_in, in, xrqn, srq->srqn); 488 + MLX5_SET(destroy_xrq_in, in, uid, srq->uid); 510 489 511 490 return mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out)); 512 491 } ··· 523 500 MLX5_SET(arm_rq_in, in, op_mod, MLX5_ARM_RQ_IN_OP_MOD_XRQ); 524 501 MLX5_SET(arm_rq_in, in, srq_number, srq->srqn); 525 502 MLX5_SET(arm_rq_in, in, lwm, lwm); 503 + MLX5_SET(arm_rq_in, in, uid, srq->uid); 526 504 527 505 return mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out)); 528 506 }

+1

include/linux/mlx5/cq.h

··· 61 61 int reset_notify_added; 62 62 struct list_head reset_notify; 63 63 struct mlx5_eq *eq; 64 + u16 uid; 64 65 }; 65 66 66 67

+1

include/linux/mlx5/driver.h

··· 474 474 475 475 atomic_t refcount; 476 476 struct completion free; 477 + u16 uid; 477 478 }; 478 479 479 480 struct mlx5_eq_table {

+77 -58

include/linux/mlx5/mlx5_ifc.h

··· 1290 1290 u8 reserved_at_118[0x3]; 1291 1291 u8 log_wq_sz[0x5]; 1292 1292 1293 - u8 reserved_at_120[0x3]; 1293 + u8 dbr_umem_valid[0x1]; 1294 + u8 wq_umem_valid[0x1]; 1295 + u8 reserved_at_122[0x1]; 1294 1296 u8 log_hairpin_num_packets[0x5]; 1295 1297 u8 reserved_at_128[0x3]; 1296 1298 u8 log_hairpin_data_sz[0x5]; ··· 2366 2364 2367 2365 u8 dc_access_key[0x40]; 2368 2366 2369 - u8 reserved_at_680[0xc0]; 2367 + u8 reserved_at_680[0x3]; 2368 + u8 dbr_umem_valid[0x1]; 2369 + 2370 + u8 reserved_at_684[0xbc]; 2370 2371 }; 2371 2372 2372 2373 struct mlx5_ifc_roce_addr_layout_bits { ··· 2469 2464 2470 2465 u8 wq_signature[0x1]; 2471 2466 u8 cont_srq[0x1]; 2472 - u8 reserved_at_22[0x1]; 2467 + u8 dbr_umem_valid[0x1]; 2473 2468 u8 rlky[0x1]; 2474 2469 u8 basic_cyclic_rcv_wqe[0x1]; 2475 2470 u8 log_rq_stride[0x3]; ··· 3133 3128 3134 3129 struct mlx5_ifc_cqc_bits { 3135 3130 u8 status[0x4]; 3136 - u8 reserved_at_4[0x4]; 3131 + u8 reserved_at_4[0x2]; 3132 + u8 dbr_umem_valid[0x1]; 3133 + u8 reserved_at_7[0x1]; 3137 3134 u8 cqe_sz[0x3]; 3138 3135 u8 cc[0x1]; 3139 3136 u8 reserved_at_c[0x1]; ··· 3401 3394 3402 3395 struct mlx5_ifc_sqerr2rts_qp_in_bits { 3403 3396 u8 opcode[0x10]; 3404 - u8 reserved_at_10[0x10]; 3397 + u8 uid[0x10]; 3405 3398 3406 3399 u8 reserved_at_20[0x10]; 3407 3400 u8 op_mod[0x10]; ··· 3431 3424 3432 3425 struct mlx5_ifc_sqd2rts_qp_in_bits { 3433 3426 u8 opcode[0x10]; 3434 - u8 reserved_at_10[0x10]; 3427 + u8 uid[0x10]; 3435 3428 3436 3429 u8 reserved_at_20[0x10]; 3437 3430 u8 op_mod[0x10]; ··· 3636 3629 3637 3630 struct mlx5_ifc_rts2rts_qp_in_bits { 3638 3631 u8 opcode[0x10]; 3639 - u8 reserved_at_10[0x10]; 3632 + u8 uid[0x10]; 3640 3633 3641 3634 u8 reserved_at_20[0x10]; 3642 3635 u8 op_mod[0x10]; ··· 3666 3659 3667 3660 struct mlx5_ifc_rtr2rts_qp_in_bits { 3668 3661 u8 opcode[0x10]; 3669 - u8 reserved_at_10[0x10]; 3662 + u8 uid[0x10]; 3670 3663 3671 3664 u8 reserved_at_20[0x10]; 3672 3665 u8 op_mod[0x10]; ··· 3696 3689 3697 3690 struct mlx5_ifc_rst2init_qp_in_bits { 3698 3691 u8 opcode[0x10]; 3699 - u8 reserved_at_10[0x10]; 3692 + u8 uid[0x10]; 3700 3693 3701 3694 u8 reserved_at_20[0x10]; 3702 3695 u8 op_mod[0x10]; ··· 5199 5192 5200 5193 struct mlx5_ifc_qp_2rst_in_bits { 5201 5194 u8 opcode[0x10]; 5202 - u8 reserved_at_10[0x10]; 5195 + u8 uid[0x10]; 5203 5196 5204 5197 u8 reserved_at_20[0x10]; 5205 5198 u8 op_mod[0x10]; ··· 5221 5214 5222 5215 struct mlx5_ifc_qp_2err_in_bits { 5223 5216 u8 opcode[0x10]; 5224 - u8 reserved_at_10[0x10]; 5217 + u8 uid[0x10]; 5225 5218 5226 5219 u8 reserved_at_20[0x10]; 5227 5220 u8 op_mod[0x10]; ··· 5321 5314 5322 5315 struct mlx5_ifc_modify_tis_in_bits { 5323 5316 u8 opcode[0x10]; 5324 - u8 reserved_at_10[0x10]; 5317 + u8 uid[0x10]; 5325 5318 5326 5319 u8 reserved_at_20[0x10]; 5327 5320 u8 op_mod[0x10]; ··· 5360 5353 5361 5354 struct mlx5_ifc_modify_tir_in_bits { 5362 5355 u8 opcode[0x10]; 5363 - u8 reserved_at_10[0x10]; 5356 + u8 uid[0x10]; 5364 5357 5365 5358 u8 reserved_at_20[0x10]; 5366 5359 u8 op_mod[0x10]; ··· 5388 5381 5389 5382 struct mlx5_ifc_modify_sq_in_bits { 5390 5383 u8 opcode[0x10]; 5391 - u8 reserved_at_10[0x10]; 5384 + u8 uid[0x10]; 5392 5385 5393 5386 u8 reserved_at_20[0x10]; 5394 5387 u8 op_mod[0x10]; ··· 5461 5454 5462 5455 struct mlx5_ifc_modify_rqt_in_bits { 5463 5456 u8 opcode[0x10]; 5464 - u8 reserved_at_10[0x10]; 5457 + u8 uid[0x10]; 5465 5458 5466 5459 u8 reserved_at_20[0x10]; 5467 5460 u8 op_mod[0x10]; ··· 5495 5488 5496 5489 struct mlx5_ifc_modify_rq_in_bits { 5497 5490 u8 opcode[0x10]; 5498 - u8 reserved_at_10[0x10]; 5491 + u8 uid[0x10]; 5499 5492 5500 5493 u8 reserved_at_20[0x10]; 5501 5494 u8 op_mod[0x10]; ··· 5531 5524 5532 5525 struct mlx5_ifc_modify_rmp_in_bits { 5533 5526 u8 opcode[0x10]; 5534 - u8 reserved_at_10[0x10]; 5527 + u8 uid[0x10]; 5535 5528 5536 5529 u8 reserved_at_20[0x10]; 5537 5530 u8 op_mod[0x10]; ··· 5636 5629 5637 5630 struct mlx5_ifc_modify_cq_in_bits { 5638 5631 u8 opcode[0x10]; 5639 - u8 reserved_at_10[0x10]; 5632 + u8 uid[0x10]; 5640 5633 5641 5634 u8 reserved_at_20[0x10]; 5642 5635 u8 op_mod[0x10]; ··· 5648 5641 5649 5642 struct mlx5_ifc_cqc_bits cq_context; 5650 5643 5651 - u8 reserved_at_280[0x600]; 5644 + u8 reserved_at_280[0x40]; 5645 + 5646 + u8 cq_umem_valid[0x1]; 5647 + u8 reserved_at_2c1[0x5bf]; 5652 5648 5653 5649 u8 pas[0][0x40]; 5654 5650 }; ··· 5799 5789 5800 5790 struct mlx5_ifc_init2rtr_qp_in_bits { 5801 5791 u8 opcode[0x10]; 5802 - u8 reserved_at_10[0x10]; 5792 + u8 uid[0x10]; 5803 5793 5804 5794 u8 reserved_at_20[0x10]; 5805 5795 u8 op_mod[0x10]; ··· 5829 5819 5830 5820 struct mlx5_ifc_init2init_qp_in_bits { 5831 5821 u8 opcode[0x10]; 5832 - u8 reserved_at_10[0x10]; 5822 + u8 uid[0x10]; 5833 5823 5834 5824 u8 reserved_at_20[0x10]; 5835 5825 u8 op_mod[0x10]; ··· 5928 5918 5929 5919 struct mlx5_ifc_drain_dct_in_bits { 5930 5920 u8 opcode[0x10]; 5931 - u8 reserved_at_10[0x10]; 5921 + u8 uid[0x10]; 5932 5922 5933 5923 u8 reserved_at_20[0x10]; 5934 5924 u8 op_mod[0x10]; ··· 5972 5962 5973 5963 struct mlx5_ifc_detach_from_mcg_in_bits { 5974 5964 u8 opcode[0x10]; 5975 - u8 reserved_at_10[0x10]; 5965 + u8 uid[0x10]; 5976 5966 5977 5967 u8 reserved_at_20[0x10]; 5978 5968 u8 op_mod[0x10]; ··· 5996 5986 5997 5987 struct mlx5_ifc_destroy_xrq_in_bits { 5998 5988 u8 opcode[0x10]; 5999 - u8 reserved_at_10[0x10]; 5989 + u8 uid[0x10]; 6000 5990 6001 5991 u8 reserved_at_20[0x10]; 6002 5992 u8 op_mod[0x10]; ··· 6018 6008 6019 6009 struct mlx5_ifc_destroy_xrc_srq_in_bits { 6020 6010 u8 opcode[0x10]; 6021 - u8 reserved_at_10[0x10]; 6011 + u8 uid[0x10]; 6022 6012 6023 6013 u8 reserved_at_20[0x10]; 6024 6014 u8 op_mod[0x10]; ··· 6040 6030 6041 6031 struct mlx5_ifc_destroy_tis_in_bits { 6042 6032 u8 opcode[0x10]; 6043 - u8 reserved_at_10[0x10]; 6033 + u8 uid[0x10]; 6044 6034 6045 6035 u8 reserved_at_20[0x10]; 6046 6036 u8 op_mod[0x10]; ··· 6062 6052 6063 6053 struct mlx5_ifc_destroy_tir_in_bits { 6064 6054 u8 opcode[0x10]; 6065 - u8 reserved_at_10[0x10]; 6055 + u8 uid[0x10]; 6066 6056 6067 6057 u8 reserved_at_20[0x10]; 6068 6058 u8 op_mod[0x10]; ··· 6084 6074 6085 6075 struct mlx5_ifc_destroy_srq_in_bits { 6086 6076 u8 opcode[0x10]; 6087 - u8 reserved_at_10[0x10]; 6077 + u8 uid[0x10]; 6088 6078 6089 6079 u8 reserved_at_20[0x10]; 6090 6080 u8 op_mod[0x10]; ··· 6106 6096 6107 6097 struct mlx5_ifc_destroy_sq_in_bits { 6108 6098 u8 opcode[0x10]; 6109 - u8 reserved_at_10[0x10]; 6099 + u8 uid[0x10]; 6110 6100 6111 6101 u8 reserved_at_20[0x10]; 6112 6102 u8 op_mod[0x10]; ··· 6152 6142 6153 6143 struct mlx5_ifc_destroy_rqt_in_bits { 6154 6144 u8 opcode[0x10]; 6155 - u8 reserved_at_10[0x10]; 6145 + u8 uid[0x10]; 6156 6146 6157 6147 u8 reserved_at_20[0x10]; 6158 6148 u8 op_mod[0x10]; ··· 6174 6164 6175 6165 struct mlx5_ifc_destroy_rq_in_bits { 6176 6166 u8 opcode[0x10]; 6177 - u8 reserved_at_10[0x10]; 6167 + u8 uid[0x10]; 6178 6168 6179 6169 u8 reserved_at_20[0x10]; 6180 6170 u8 op_mod[0x10]; ··· 6218 6208 6219 6209 struct mlx5_ifc_destroy_rmp_in_bits { 6220 6210 u8 opcode[0x10]; 6221 - u8 reserved_at_10[0x10]; 6211 + u8 uid[0x10]; 6222 6212 6223 6213 u8 reserved_at_20[0x10]; 6224 6214 u8 op_mod[0x10]; ··· 6240 6230 6241 6231 struct mlx5_ifc_destroy_qp_in_bits { 6242 6232 u8 opcode[0x10]; 6243 - u8 reserved_at_10[0x10]; 6233 + u8 uid[0x10]; 6244 6234 6245 6235 u8 reserved_at_20[0x10]; 6246 6236 u8 op_mod[0x10]; ··· 6392 6382 6393 6383 struct mlx5_ifc_destroy_dct_in_bits { 6394 6384 u8 opcode[0x10]; 6395 - u8 reserved_at_10[0x10]; 6385 + u8 uid[0x10]; 6396 6386 6397 6387 u8 reserved_at_20[0x10]; 6398 6388 u8 op_mod[0x10]; ··· 6414 6404 6415 6405 struct mlx5_ifc_destroy_cq_in_bits { 6416 6406 u8 opcode[0x10]; 6417 - u8 reserved_at_10[0x10]; 6407 + u8 uid[0x10]; 6418 6408 6419 6409 u8 reserved_at_20[0x10]; 6420 6410 u8 op_mod[0x10]; ··· 6517 6507 6518 6508 struct mlx5_ifc_dealloc_xrcd_in_bits { 6519 6509 u8 opcode[0x10]; 6520 - u8 reserved_at_10[0x10]; 6510 + u8 uid[0x10]; 6521 6511 6522 6512 u8 reserved_at_20[0x10]; 6523 6513 u8 op_mod[0x10]; ··· 6605 6595 6606 6596 struct mlx5_ifc_dealloc_pd_in_bits { 6607 6597 u8 opcode[0x10]; 6608 - u8 reserved_at_10[0x10]; 6598 + u8 uid[0x10]; 6609 6599 6610 6600 u8 reserved_at_20[0x10]; 6611 6601 u8 op_mod[0x10]; ··· 6651 6641 6652 6642 struct mlx5_ifc_create_xrq_in_bits { 6653 6643 u8 opcode[0x10]; 6654 - u8 reserved_at_10[0x10]; 6644 + u8 uid[0x10]; 6655 6645 6656 6646 u8 reserved_at_20[0x10]; 6657 6647 u8 op_mod[0x10]; ··· 6675 6665 6676 6666 struct mlx5_ifc_create_xrc_srq_in_bits { 6677 6667 u8 opcode[0x10]; 6678 - u8 reserved_at_10[0x10]; 6668 + u8 uid[0x10]; 6679 6669 6680 6670 u8 reserved_at_20[0x10]; 6681 6671 u8 op_mod[0x10]; ··· 6684 6674 6685 6675 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry; 6686 6676 6687 - u8 reserved_at_280[0x600]; 6677 + u8 reserved_at_280[0x40]; 6678 + u8 xrc_srq_umem_valid[0x1]; 6679 + u8 reserved_at_2c1[0x5bf]; 6688 6680 6689 6681 u8 pas[0][0x40]; 6690 6682 }; ··· 6705 6693 6706 6694 struct mlx5_ifc_create_tis_in_bits { 6707 6695 u8 opcode[0x10]; 6708 - u8 reserved_at_10[0x10]; 6696 + u8 uid[0x10]; 6709 6697 6710 6698 u8 reserved_at_20[0x10]; 6711 6699 u8 op_mod[0x10]; ··· 6729 6717 6730 6718 struct mlx5_ifc_create_tir_in_bits { 6731 6719 u8 opcode[0x10]; 6732 - u8 reserved_at_10[0x10]; 6720 + u8 uid[0x10]; 6733 6721 6734 6722 u8 reserved_at_20[0x10]; 6735 6723 u8 op_mod[0x10]; ··· 6753 6741 6754 6742 struct mlx5_ifc_create_srq_in_bits { 6755 6743 u8 opcode[0x10]; 6756 - u8 reserved_at_10[0x10]; 6744 + u8 uid[0x10]; 6757 6745 6758 6746 u8 reserved_at_20[0x10]; 6759 6747 u8 op_mod[0x10]; ··· 6781 6769 6782 6770 struct mlx5_ifc_create_sq_in_bits { 6783 6771 u8 opcode[0x10]; 6784 - u8 reserved_at_10[0x10]; 6772 + u8 uid[0x10]; 6785 6773 6786 6774 u8 reserved_at_20[0x10]; 6787 6775 u8 op_mod[0x10]; ··· 6835 6823 6836 6824 struct mlx5_ifc_create_rqt_in_bits { 6837 6825 u8 opcode[0x10]; 6838 - u8 reserved_at_10[0x10]; 6826 + u8 uid[0x10]; 6839 6827 6840 6828 u8 reserved_at_20[0x10]; 6841 6829 u8 op_mod[0x10]; ··· 6859 6847 6860 6848 struct mlx5_ifc_create_rq_in_bits { 6861 6849 u8 opcode[0x10]; 6862 - u8 reserved_at_10[0x10]; 6850 + u8 uid[0x10]; 6863 6851 6864 6852 u8 reserved_at_20[0x10]; 6865 6853 u8 op_mod[0x10]; ··· 6883 6871 6884 6872 struct mlx5_ifc_create_rmp_in_bits { 6885 6873 u8 opcode[0x10]; 6886 - u8 reserved_at_10[0x10]; 6874 + u8 uid[0x10]; 6887 6875 6888 6876 u8 reserved_at_20[0x10]; 6889 6877 u8 op_mod[0x10]; ··· 6907 6895 6908 6896 struct mlx5_ifc_create_qp_in_bits { 6909 6897 u8 opcode[0x10]; 6910 - u8 reserved_at_10[0x10]; 6898 + u8 uid[0x10]; 6911 6899 6912 6900 u8 reserved_at_20[0x10]; 6913 6901 u8 op_mod[0x10]; ··· 6920 6908 6921 6909 struct mlx5_ifc_qpc_bits qpc; 6922 6910 6923 - u8 reserved_at_800[0x80]; 6911 + u8 reserved_at_800[0x60]; 6912 + 6913 + u8 wq_umem_valid[0x1]; 6914 + u8 reserved_at_861[0x1f]; 6924 6915 6925 6916 u8 pas[0][0x40]; 6926 6917 }; ··· 6985 6970 u8 reserved_at_40[0x20]; 6986 6971 6987 6972 u8 pg_access[0x1]; 6988 - u8 reserved_at_61[0x1f]; 6973 + u8 mkey_umem_valid[0x1]; 6974 + u8 reserved_at_62[0x1e]; 6989 6975 6990 6976 struct mlx5_ifc_mkc_bits memory_key_mkey_entry; 6991 6977 ··· 7154 7138 7155 7139 struct mlx5_ifc_create_dct_in_bits { 7156 7140 u8 opcode[0x10]; 7157 - u8 reserved_at_10[0x10]; 7141 + u8 uid[0x10]; 7158 7142 7159 7143 u8 reserved_at_20[0x10]; 7160 7144 u8 op_mod[0x10]; ··· 7180 7164 7181 7165 struct mlx5_ifc_create_cq_in_bits { 7182 7166 u8 opcode[0x10]; 7183 - u8 reserved_at_10[0x10]; 7167 + u8 uid[0x10]; 7184 7168 7185 7169 u8 reserved_at_20[0x10]; 7186 7170 u8 op_mod[0x10]; ··· 7189 7173 7190 7174 struct mlx5_ifc_cqc_bits cq_context; 7191 7175 7192 - u8 reserved_at_280[0x600]; 7176 + u8 reserved_at_280[0x60]; 7177 + 7178 + u8 cq_umem_valid[0x1]; 7179 + u8 reserved_at_2e1[0x59f]; 7193 7180 7194 7181 u8 pas[0][0x40]; 7195 7182 }; ··· 7240 7221 7241 7222 struct mlx5_ifc_attach_to_mcg_in_bits { 7242 7223 u8 opcode[0x10]; 7243 - u8 reserved_at_10[0x10]; 7224 + u8 uid[0x10]; 7244 7225 7245 7226 u8 reserved_at_20[0x10]; 7246 7227 u8 op_mod[0x10]; ··· 7291 7272 7292 7273 struct mlx5_ifc_arm_xrc_srq_in_bits { 7293 7274 u8 opcode[0x10]; 7294 - u8 reserved_at_10[0x10]; 7275 + u8 uid[0x10]; 7295 7276 7296 7277 u8 reserved_at_20[0x10]; 7297 7278 u8 op_mod[0x10]; ··· 7319 7300 7320 7301 struct mlx5_ifc_arm_rq_in_bits { 7321 7302 u8 opcode[0x10]; 7322 - u8 reserved_at_10[0x10]; 7303 + u8 uid[0x10]; 7323 7304 7324 7305 u8 reserved_at_20[0x10]; 7325 7306 u8 op_mod[0x10]; ··· 7367 7348 7368 7349 struct mlx5_ifc_alloc_xrcd_in_bits { 7369 7350 u8 opcode[0x10]; 7370 - u8 reserved_at_10[0x10]; 7351 + u8 uid[0x10]; 7371 7352 7372 7353 u8 reserved_at_20[0x10]; 7373 7354 u8 op_mod[0x10]; ··· 7455 7436 7456 7437 struct mlx5_ifc_alloc_pd_in_bits { 7457 7438 u8 opcode[0x10]; 7458 - u8 reserved_at_10[0x10]; 7439 + u8 uid[0x10]; 7459 7440 7460 7441 u8 reserved_at_20[0x10]; 7461 7442 u8 op_mod[0x10];

+1

include/linux/mlx5/qp.h

··· 471 471 int qpn; 472 472 struct mlx5_rsc_debug *dbg; 473 473 int pid; 474 + u16 uid; 474 475 }; 475 476 476 477 struct mlx5_core_dct {

+1

include/linux/mlx5/srq.h

··· 61 61 u32 tm_next_tag; 62 62 u32 tm_hw_phase_cnt; 63 63 u32 tm_sw_phase_cnt; 64 + u16 uid; 64 65 }; 65 66 66 67 struct mlx5_core_dev;