drm/tegra: hdmi: Register debugfs in ->late_register()

Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git

kernel os linux

The ->late_register() and ->early_unregister() callbacks are called at
the right time to make sure userspace only accesses interfaces when it
should. Move debugfs registration and unregistration to these callback
functions to avoid potential races with userspace.

Signed-off-by: Thierry Reding <treding@nvidia.com>

Thierry Reding 8 years ago 1d60047d a813d704

+245 -265

1 changed file

expand all

drivers

gpu

drm

tegra

hdmi.c

+245 -265

drivers/gpu/drm/tegra/hdmi.c

··· 79 79 bool dvi; 80 80 81 81 struct drm_info_list *debugfs_files; 82 - struct drm_minor *minor; 83 - struct dentry *debugfs; 84 82 }; 85 83 86 84 static inline struct tegra_hdmi * ··· 908 910 return status; 909 911 } 910 912 913 + #define DEBUGFS_REG32(_name) { .name = #_name, .offset = _name } 914 + 915 + static const struct debugfs_reg32 tegra_hdmi_regs[] = { 916 + DEBUGFS_REG32(HDMI_CTXSW), 917 + DEBUGFS_REG32(HDMI_NV_PDISP_SOR_STATE0), 918 + DEBUGFS_REG32(HDMI_NV_PDISP_SOR_STATE1), 919 + DEBUGFS_REG32(HDMI_NV_PDISP_SOR_STATE2), 920 + DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_AN_MSB), 921 + DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_AN_LSB), 922 + DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_CN_MSB), 923 + DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_CN_LSB), 924 + DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_AKSV_MSB), 925 + DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_AKSV_LSB), 926 + DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_BKSV_MSB), 927 + DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_BKSV_LSB), 928 + DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_CKSV_MSB), 929 + DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_CKSV_LSB), 930 + DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_DKSV_MSB), 931 + DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_DKSV_LSB), 932 + DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_CTRL), 933 + DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_CMODE), 934 + DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_MPRIME_MSB), 935 + DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_MPRIME_LSB), 936 + DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_SPRIME_MSB), 937 + DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_SPRIME_LSB2), 938 + DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_SPRIME_LSB1), 939 + DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_RI), 940 + DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_CS_MSB), 941 + DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_CS_LSB), 942 + DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AUDIO_EMU0), 943 + DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AUDIO_EMU_RDATA0), 944 + DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AUDIO_EMU1), 945 + DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AUDIO_EMU2), 946 + DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_CTRL), 947 + DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_STATUS), 948 + DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_HEADER), 949 + DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_SUBPACK0_LOW), 950 + DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_SUBPACK0_HIGH), 951 + DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_CTRL), 952 + DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_STATUS), 953 + DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_HEADER), 954 + DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK0_LOW), 955 + DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH), 956 + DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK1_LOW), 957 + DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH), 958 + DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GENERIC_CTRL), 959 + DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GENERIC_STATUS), 960 + DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GENERIC_HEADER), 961 + DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK0_LOW), 962 + DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK0_HIGH), 963 + DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK1_LOW), 964 + DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK1_HIGH), 965 + DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK2_LOW), 966 + DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK2_HIGH), 967 + DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK3_LOW), 968 + DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK3_HIGH), 969 + DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_CTRL), 970 + DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_0320_SUBPACK_LOW), 971 + DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_0320_SUBPACK_HIGH), 972 + DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_0441_SUBPACK_LOW), 973 + DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_0441_SUBPACK_HIGH), 974 + DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_0882_SUBPACK_LOW), 975 + DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_0882_SUBPACK_HIGH), 976 + DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_1764_SUBPACK_LOW), 977 + DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_1764_SUBPACK_HIGH), 978 + DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_0480_SUBPACK_LOW), 979 + DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_0480_SUBPACK_HIGH), 980 + DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_0960_SUBPACK_LOW), 981 + DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_0960_SUBPACK_HIGH), 982 + DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_1920_SUBPACK_LOW), 983 + DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_1920_SUBPACK_HIGH), 984 + DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_CTRL), 985 + DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_VSYNC_KEEPOUT), 986 + DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_VSYNC_WINDOW), 987 + DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GCP_CTRL), 988 + DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GCP_STATUS), 989 + DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GCP_SUBPACK), 990 + DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_CHANNEL_STATUS1), 991 + DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_CHANNEL_STATUS2), 992 + DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_EMU0), 993 + DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_EMU1), 994 + DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_EMU1_RDATA), 995 + DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_SPARE), 996 + DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_SPDIF_CHN_STATUS1), 997 + DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_SPDIF_CHN_STATUS2), 998 + DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_HDCPRIF_ROM_CTRL), 999 + DEBUGFS_REG32(HDMI_NV_PDISP_SOR_CAP), 1000 + DEBUGFS_REG32(HDMI_NV_PDISP_SOR_PWR), 1001 + DEBUGFS_REG32(HDMI_NV_PDISP_SOR_TEST), 1002 + DEBUGFS_REG32(HDMI_NV_PDISP_SOR_PLL0), 1003 + DEBUGFS_REG32(HDMI_NV_PDISP_SOR_PLL1), 1004 + DEBUGFS_REG32(HDMI_NV_PDISP_SOR_PLL2), 1005 + DEBUGFS_REG32(HDMI_NV_PDISP_SOR_CSTM), 1006 + DEBUGFS_REG32(HDMI_NV_PDISP_SOR_LVDS), 1007 + DEBUGFS_REG32(HDMI_NV_PDISP_SOR_CRCA), 1008 + DEBUGFS_REG32(HDMI_NV_PDISP_SOR_CRCB), 1009 + DEBUGFS_REG32(HDMI_NV_PDISP_SOR_BLANK), 1010 + DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_CTL), 1011 + DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(0)), 1012 + DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(1)), 1013 + DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(2)), 1014 + DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(3)), 1015 + DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(4)), 1016 + DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(5)), 1017 + DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(6)), 1018 + DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(7)), 1019 + DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(8)), 1020 + DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(9)), 1021 + DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(10)), 1022 + DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(11)), 1023 + DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(12)), 1024 + DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(13)), 1025 + DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(14)), 1026 + DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(15)), 1027 + DEBUGFS_REG32(HDMI_NV_PDISP_SOR_VCRCA0), 1028 + DEBUGFS_REG32(HDMI_NV_PDISP_SOR_VCRCA1), 1029 + DEBUGFS_REG32(HDMI_NV_PDISP_SOR_CCRCA0), 1030 + DEBUGFS_REG32(HDMI_NV_PDISP_SOR_CCRCA1), 1031 + DEBUGFS_REG32(HDMI_NV_PDISP_SOR_EDATAA0), 1032 + DEBUGFS_REG32(HDMI_NV_PDISP_SOR_EDATAA1), 1033 + DEBUGFS_REG32(HDMI_NV_PDISP_SOR_COUNTA0), 1034 + DEBUGFS_REG32(HDMI_NV_PDISP_SOR_COUNTA1), 1035 + DEBUGFS_REG32(HDMI_NV_PDISP_SOR_DEBUGA0), 1036 + DEBUGFS_REG32(HDMI_NV_PDISP_SOR_DEBUGA1), 1037 + DEBUGFS_REG32(HDMI_NV_PDISP_SOR_TRIG), 1038 + DEBUGFS_REG32(HDMI_NV_PDISP_SOR_MSCHECK), 1039 + DEBUGFS_REG32(HDMI_NV_PDISP_SOR_LANE_DRIVE_CURRENT), 1040 + DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_DEBUG0), 1041 + DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_DEBUG1), 1042 + DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_DEBUG2), 1043 + DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_FS(0)), 1044 + DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_FS(1)), 1045 + DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_FS(2)), 1046 + DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_FS(3)), 1047 + DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_FS(4)), 1048 + DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_FS(5)), 1049 + DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_FS(6)), 1050 + DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_PULSE_WIDTH), 1051 + DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_THRESHOLD), 1052 + DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_CNTRL0), 1053 + DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_N), 1054 + DEBUGFS_REG32(HDMI_NV_PDISP_HDCPRIF_ROM_TIMING), 1055 + DEBUGFS_REG32(HDMI_NV_PDISP_SOR_REFCLK), 1056 + DEBUGFS_REG32(HDMI_NV_PDISP_CRC_CONTROL), 1057 + DEBUGFS_REG32(HDMI_NV_PDISP_INPUT_CONTROL), 1058 + DEBUGFS_REG32(HDMI_NV_PDISP_SCRATCH), 1059 + DEBUGFS_REG32(HDMI_NV_PDISP_PE_CURRENT), 1060 + DEBUGFS_REG32(HDMI_NV_PDISP_KEY_CTRL), 1061 + DEBUGFS_REG32(HDMI_NV_PDISP_KEY_DEBUG0), 1062 + DEBUGFS_REG32(HDMI_NV_PDISP_KEY_DEBUG1), 1063 + DEBUGFS_REG32(HDMI_NV_PDISP_KEY_DEBUG2), 1064 + DEBUGFS_REG32(HDMI_NV_PDISP_KEY_HDCP_KEY_0), 1065 + DEBUGFS_REG32(HDMI_NV_PDISP_KEY_HDCP_KEY_1), 1066 + DEBUGFS_REG32(HDMI_NV_PDISP_KEY_HDCP_KEY_2), 1067 + DEBUGFS_REG32(HDMI_NV_PDISP_KEY_HDCP_KEY_3), 1068 + DEBUGFS_REG32(HDMI_NV_PDISP_KEY_HDCP_KEY_TRIG), 1069 + DEBUGFS_REG32(HDMI_NV_PDISP_KEY_SKEY_INDEX), 1070 + DEBUGFS_REG32(HDMI_NV_PDISP_SOR_AUDIO_CNTRL0), 1071 + DEBUGFS_REG32(HDMI_NV_PDISP_SOR_AUDIO_SPARE0), 1072 + DEBUGFS_REG32(HDMI_NV_PDISP_SOR_AUDIO_HDA_CODEC_SCRATCH0), 1073 + DEBUGFS_REG32(HDMI_NV_PDISP_SOR_AUDIO_HDA_CODEC_SCRATCH1), 1074 + DEBUGFS_REG32(HDMI_NV_PDISP_SOR_AUDIO_HDA_ELD_BUFWR), 1075 + DEBUGFS_REG32(HDMI_NV_PDISP_SOR_AUDIO_HDA_PRESENSE), 1076 + DEBUGFS_REG32(HDMI_NV_PDISP_INT_STATUS), 1077 + DEBUGFS_REG32(HDMI_NV_PDISP_INT_MASK), 1078 + DEBUGFS_REG32(HDMI_NV_PDISP_INT_ENABLE), 1079 + DEBUGFS_REG32(HDMI_NV_PDISP_SOR_IO_PEAK_CURRENT), 1080 + }; 1081 + 1082 + static int tegra_hdmi_show_regs(struct seq_file *s, void *data) 1083 + { 1084 + struct drm_info_node *node = s->private; 1085 + struct tegra_hdmi *hdmi = node->info_ent->data; 1086 + struct drm_crtc *crtc = hdmi->output.encoder.crtc; 1087 + struct drm_device *drm = node->minor->dev; 1088 + unsigned int i; 1089 + int err = 0; 1090 + 1091 + drm_modeset_lock_all(drm); 1092 + 1093 + if (!crtc || !crtc->state->active) { 1094 + err = -EBUSY; 1095 + goto unlock; 1096 + } 1097 + 1098 + for (i = 0; i < ARRAY_SIZE(tegra_hdmi_regs); i++) { 1099 + unsigned int offset = tegra_hdmi_regs[i].offset; 1100 + 1101 + seq_printf(s, "%-56s %#05x %08x\n", tegra_hdmi_regs[i].name, 1102 + offset, tegra_hdmi_readl(hdmi, offset)); 1103 + } 1104 + 1105 + unlock: 1106 + drm_modeset_unlock_all(drm); 1107 + return err; 1108 + } 1109 + 1110 + static struct drm_info_list debugfs_files[] = { 1111 + { "regs", tegra_hdmi_show_regs, 0, NULL }, 1112 + }; 1113 + 1114 + static int tegra_hdmi_late_register(struct drm_connector *connector) 1115 + { 1116 + struct tegra_output *output = connector_to_output(connector); 1117 + unsigned int i, count = ARRAY_SIZE(debugfs_files); 1118 + struct drm_minor *minor = connector->dev->primary; 1119 + struct dentry *root = connector->debugfs_entry; 1120 + struct tegra_hdmi *hdmi = to_hdmi(output); 1121 + int err; 1122 + 1123 + hdmi->debugfs_files = kmemdup(debugfs_files, sizeof(debugfs_files), 1124 + GFP_KERNEL); 1125 + if (!hdmi->debugfs_files) 1126 + return -ENOMEM; 1127 + 1128 + for (i = 0; i < count; i++) 1129 + hdmi->debugfs_files[i].data = hdmi; 1130 + 1131 + err = drm_debugfs_create_files(hdmi->debugfs_files, count, root, minor); 1132 + if (err < 0) 1133 + goto free; 1134 + 1135 + return 0; 1136 + 1137 + free: 1138 + kfree(hdmi->debugfs_files); 1139 + hdmi->debugfs_files = NULL; 1140 + 1141 + return err; 1142 + } 1143 + 1144 + static void tegra_hdmi_early_unregister(struct drm_connector *connector) 1145 + { 1146 + struct tegra_output *output = connector_to_output(connector); 1147 + struct drm_minor *minor = connector->dev->primary; 1148 + unsigned int count = ARRAY_SIZE(debugfs_files); 1149 + struct tegra_hdmi *hdmi = to_hdmi(output); 1150 + 1151 + drm_debugfs_remove_files(hdmi->debugfs_files, count, minor); 1152 + kfree(hdmi->debugfs_files); 1153 + hdmi->debugfs_files = NULL; 1154 + } 1155 + 911 1156 static const struct drm_connector_funcs tegra_hdmi_connector_funcs = { 912 1157 .reset = drm_atomic_helper_connector_reset, 913 1158 .detect = tegra_hdmi_connector_detect, ··· 1158 917 .destroy = tegra_output_connector_destroy, 1159 918 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, 1160 919 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 920 + .late_register = tegra_hdmi_late_register, 921 + .early_unregister = tegra_hdmi_early_unregister, 1161 922 }; 1162 923 1163 924 static enum drm_mode_status ··· 1468 1225 .atomic_check = tegra_hdmi_encoder_atomic_check, 1469 1226 }; 1470 1227 1471 - #define DEBUGFS_REG32(_name) { .name = #_name, .offset = _name } 1472 - 1473 - static const struct debugfs_reg32 tegra_hdmi_regs[] = { 1474 - DEBUGFS_REG32(HDMI_CTXSW), 1475 - DEBUGFS_REG32(HDMI_NV_PDISP_SOR_STATE0), 1476 - DEBUGFS_REG32(HDMI_NV_PDISP_SOR_STATE1), 1477 - DEBUGFS_REG32(HDMI_NV_PDISP_SOR_STATE2), 1478 - DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_AN_MSB), 1479 - DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_AN_LSB), 1480 - DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_CN_MSB), 1481 - DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_CN_LSB), 1482 - DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_AKSV_MSB), 1483 - DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_AKSV_LSB), 1484 - DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_BKSV_MSB), 1485 - DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_BKSV_LSB), 1486 - DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_CKSV_MSB), 1487 - DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_CKSV_LSB), 1488 - DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_DKSV_MSB), 1489 - DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_DKSV_LSB), 1490 - DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_CTRL), 1491 - DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_CMODE), 1492 - DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_MPRIME_MSB), 1493 - DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_MPRIME_LSB), 1494 - DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_SPRIME_MSB), 1495 - DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_SPRIME_LSB2), 1496 - DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_SPRIME_LSB1), 1497 - DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_RI), 1498 - DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_CS_MSB), 1499 - DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_CS_LSB), 1500 - DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AUDIO_EMU0), 1501 - DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AUDIO_EMU_RDATA0), 1502 - DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AUDIO_EMU1), 1503 - DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AUDIO_EMU2), 1504 - DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_CTRL), 1505 - DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_STATUS), 1506 - DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_HEADER), 1507 - DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_SUBPACK0_LOW), 1508 - DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_SUBPACK0_HIGH), 1509 - DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_CTRL), 1510 - DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_STATUS), 1511 - DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_HEADER), 1512 - DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK0_LOW), 1513 - DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH), 1514 - DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK1_LOW), 1515 - DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH), 1516 - DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GENERIC_CTRL), 1517 - DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GENERIC_STATUS), 1518 - DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GENERIC_HEADER), 1519 - DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK0_LOW), 1520 - DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK0_HIGH), 1521 - DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK1_LOW), 1522 - DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK1_HIGH), 1523 - DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK2_LOW), 1524 - DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK2_HIGH), 1525 - DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK3_LOW), 1526 - DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK3_HIGH), 1527 - DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_CTRL), 1528 - DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_0320_SUBPACK_LOW), 1529 - DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_0320_SUBPACK_HIGH), 1530 - DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_0441_SUBPACK_LOW), 1531 - DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_0441_SUBPACK_HIGH), 1532 - DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_0882_SUBPACK_LOW), 1533 - DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_0882_SUBPACK_HIGH), 1534 - DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_1764_SUBPACK_LOW), 1535 - DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_1764_SUBPACK_HIGH), 1536 - DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_0480_SUBPACK_LOW), 1537 - DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_0480_SUBPACK_HIGH), 1538 - DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_0960_SUBPACK_LOW), 1539 - DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_0960_SUBPACK_HIGH), 1540 - DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_1920_SUBPACK_LOW), 1541 - DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_1920_SUBPACK_HIGH), 1542 - DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_CTRL), 1543 - DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_VSYNC_KEEPOUT), 1544 - DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_VSYNC_WINDOW), 1545 - DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GCP_CTRL), 1546 - DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GCP_STATUS), 1547 - DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GCP_SUBPACK), 1548 - DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_CHANNEL_STATUS1), 1549 - DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_CHANNEL_STATUS2), 1550 - DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_EMU0), 1551 - DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_EMU1), 1552 - DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_EMU1_RDATA), 1553 - DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_SPARE), 1554 - DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_SPDIF_CHN_STATUS1), 1555 - DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_SPDIF_CHN_STATUS2), 1556 - DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_HDCPRIF_ROM_CTRL), 1557 - DEBUGFS_REG32(HDMI_NV_PDISP_SOR_CAP), 1558 - DEBUGFS_REG32(HDMI_NV_PDISP_SOR_PWR), 1559 - DEBUGFS_REG32(HDMI_NV_PDISP_SOR_TEST), 1560 - DEBUGFS_REG32(HDMI_NV_PDISP_SOR_PLL0), 1561 - DEBUGFS_REG32(HDMI_NV_PDISP_SOR_PLL1), 1562 - DEBUGFS_REG32(HDMI_NV_PDISP_SOR_PLL2), 1563 - DEBUGFS_REG32(HDMI_NV_PDISP_SOR_CSTM), 1564 - DEBUGFS_REG32(HDMI_NV_PDISP_SOR_LVDS), 1565 - DEBUGFS_REG32(HDMI_NV_PDISP_SOR_CRCA), 1566 - DEBUGFS_REG32(HDMI_NV_PDISP_SOR_CRCB), 1567 - DEBUGFS_REG32(HDMI_NV_PDISP_SOR_BLANK), 1568 - DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_CTL), 1569 - DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(0)), 1570 - DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(1)), 1571 - DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(2)), 1572 - DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(3)), 1573 - DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(4)), 1574 - DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(5)), 1575 - DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(6)), 1576 - DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(7)), 1577 - DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(8)), 1578 - DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(9)), 1579 - DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(10)), 1580 - DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(11)), 1581 - DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(12)), 1582 - DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(13)), 1583 - DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(14)), 1584 - DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(15)), 1585 - DEBUGFS_REG32(HDMI_NV_PDISP_SOR_VCRCA0), 1586 - DEBUGFS_REG32(HDMI_NV_PDISP_SOR_VCRCA1), 1587 - DEBUGFS_REG32(HDMI_NV_PDISP_SOR_CCRCA0), 1588 - DEBUGFS_REG32(HDMI_NV_PDISP_SOR_CCRCA1), 1589 - DEBUGFS_REG32(HDMI_NV_PDISP_SOR_EDATAA0), 1590 - DEBUGFS_REG32(HDMI_NV_PDISP_SOR_EDATAA1), 1591 - DEBUGFS_REG32(HDMI_NV_PDISP_SOR_COUNTA0), 1592 - DEBUGFS_REG32(HDMI_NV_PDISP_SOR_COUNTA1), 1593 - DEBUGFS_REG32(HDMI_NV_PDISP_SOR_DEBUGA0), 1594 - DEBUGFS_REG32(HDMI_NV_PDISP_SOR_DEBUGA1), 1595 - DEBUGFS_REG32(HDMI_NV_PDISP_SOR_TRIG), 1596 - DEBUGFS_REG32(HDMI_NV_PDISP_SOR_MSCHECK), 1597 - DEBUGFS_REG32(HDMI_NV_PDISP_SOR_LANE_DRIVE_CURRENT), 1598 - DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_DEBUG0), 1599 - DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_DEBUG1), 1600 - DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_DEBUG2), 1601 - DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_FS(0)), 1602 - DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_FS(1)), 1603 - DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_FS(2)), 1604 - DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_FS(3)), 1605 - DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_FS(4)), 1606 - DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_FS(5)), 1607 - DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_FS(6)), 1608 - DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_PULSE_WIDTH), 1609 - DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_THRESHOLD), 1610 - DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_CNTRL0), 1611 - DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_N), 1612 - DEBUGFS_REG32(HDMI_NV_PDISP_HDCPRIF_ROM_TIMING), 1613 - DEBUGFS_REG32(HDMI_NV_PDISP_SOR_REFCLK), 1614 - DEBUGFS_REG32(HDMI_NV_PDISP_CRC_CONTROL), 1615 - DEBUGFS_REG32(HDMI_NV_PDISP_INPUT_CONTROL), 1616 - DEBUGFS_REG32(HDMI_NV_PDISP_SCRATCH), 1617 - DEBUGFS_REG32(HDMI_NV_PDISP_PE_CURRENT), 1618 - DEBUGFS_REG32(HDMI_NV_PDISP_KEY_CTRL), 1619 - DEBUGFS_REG32(HDMI_NV_PDISP_KEY_DEBUG0), 1620 - DEBUGFS_REG32(HDMI_NV_PDISP_KEY_DEBUG1), 1621 - DEBUGFS_REG32(HDMI_NV_PDISP_KEY_DEBUG2), 1622 - DEBUGFS_REG32(HDMI_NV_PDISP_KEY_HDCP_KEY_0), 1623 - DEBUGFS_REG32(HDMI_NV_PDISP_KEY_HDCP_KEY_1), 1624 - DEBUGFS_REG32(HDMI_NV_PDISP_KEY_HDCP_KEY_2), 1625 - DEBUGFS_REG32(HDMI_NV_PDISP_KEY_HDCP_KEY_3), 1626 - DEBUGFS_REG32(HDMI_NV_PDISP_KEY_HDCP_KEY_TRIG), 1627 - DEBUGFS_REG32(HDMI_NV_PDISP_KEY_SKEY_INDEX), 1628 - DEBUGFS_REG32(HDMI_NV_PDISP_SOR_AUDIO_CNTRL0), 1629 - DEBUGFS_REG32(HDMI_NV_PDISP_SOR_AUDIO_SPARE0), 1630 - DEBUGFS_REG32(HDMI_NV_PDISP_SOR_AUDIO_HDA_CODEC_SCRATCH0), 1631 - DEBUGFS_REG32(HDMI_NV_PDISP_SOR_AUDIO_HDA_CODEC_SCRATCH1), 1632 - DEBUGFS_REG32(HDMI_NV_PDISP_SOR_AUDIO_HDA_ELD_BUFWR), 1633 - DEBUGFS_REG32(HDMI_NV_PDISP_SOR_AUDIO_HDA_PRESENSE), 1634 - DEBUGFS_REG32(HDMI_NV_PDISP_INT_STATUS), 1635 - DEBUGFS_REG32(HDMI_NV_PDISP_INT_MASK), 1636 - DEBUGFS_REG32(HDMI_NV_PDISP_INT_ENABLE), 1637 - DEBUGFS_REG32(HDMI_NV_PDISP_SOR_IO_PEAK_CURRENT), 1638 - }; 1639 - 1640 - static int tegra_hdmi_show_regs(struct seq_file *s, void *data) 1641 - { 1642 - struct drm_info_node *node = s->private; 1643 - struct tegra_hdmi *hdmi = node->info_ent->data; 1644 - struct drm_crtc *crtc = hdmi->output.encoder.crtc; 1645 - struct drm_device *drm = node->minor->dev; 1646 - unsigned int i; 1647 - int err = 0; 1648 - 1649 - drm_modeset_lock_all(drm); 1650 - 1651 - if (!crtc || !crtc->state->active) { 1652 - err = -EBUSY; 1653 - goto unlock; 1654 - } 1655 - 1656 - for (i = 0; i < ARRAY_SIZE(tegra_hdmi_regs); i++) { 1657 - unsigned int offset = tegra_hdmi_regs[i].offset; 1658 - 1659 - seq_printf(s, "%-56s %#05x %08x\n", tegra_hdmi_regs[i].name, 1660 - offset, tegra_hdmi_readl(hdmi, offset)); 1661 - } 1662 - 1663 - unlock: 1664 - drm_modeset_unlock_all(drm); 1665 - return err; 1666 - } 1667 - 1668 - static struct drm_info_list debugfs_files[] = { 1669 - { "regs", tegra_hdmi_show_regs, 0, NULL }, 1670 - }; 1671 - 1672 - static int tegra_hdmi_debugfs_init(struct tegra_hdmi *hdmi, 1673 - struct drm_minor *minor) 1674 - { 1675 - unsigned int i; 1676 - int err; 1677 - 1678 - hdmi->debugfs = debugfs_create_dir("hdmi", minor->debugfs_root); 1679 - if (!hdmi->debugfs) 1680 - return -ENOMEM; 1681 - 1682 - hdmi->debugfs_files = kmemdup(debugfs_files, sizeof(debugfs_files), 1683 - GFP_KERNEL); 1684 - if (!hdmi->debugfs_files) { 1685 - err = -ENOMEM; 1686 - goto remove; 1687 - } 1688 - 1689 - for (i = 0; i < ARRAY_SIZE(debugfs_files); i++) 1690 - hdmi->debugfs_files[i].data = hdmi; 1691 - 1692 - err = drm_debugfs_create_files(hdmi->debugfs_files, 1693 - ARRAY_SIZE(debugfs_files), 1694 - hdmi->debugfs, minor); 1695 - if (err < 0) 1696 - goto free; 1697 - 1698 - hdmi->minor = minor; 1699 - 1700 - return 0; 1701 - 1702 - free: 1703 - kfree(hdmi->debugfs_files); 1704 - hdmi->debugfs_files = NULL; 1705 - remove: 1706 - debugfs_remove(hdmi->debugfs); 1707 - hdmi->debugfs = NULL; 1708 - 1709 - return err; 1710 - } 1711 - 1712 - static void tegra_hdmi_debugfs_exit(struct tegra_hdmi *hdmi) 1713 - { 1714 - drm_debugfs_remove_files(hdmi->debugfs_files, ARRAY_SIZE(debugfs_files), 1715 - hdmi->minor); 1716 - hdmi->minor = NULL; 1717 - 1718 - kfree(hdmi->debugfs_files); 1719 - hdmi->debugfs_files = NULL; 1720 - 1721 - debugfs_remove(hdmi->debugfs); 1722 - hdmi->debugfs = NULL; 1723 - } 1724 - 1725 1228 static int tegra_hdmi_init(struct host1x_client *client) 1726 1229 { 1727 1230 struct drm_device *drm = dev_get_drvdata(client->parent); ··· 1500 1511 1501 1512 hdmi->output.encoder.possible_crtcs = 0x3; 1502 1513 1503 - if (IS_ENABLED(CONFIG_DEBUG_FS)) { 1504 - err = tegra_hdmi_debugfs_init(hdmi, drm->primary); 1505 - if (err < 0) 1506 - dev_err(client->dev, "debugfs setup failed: %d\n", err); 1507 - } 1508 - 1509 1514 err = regulator_enable(hdmi->hdmi); 1510 1515 if (err < 0) { 1511 1516 dev_err(client->dev, "failed to enable HDMI regulator: %d\n", ··· 1531 1548 regulator_disable(hdmi->vdd); 1532 1549 regulator_disable(hdmi->pll); 1533 1550 regulator_disable(hdmi->hdmi); 1534 - 1535 - if (IS_ENABLED(CONFIG_DEBUG_FS)) 1536 - tegra_hdmi_debugfs_exit(hdmi); 1537 1551 1538 1552 return 0; 1539 1553 }