Merge tag 'imx-drm-next-2015-03-31' of git://git.pengutronix.de/git/pza/linux into drm-next

+425 -1

Documentation/DocBook/media/v4l/subdev-formats.xml

··· 91 91 <listitem><para>For formats where the total number of bits per pixel is smaller 92 92 than the number of bus samples per pixel times the bus width, a padding 93 93 value stating if the bytes are padded in their most high order bits 94 - (PADHI) or low order bits (PADLO).</para></listitem> 94 + (PADHI) or low order bits (PADLO). A "C" prefix is used for component-wise 95 + padding in the most high order bits (CPADHI) or low order bits (CPADLO) 96 + of each separate component.</para></listitem> 95 97 <listitem><para>For formats where the number of bus samples per pixel is larger 96 98 than 1, an endianness value stating if the pixel is transferred MSB first 97 99 (BE) or LSB first (LE).</para></listitem> ··· 194 192 </row> 195 193 </thead> 196 194 <tbody valign="top"> 195 + <row id="MEDIA-BUS-FMT-RGB444-1X12"> 196 + <entry>MEDIA_BUS_FMT_RGB444_1X12</entry> 197 + <entry>0x100e</entry> 198 + <entry></entry> 199 + &dash-ent-20; 200 + <entry>r<subscript>3</subscript></entry> 201 + <entry>r<subscript>2</subscript></entry> 202 + <entry>r<subscript>1</subscript></entry> 203 + <entry>r<subscript>0</subscript></entry> 204 + <entry>g<subscript>3</subscript></entry> 205 + <entry>g<subscript>2</subscript></entry> 206 + <entry>g<subscript>1</subscript></entry> 207 + <entry>g<subscript>0</subscript></entry> 208 + <entry>b<subscript>3</subscript></entry> 209 + <entry>b<subscript>2</subscript></entry> 210 + <entry>b<subscript>1</subscript></entry> 211 + <entry>b<subscript>0</subscript></entry> 212 + </row> 197 213 <row id="MEDIA-BUS-FMT-RGB444-2X8-PADHI-BE"> 198 214 <entry>MEDIA_BUS_FMT_RGB444_2X8_PADHI_BE</entry> 199 215 <entry>0x1001</entry> ··· 323 303 <entry>r<subscript>0</subscript></entry> 324 304 <entry>g<subscript>4</subscript></entry> 325 305 <entry>g<subscript>3</subscript></entry> 306 + </row> 307 + <row id="MEDIA-BUS-FMT-RGB565-1X16"> 308 + <entry>MEDIA_BUS_FMT_RGB565_1X16</entry> 309 + <entry>0x100f</entry> 310 + <entry></entry> 311 + &dash-ent-16; 312 + <entry>r<subscript>4</subscript></entry> 313 + <entry>r<subscript>3</subscript></entry> 314 + <entry>r<subscript>2</subscript></entry> 315 + <entry>r<subscript>1</subscript></entry> 316 + <entry>r<subscript>0</subscript></entry> 317 + <entry>g<subscript>5</subscript></entry> 318 + <entry>g<subscript>4</subscript></entry> 319 + <entry>g<subscript>3</subscript></entry> 320 + <entry>g<subscript>2</subscript></entry> 321 + <entry>g<subscript>1</subscript></entry> 322 + <entry>g<subscript>0</subscript></entry> 323 + <entry>b<subscript>4</subscript></entry> 324 + <entry>b<subscript>3</subscript></entry> 325 + <entry>b<subscript>2</subscript></entry> 326 + <entry>b<subscript>1</subscript></entry> 327 + <entry>b<subscript>0</subscript></entry> 326 328 </row> 327 329 <row id="MEDIA-BUS-FMT-BGR565-2X8-BE"> 328 330 <entry>MEDIA_BUS_FMT_BGR565_2X8_BE</entry> ··· 481 439 <entry>b<subscript>2</subscript></entry> 482 440 <entry>b<subscript>1</subscript></entry> 483 441 <entry>b<subscript>0</subscript></entry> 442 + </row> 443 + <row id="MEDIA-BUS-FMT-RGB666-1X24_CPADHI"> 444 + <entry>MEDIA_BUS_FMT_RGB666_1X24_CPADHI</entry> 445 + <entry>0x1015</entry> 446 + <entry></entry> 447 + &dash-ent-8; 448 + <entry>0</entry> 449 + <entry>0</entry> 450 + <entry>r<subscript>5</subscript></entry> 451 + <entry>r<subscript>4</subscript></entry> 452 + <entry>r<subscript>3</subscript></entry> 453 + <entry>r<subscript>2</subscript></entry> 454 + <entry>r<subscript>1</subscript></entry> 455 + <entry>r<subscript>0</subscript></entry> 456 + <entry>0</entry> 457 + <entry>0</entry> 458 + <entry>g<subscript>5</subscript></entry> 459 + <entry>g<subscript>4</subscript></entry> 460 + <entry>g<subscript>3</subscript></entry> 461 + <entry>g<subscript>2</subscript></entry> 462 + <entry>g<subscript>1</subscript></entry> 463 + <entry>g<subscript>0</subscript></entry> 464 + <entry>0</entry> 465 + <entry>0</entry> 466 + <entry>b<subscript>5</subscript></entry> 467 + <entry>b<subscript>4</subscript></entry> 468 + <entry>b<subscript>3</subscript></entry> 469 + <entry>b<subscript>2</subscript></entry> 470 + <entry>b<subscript>1</subscript></entry> 471 + <entry>b<subscript>0</subscript></entry> 472 + </row> 473 + <row id="MEDIA-BUS-FMT-BGR888-1X24"> 474 + <entry>MEDIA_BUS_FMT_BGR888_1X24</entry> 475 + <entry>0x1013</entry> 476 + <entry></entry> 477 + &dash-ent-8; 478 + <entry>b<subscript>7</subscript></entry> 479 + <entry>b<subscript>6</subscript></entry> 480 + <entry>b<subscript>5</subscript></entry> 481 + <entry>b<subscript>4</subscript></entry> 482 + <entry>b<subscript>3</subscript></entry> 483 + <entry>b<subscript>2</subscript></entry> 484 + <entry>b<subscript>1</subscript></entry> 485 + <entry>b<subscript>0</subscript></entry> 486 + <entry>g<subscript>7</subscript></entry> 487 + <entry>g<subscript>6</subscript></entry> 488 + <entry>g<subscript>5</subscript></entry> 489 + <entry>g<subscript>4</subscript></entry> 490 + <entry>g<subscript>3</subscript></entry> 491 + <entry>g<subscript>2</subscript></entry> 492 + <entry>g<subscript>1</subscript></entry> 493 + <entry>g<subscript>0</subscript></entry> 494 + <entry>r<subscript>7</subscript></entry> 495 + <entry>r<subscript>6</subscript></entry> 496 + <entry>r<subscript>5</subscript></entry> 497 + <entry>r<subscript>4</subscript></entry> 498 + <entry>r<subscript>3</subscript></entry> 499 + <entry>r<subscript>2</subscript></entry> 500 + <entry>r<subscript>1</subscript></entry> 501 + <entry>r<subscript>0</subscript></entry> 502 + </row> 503 + <row id="MEDIA-BUS-FMT-GBR888-1X24"> 504 + <entry>MEDIA_BUS_FMT_GBR888_1X24</entry> 505 + <entry>0x1014</entry> 506 + <entry></entry> 507 + &dash-ent-8; 508 + <entry>g<subscript>7</subscript></entry> 509 + <entry>g<subscript>6</subscript></entry> 510 + <entry>g<subscript>5</subscript></entry> 511 + <entry>g<subscript>4</subscript></entry> 512 + <entry>g<subscript>3</subscript></entry> 513 + <entry>g<subscript>2</subscript></entry> 514 + <entry>g<subscript>1</subscript></entry> 515 + <entry>g<subscript>0</subscript></entry> 516 + <entry>b<subscript>7</subscript></entry> 517 + <entry>b<subscript>6</subscript></entry> 518 + <entry>b<subscript>5</subscript></entry> 519 + <entry>b<subscript>4</subscript></entry> 520 + <entry>b<subscript>3</subscript></entry> 521 + <entry>b<subscript>2</subscript></entry> 522 + <entry>b<subscript>1</subscript></entry> 523 + <entry>b<subscript>0</subscript></entry> 524 + <entry>r<subscript>7</subscript></entry> 525 + <entry>r<subscript>6</subscript></entry> 526 + <entry>r<subscript>5</subscript></entry> 527 + <entry>r<subscript>4</subscript></entry> 528 + <entry>r<subscript>3</subscript></entry> 529 + <entry>r<subscript>2</subscript></entry> 530 + <entry>r<subscript>1</subscript></entry> 531 + <entry>r<subscript>0</subscript></entry> 484 532 </row> 485 533 <row id="MEDIA-BUS-FMT-RGB888-1X24"> 486 534 <entry>MEDIA_BUS_FMT_RGB888_1X24</entry> ··· 710 578 <entry>b<subscript>2</subscript></entry> 711 579 <entry>b<subscript>1</subscript></entry> 712 580 <entry>b<subscript>0</subscript></entry> 581 + </row> 582 + </tbody> 583 + </tgroup> 584 + </table> 585 + 586 + <para>On LVDS buses, usually each sample is transferred serialized in 587 + seven time slots per pixel clock, on three (18-bit) or four (24-bit) 588 + differential data pairs at the same time. The remaining bits are used for 589 + control signals as defined by SPWG/PSWG/VESA or JEIDA standards. 590 + The 24-bit RGB format serialized in seven time slots on four lanes using 591 + JEIDA defined bit mapping will be named 592 + <constant>MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA</constant>, for example. 593 + </para> 594 + 595 + <table pgwide="0" frame="none" id="v4l2-mbus-pixelcode-rgb-lvds"> 596 + <title>LVDS RGB formats</title> 597 + <tgroup cols="8"> 598 + <colspec colname="id" align="left" /> 599 + <colspec colname="code" align="center" /> 600 + <colspec colname="slot" align="center" /> 601 + <colspec colname="lane" /> 602 + <colspec colnum="5" colname="l03" align="center" /> 603 + <colspec colnum="6" colname="l02" align="center" /> 604 + <colspec colnum="7" colname="l01" align="center" /> 605 + <colspec colnum="8" colname="l00" align="center" /> 606 + <spanspec namest="l03" nameend="l00" spanname="l0" /> 607 + <thead> 608 + <row> 609 + <entry>Identifier</entry> 610 + <entry>Code</entry> 611 + <entry></entry> 612 + <entry></entry> 613 + <entry spanname="l0">Data organization</entry> 614 + </row> 615 + <row> 616 + <entry></entry> 617 + <entry></entry> 618 + <entry>Timeslot</entry> 619 + <entry>Lane</entry> 620 + <entry>3</entry> 621 + <entry>2</entry> 622 + <entry>1</entry> 623 + <entry>0</entry> 624 + </row> 625 + </thead> 626 + <tbody valign="top"> 627 + <row id="MEDIA-BUS-FMT-RGB666-1X7X3-SPWG"> 628 + <entry>MEDIA_BUS_FMT_RGB666_1X7X3_SPWG</entry> 629 + <entry>0x1010</entry> 630 + <entry>0</entry> 631 + <entry></entry> 632 + <entry>-</entry> 633 + <entry>d</entry> 634 + <entry>b<subscript>1</subscript></entry> 635 + <entry>g<subscript>0</subscript></entry> 636 + </row> 637 + <row> 638 + <entry></entry> 639 + <entry></entry> 640 + <entry>1</entry> 641 + <entry></entry> 642 + <entry>-</entry> 643 + <entry>d</entry> 644 + <entry>b<subscript>0</subscript></entry> 645 + <entry>r<subscript>5</subscript></entry> 646 + </row> 647 + <row> 648 + <entry></entry> 649 + <entry></entry> 650 + <entry>2</entry> 651 + <entry></entry> 652 + <entry>-</entry> 653 + <entry>d</entry> 654 + <entry>g<subscript>5</subscript></entry> 655 + <entry>r<subscript>4</subscript></entry> 656 + </row> 657 + <row> 658 + <entry></entry> 659 + <entry></entry> 660 + <entry>3</entry> 661 + <entry></entry> 662 + <entry>-</entry> 663 + <entry>b<subscript>5</subscript></entry> 664 + <entry>g<subscript>4</subscript></entry> 665 + <entry>r<subscript>3</subscript></entry> 666 + </row> 667 + <row> 668 + <entry></entry> 669 + <entry></entry> 670 + <entry>4</entry> 671 + <entry></entry> 672 + <entry>-</entry> 673 + <entry>b<subscript>4</subscript></entry> 674 + <entry>g<subscript>3</subscript></entry> 675 + <entry>r<subscript>2</subscript></entry> 676 + </row> 677 + <row> 678 + <entry></entry> 679 + <entry></entry> 680 + <entry>5</entry> 681 + <entry></entry> 682 + <entry>-</entry> 683 + <entry>b<subscript>3</subscript></entry> 684 + <entry>g<subscript>2</subscript></entry> 685 + <entry>r<subscript>1</subscript></entry> 686 + </row> 687 + <row> 688 + <entry></entry> 689 + <entry></entry> 690 + <entry>6</entry> 691 + <entry></entry> 692 + <entry>-</entry> 693 + <entry>b<subscript>2</subscript></entry> 694 + <entry>g<subscript>1</subscript></entry> 695 + <entry>r<subscript>0</subscript></entry> 696 + </row> 697 + <row id="MEDIA-BUS-FMT-RGB888-1X7X4-SPWG"> 698 + <entry>MEDIA_BUS_FMT_RGB888_1X7X4_SPWG</entry> 699 + <entry>0x1011</entry> 700 + <entry>0</entry> 701 + <entry></entry> 702 + <entry>d</entry> 703 + <entry>d</entry> 704 + <entry>b<subscript>1</subscript></entry> 705 + <entry>g<subscript>0</subscript></entry> 706 + </row> 707 + <row> 708 + <entry></entry> 709 + <entry></entry> 710 + <entry>1</entry> 711 + <entry></entry> 712 + <entry>b<subscript>7</subscript></entry> 713 + <entry>d</entry> 714 + <entry>b<subscript>0</subscript></entry> 715 + <entry>r<subscript>5</subscript></entry> 716 + </row> 717 + <row> 718 + <entry></entry> 719 + <entry></entry> 720 + <entry>2</entry> 721 + <entry></entry> 722 + <entry>b<subscript>6</subscript></entry> 723 + <entry>d</entry> 724 + <entry>g<subscript>5</subscript></entry> 725 + <entry>r<subscript>4</subscript></entry> 726 + </row> 727 + <row> 728 + <entry></entry> 729 + <entry></entry> 730 + <entry>3</entry> 731 + <entry></entry> 732 + <entry>g<subscript>7</subscript></entry> 733 + <entry>b<subscript>5</subscript></entry> 734 + <entry>g<subscript>4</subscript></entry> 735 + <entry>r<subscript>3</subscript></entry> 736 + </row> 737 + <row> 738 + <entry></entry> 739 + <entry></entry> 740 + <entry>4</entry> 741 + <entry></entry> 742 + <entry>g<subscript>6</subscript></entry> 743 + <entry>b<subscript>4</subscript></entry> 744 + <entry>g<subscript>3</subscript></entry> 745 + <entry>r<subscript>2</subscript></entry> 746 + </row> 747 + <row> 748 + <entry></entry> 749 + <entry></entry> 750 + <entry>5</entry> 751 + <entry></entry> 752 + <entry>r<subscript>7</subscript></entry> 753 + <entry>b<subscript>3</subscript></entry> 754 + <entry>g<subscript>2</subscript></entry> 755 + <entry>r<subscript>1</subscript></entry> 756 + </row> 757 + <row> 758 + <entry></entry> 759 + <entry></entry> 760 + <entry>6</entry> 761 + <entry></entry> 762 + <entry>r<subscript>6</subscript></entry> 763 + <entry>b<subscript>2</subscript></entry> 764 + <entry>g<subscript>1</subscript></entry> 765 + <entry>r<subscript>0</subscript></entry> 766 + </row> 767 + <row id="MEDIA-BUS-FMT-RGB888-1X7X4-JEIDA"> 768 + <entry>MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA</entry> 769 + <entry>0x1012</entry> 770 + <entry>0</entry> 771 + <entry></entry> 772 + <entry>d</entry> 773 + <entry>d</entry> 774 + <entry>b<subscript>3</subscript></entry> 775 + <entry>g<subscript>2</subscript></entry> 776 + </row> 777 + <row> 778 + <entry></entry> 779 + <entry></entry> 780 + <entry>1</entry> 781 + <entry></entry> 782 + <entry>b<subscript>1</subscript></entry> 783 + <entry>d</entry> 784 + <entry>b<subscript>2</subscript></entry> 785 + <entry>r<subscript>7</subscript></entry> 786 + </row> 787 + <row> 788 + <entry></entry> 789 + <entry></entry> 790 + <entry>2</entry> 791 + <entry></entry> 792 + <entry>b<subscript>0</subscript></entry> 793 + <entry>d</entry> 794 + <entry>g<subscript>7</subscript></entry> 795 + <entry>r<subscript>6</subscript></entry> 796 + </row> 797 + <row> 798 + <entry></entry> 799 + <entry></entry> 800 + <entry>3</entry> 801 + <entry></entry> 802 + <entry>g<subscript>1</subscript></entry> 803 + <entry>b<subscript>7</subscript></entry> 804 + <entry>g<subscript>6</subscript></entry> 805 + <entry>r<subscript>5</subscript></entry> 806 + </row> 807 + <row> 808 + <entry></entry> 809 + <entry></entry> 810 + <entry>4</entry> 811 + <entry></entry> 812 + <entry>g<subscript>0</subscript></entry> 813 + <entry>b<subscript>6</subscript></entry> 814 + <entry>g<subscript>5</subscript></entry> 815 + <entry>r<subscript>4</subscript></entry> 816 + </row> 817 + <row> 818 + <entry></entry> 819 + <entry></entry> 820 + <entry>5</entry> 821 + <entry></entry> 822 + <entry>r<subscript>1</subscript></entry> 823 + <entry>b<subscript>5</subscript></entry> 824 + <entry>g<subscript>4</subscript></entry> 825 + <entry>r<subscript>3</subscript></entry> 826 + </row> 827 + <row> 828 + <entry></entry> 829 + <entry></entry> 830 + <entry>6</entry> 831 + <entry></entry> 832 + <entry>r<subscript>0</subscript></entry> 833 + <entry>b<subscript>4</subscript></entry> 834 + <entry>g<subscript>3</subscript></entry> 835 + <entry>r<subscript>2</subscript></entry> 713 836 </row> 714 837 </tbody> 715 838 </tgroup> ··· 3046 2659 <entry>u<subscript>2</subscript></entry> 3047 2660 <entry>u<subscript>1</subscript></entry> 3048 2661 <entry>u<subscript>0</subscript></entry> 2662 + </row> 2663 + <row id="MEDIA-BUS-FMT-YUV8-1X24"> 2664 + <entry>MEDIA_BUS_FMT_YUV8_1X24</entry> 2665 + <entry>0x2024</entry> 2666 + <entry></entry> 2667 + <entry>-</entry> 2668 + <entry>-</entry> 2669 + <entry>-</entry> 2670 + <entry>-</entry> 2671 + <entry>-</entry> 2672 + <entry>-</entry> 2673 + <entry>-</entry> 2674 + <entry>-</entry> 2675 + <entry>y<subscript>7</subscript></entry> 2676 + <entry>y<subscript>6</subscript></entry> 2677 + <entry>y<subscript>5</subscript></entry> 2678 + <entry>y<subscript>4</subscript></entry> 2679 + <entry>y<subscript>3</subscript></entry> 2680 + <entry>y<subscript>2</subscript></entry> 2681 + <entry>y<subscript>1</subscript></entry> 2682 + <entry>y<subscript>0</subscript></entry> 2683 + <entry>u<subscript>7</subscript></entry> 2684 + <entry>u<subscript>6</subscript></entry> 2685 + <entry>u<subscript>5</subscript></entry> 2686 + <entry>u<subscript>4</subscript></entry> 2687 + <entry>u<subscript>3</subscript></entry> 2688 + <entry>u<subscript>2</subscript></entry> 2689 + <entry>u<subscript>1</subscript></entry> 2690 + <entry>u<subscript>0</subscript></entry> 2691 + <entry>v<subscript>7</subscript></entry> 2692 + <entry>v<subscript>6</subscript></entry> 2693 + <entry>v<subscript>5</subscript></entry> 2694 + <entry>v<subscript>4</subscript></entry> 2695 + <entry>v<subscript>3</subscript></entry> 2696 + <entry>v<subscript>2</subscript></entry> 2697 + <entry>v<subscript>1</subscript></entry> 2698 + <entry>v<subscript>0</subscript></entry> 3049 2699 </row> 3050 2700 <row id="MEDIA-BUS-FMT-YUV10-1X30"> 3051 2701 <entry>MEDIA_BUS_FMT_YUV10_1X30</entry>

+43 -19

Documentation/devicetree/bindings/drm/imx/ldb.txt

··· 44 44 LVDS Channel 45 45 ============ 46 46 47 - Each LVDS Channel has to contain a display-timings node that describes the 48 - video timings for the connected LVDS display. For detailed information, also 49 - have a look at Documentation/devicetree/bindings/video/display-timing.txt. 47 + Each LVDS Channel has to contain either an of graph link to a panel device node 48 + or a display-timings node that describes the video timings for the connected 49 + LVDS display as well as the fsl,data-mapping and fsl,data-width properties. 50 50 51 51 Required properties: 52 52 - reg : should be <0> or <1> 53 + - port: Input and output port nodes with endpoint definitions as defined in 54 + Documentation/devicetree/bindings/graph.txt. 55 + On i.MX5, the internal two-input-multiplexer is used. Due to hardware 56 + limitations, only one input port (port@[0,1]) can be used for each channel 57 + (lvds-channel@[0,1], respectively). 58 + On i.MX6, there should be four input ports (port@[0-3]) that correspond 59 + to the four LVDS multiplexer inputs. 60 + A single output port (port@2 on i.MX5, port@4 on i.MX6) must be connected 61 + to a panel input port. Optionally, the output port can be left out if 62 + display-timings are used instead. 63 + 64 + Optional properties (required if display-timings are used): 65 + - display-timings : A node that describes the display timings as defined in 66 + Documentation/devicetree/bindings/video/display-timing.txt. 53 67 - fsl,data-mapping : should be "spwg" or "jeida" 54 68 This describes how the color bits are laid out in the 55 69 serialized LVDS signal. 56 70 - fsl,data-width : should be <18> or <24> 57 - - port: A port node with endpoint definitions as defined in 58 - Documentation/devicetree/bindings/media/video-interfaces.txt. 59 - On i.MX5, the internal two-input-multiplexer is used. 60 - Due to hardware limitations, only one port (port@[0,1]) 61 - can be used for each channel (lvds-channel@[0,1], respectively) 62 - On i.MX6, there should be four ports (port@[0-3]) that correspond 63 - to the four LVDS multiplexer inputs. 64 71 65 72 example: 66 73 ··· 80 73 #size-cells = <0>; 81 74 compatible = "fsl,imx53-ldb"; 82 75 gpr = <&gpr>; 83 - clocks = <&clks 122>, <&clks 120>, 84 - <&clks 115>, <&clks 116>, 85 - <&clks 123>, <&clks 85>; 76 + clocks = <&clks IMX5_CLK_LDB_DI0_SEL>, 77 + <&clks IMX5_CLK_LDB_DI1_SEL>, 78 + <&clks IMX5_CLK_IPU_DI0_SEL>, 79 + <&clks IMX5_CLK_IPU_DI1_SEL>, 80 + <&clks IMX5_CLK_LDB_DI0_GATE>, 81 + <&clks IMX5_CLK_LDB_DI1_GATE>; 86 82 clock-names = "di0_pll", "di1_pll", 87 83 "di0_sel", "di1_sel", 88 84 "di0", "di1"; 89 85 86 + /* Using an of-graph endpoint link to connect the panel */ 90 87 lvds-channel@0 { 91 88 #address-cells = <1>; 92 89 #size-cells = <0>; 93 90 reg = <0>; 94 - fsl,data-mapping = "spwg"; 95 - fsl,data-width = <24>; 96 - 97 - display-timings { 98 - /* ... */ 99 - }; 100 91 101 92 port@0 { 102 93 reg = <0>; ··· 103 98 remote-endpoint = <&ipu_di0_lvds0>; 104 99 }; 105 100 }; 101 + 102 + port@2 { 103 + reg = <2>; 104 + 105 + lvds0_out: endpoint { 106 + remote-endpoint = <&panel_in>; 107 + }; 108 + }; 106 109 }; 107 110 111 + /* Using display-timings and fsl,data-mapping/width instead */ 108 112 lvds-channel@1 { 109 113 #address-cells = <1>; 110 114 #size-cells = <0>; ··· 131 117 lvds1_in: endpoint { 132 118 remote-endpoint = <&ipu_di1_lvds1>; 133 119 }; 120 + }; 121 + }; 122 + }; 123 + 124 + panel: lvds-panel { 125 + /* ... */ 126 + 127 + port { 128 + panel_in: endpoint { 129 + remote-endpoint = <&lvds0_out>; 134 130 }; 135 131 }; 136 132 };

+1

drivers/gpu/drm/imx/Kconfig

··· 36 36 config DRM_IMX_LDB 37 37 tristate "Support for LVDS displays" 38 38 depends on DRM_IMX && MFD_SYSCON 39 + select DRM_PANEL 39 40 help 40 41 Choose this to enable the internal LVDS Display Bridge (LDB) 41 42 found on i.MX53 and i.MX6 processors.

+1 -1

drivers/gpu/drm/imx/dw_hdmi-imx.c

··· 123 123 124 124 static void dw_hdmi_imx_encoder_prepare(struct drm_encoder *encoder) 125 125 { 126 - imx_drm_panel_format(encoder, V4L2_PIX_FMT_RGB24); 126 + imx_drm_set_bus_format(encoder, MEDIA_BUS_FMT_RGB888_1X24); 127 127 } 128 128 129 129 static struct drm_encoder_helper_funcs dw_hdmi_imx_encoder_helper_funcs = {

+7 -7

drivers/gpu/drm/imx/imx-drm-core.c

··· 103 103 return NULL; 104 104 } 105 105 106 - int imx_drm_panel_format_pins(struct drm_encoder *encoder, 107 - u32 interface_pix_fmt, int hsync_pin, int vsync_pin) 106 + int imx_drm_set_bus_format_pins(struct drm_encoder *encoder, u32 bus_format, 107 + int hsync_pin, int vsync_pin) 108 108 { 109 109 struct imx_drm_crtc_helper_funcs *helper; 110 110 struct imx_drm_crtc *imx_crtc; ··· 116 116 helper = &imx_crtc->imx_drm_helper_funcs; 117 117 if (helper->set_interface_pix_fmt) 118 118 return helper->set_interface_pix_fmt(encoder->crtc, 119 - interface_pix_fmt, hsync_pin, vsync_pin); 119 + bus_format, hsync_pin, vsync_pin); 120 120 return 0; 121 121 } 122 - EXPORT_SYMBOL_GPL(imx_drm_panel_format_pins); 122 + EXPORT_SYMBOL_GPL(imx_drm_set_bus_format_pins); 123 123 124 - int imx_drm_panel_format(struct drm_encoder *encoder, u32 interface_pix_fmt) 124 + int imx_drm_set_bus_format(struct drm_encoder *encoder, u32 bus_format) 125 125 { 126 - return imx_drm_panel_format_pins(encoder, interface_pix_fmt, 2, 3); 126 + return imx_drm_set_bus_format_pins(encoder, bus_format, 2, 3); 127 127 } 128 - EXPORT_SYMBOL_GPL(imx_drm_panel_format); 128 + EXPORT_SYMBOL_GPL(imx_drm_set_bus_format); 129 129 130 130 int imx_drm_crtc_vblank_get(struct imx_drm_crtc *imx_drm_crtc) 131 131 {

+5 -5

drivers/gpu/drm/imx/imx-drm.h

··· 18 18 int (*enable_vblank)(struct drm_crtc *crtc); 19 19 void (*disable_vblank)(struct drm_crtc *crtc); 20 20 int (*set_interface_pix_fmt)(struct drm_crtc *crtc, 21 - u32 pix_fmt, int hsync_pin, int vsync_pin); 21 + u32 bus_format, int hsync_pin, int vsync_pin); 22 22 const struct drm_crtc_helper_funcs *crtc_helper_funcs; 23 23 const struct drm_crtc_funcs *crtc_funcs; 24 24 }; ··· 40 40 41 41 struct drm_gem_cma_object *imx_drm_fb_get_obj(struct drm_framebuffer *fb); 42 42 43 - int imx_drm_panel_format_pins(struct drm_encoder *encoder, 44 - u32 interface_pix_fmt, int hsync_pin, int vsync_pin); 45 - int imx_drm_panel_format(struct drm_encoder *encoder, 46 - u32 interface_pix_fmt); 43 + int imx_drm_set_bus_format_pins(struct drm_encoder *encoder, 44 + u32 bus_format, int hsync_pin, int vsync_pin); 45 + int imx_drm_set_bus_format(struct drm_encoder *encoder, 46 + u32 bus_format); 47 47 48 48 int imx_drm_encoder_get_mux_id(struct device_node *node, 49 49 struct drm_encoder *encoder);

+139 -59

drivers/gpu/drm/imx/imx-ldb.c

··· 19 19 #include <drm/drmP.h> 20 20 #include <drm/drm_fb_helper.h> 21 21 #include <drm/drm_crtc_helper.h> 22 + #include <drm/drm_panel.h> 22 23 #include <linux/mfd/syscon.h> 23 24 #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h> 24 - #include <linux/of_address.h> 25 25 #include <linux/of_device.h> 26 + #include <linux/of_graph.h> 26 27 #include <video/of_videomode.h> 27 28 #include <linux/regmap.h> 28 29 #include <linux/videodev2.h> ··· 56 55 struct imx_ldb *ldb; 57 56 struct drm_connector connector; 58 57 struct drm_encoder encoder; 58 + struct drm_panel *panel; 59 59 struct device_node *child; 60 60 int chno; 61 61 void *edid; 62 62 int edid_len; 63 63 struct drm_display_mode mode; 64 64 int mode_valid; 65 + int bus_format; 65 66 }; 66 67 67 68 struct bus_mux { ··· 78 75 struct imx_ldb_channel channel[2]; 79 76 struct clk *clk[2]; /* our own clock */ 80 77 struct clk *clk_sel[4]; /* parent of display clock */ 78 + struct clk *clk_parent[4]; /* original parent of clk_sel */ 81 79 struct clk *clk_pll[2]; /* upstream clock we can adjust */ 82 80 u32 ldb_ctrl; 83 81 const struct bus_mux *lvds_mux; ··· 94 90 { 95 91 struct imx_ldb_channel *imx_ldb_ch = con_to_imx_ldb_ch(connector); 96 92 int num_modes = 0; 93 + 94 + if (imx_ldb_ch->panel && imx_ldb_ch->panel->funcs && 95 + imx_ldb_ch->panel->funcs->get_modes) { 96 + struct drm_display_info *di = &connector->display_info; 97 + 98 + num_modes = imx_ldb_ch->panel->funcs->get_modes(imx_ldb_ch->panel); 99 + if (!imx_ldb_ch->bus_format && di->num_bus_formats) 100 + imx_ldb_ch->bus_format = di->bus_formats[0]; 101 + if (num_modes > 0) 102 + return num_modes; 103 + } 97 104 98 105 if (imx_ldb_ch->edid) { 99 106 drm_mode_connector_update_edid_property(connector, ··· 178 163 { 179 164 struct imx_ldb_channel *imx_ldb_ch = enc_to_imx_ldb_ch(encoder); 180 165 struct imx_ldb *ldb = imx_ldb_ch->ldb; 181 - u32 pixel_fmt; 166 + int dual = ldb->ldb_ctrl & LDB_SPLIT_MODE_EN; 167 + u32 bus_format; 182 168 183 - switch (imx_ldb_ch->chno) { 184 - case 0: 185 - pixel_fmt = (ldb->ldb_ctrl & LDB_DATA_WIDTH_CH0_24) ? 186 - V4L2_PIX_FMT_RGB24 : V4L2_PIX_FMT_BGR666; 187 - break; 188 - case 1: 189 - pixel_fmt = (ldb->ldb_ctrl & LDB_DATA_WIDTH_CH1_24) ? 190 - V4L2_PIX_FMT_RGB24 : V4L2_PIX_FMT_BGR666; 191 - break; 169 + switch (imx_ldb_ch->bus_format) { 192 170 default: 193 - dev_err(ldb->dev, "unable to config di%d panel format\n", 194 - imx_ldb_ch->chno); 195 - pixel_fmt = V4L2_PIX_FMT_RGB24; 171 + dev_warn(ldb->dev, 172 + "could not determine data mapping, default to 18-bit \"spwg\"\n"); 173 + /* fallthrough */ 174 + case MEDIA_BUS_FMT_RGB666_1X7X3_SPWG: 175 + bus_format = MEDIA_BUS_FMT_RGB666_1X18; 176 + break; 177 + case MEDIA_BUS_FMT_RGB888_1X7X4_SPWG: 178 + bus_format = MEDIA_BUS_FMT_RGB888_1X24; 179 + if (imx_ldb_ch->chno == 0 || dual) 180 + ldb->ldb_ctrl |= LDB_DATA_WIDTH_CH0_24; 181 + if (imx_ldb_ch->chno == 1 || dual) 182 + ldb->ldb_ctrl |= LDB_DATA_WIDTH_CH1_24; 183 + break; 184 + case MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA: 185 + bus_format = MEDIA_BUS_FMT_RGB888_1X24; 186 + if (imx_ldb_ch->chno == 0 || dual) 187 + ldb->ldb_ctrl |= LDB_DATA_WIDTH_CH0_24 | 188 + LDB_BIT_MAP_CH0_JEIDA; 189 + if (imx_ldb_ch->chno == 1 || dual) 190 + ldb->ldb_ctrl |= LDB_DATA_WIDTH_CH1_24 | 191 + LDB_BIT_MAP_CH1_JEIDA; 192 + break; 196 193 } 197 194 198 - imx_drm_panel_format(encoder, pixel_fmt); 195 + imx_drm_set_bus_format(encoder, bus_format); 199 196 } 200 197 201 198 static void imx_ldb_encoder_commit(struct drm_encoder *encoder) ··· 216 189 struct imx_ldb *ldb = imx_ldb_ch->ldb; 217 190 int dual = ldb->ldb_ctrl & LDB_SPLIT_MODE_EN; 218 191 int mux = imx_drm_encoder_get_mux_id(imx_ldb_ch->child, encoder); 192 + 193 + drm_panel_prepare(imx_ldb_ch->panel); 219 194 220 195 if (dual) { 221 196 clk_prepare_enable(ldb->clk[0]); ··· 252 223 } 253 224 254 225 regmap_write(ldb->regmap, IOMUXC_GPR2, ldb->ldb_ctrl); 226 + 227 + drm_panel_enable(imx_ldb_ch->panel); 255 228 } 256 229 257 230 static void imx_ldb_encoder_mode_set(struct drm_encoder *encoder, ··· 305 274 { 306 275 struct imx_ldb_channel *imx_ldb_ch = enc_to_imx_ldb_ch(encoder); 307 276 struct imx_ldb *ldb = imx_ldb_ch->ldb; 277 + int mux, ret; 308 278 309 279 /* 310 280 * imx_ldb_encoder_disable is called by ··· 319 287 (ldb->ldb_ctrl & LDB_CH1_MODE_EN_MASK) == 0) 320 288 return; 321 289 290 + drm_panel_disable(imx_ldb_ch->panel); 291 + 322 292 if (imx_ldb_ch == &ldb->channel[0]) 323 293 ldb->ldb_ctrl &= ~LDB_CH0_MODE_EN_MASK; 324 294 else if (imx_ldb_ch == &ldb->channel[1]) ··· 332 298 clk_disable_unprepare(ldb->clk[0]); 333 299 clk_disable_unprepare(ldb->clk[1]); 334 300 } 301 + 302 + if (ldb->lvds_mux) { 303 + const struct bus_mux *lvds_mux = NULL; 304 + 305 + if (imx_ldb_ch == &ldb->channel[0]) 306 + lvds_mux = &ldb->lvds_mux[0]; 307 + else if (imx_ldb_ch == &ldb->channel[1]) 308 + lvds_mux = &ldb->lvds_mux[1]; 309 + 310 + regmap_read(ldb->regmap, lvds_mux->reg, &mux); 311 + mux &= lvds_mux->mask; 312 + mux >>= lvds_mux->shift; 313 + } else { 314 + mux = (imx_ldb_ch == &ldb->channel[0]) ? 0 : 1; 315 + } 316 + 317 + /* set display clock mux back to original input clock */ 318 + ret = clk_set_parent(ldb->clk_sel[mux], ldb->clk_parent[mux]); 319 + if (ret) 320 + dev_err(ldb->dev, 321 + "unable to set di%d parent clock to original parent\n", 322 + mux); 323 + 324 + drm_panel_unprepare(imx_ldb_ch->panel); 335 325 } 336 326 337 327 static struct drm_connector_funcs imx_ldb_connector_funcs = { ··· 429 371 drm_connector_init(drm, &imx_ldb_ch->connector, 430 372 &imx_ldb_connector_funcs, DRM_MODE_CONNECTOR_LVDS); 431 373 374 + if (imx_ldb_ch->panel) 375 + drm_panel_attach(imx_ldb_ch->panel, &imx_ldb_ch->connector); 376 + 432 377 drm_mode_connector_attach_encoder(&imx_ldb_ch->connector, 433 378 &imx_ldb_ch->encoder); 434 379 ··· 443 382 LVDS_BIT_MAP_JEIDA 444 383 }; 445 384 446 - static const char * const imx_ldb_bit_mappings[] = { 447 - [LVDS_BIT_MAP_SPWG] = "spwg", 448 - [LVDS_BIT_MAP_JEIDA] = "jeida", 385 + struct imx_ldb_bit_mapping { 386 + u32 bus_format; 387 + u32 datawidth; 388 + const char * const mapping; 449 389 }; 450 390 451 - static const int of_get_data_mapping(struct device_node *np) 391 + static const struct imx_ldb_bit_mapping imx_ldb_bit_mappings[] = { 392 + { MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 18, "spwg" }, 393 + { MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 24, "spwg" }, 394 + { MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 24, "jeida" }, 395 + }; 396 + 397 + static u32 of_get_bus_format(struct device *dev, struct device_node *np) 452 398 { 453 399 const char *bm; 400 + u32 datawidth = 0; 454 401 int ret, i; 455 402 456 403 ret = of_property_read_string(np, "fsl,data-mapping", &bm); 457 404 if (ret < 0) 458 405 return ret; 459 406 460 - for (i = 0; i < ARRAY_SIZE(imx_ldb_bit_mappings); i++) 461 - if (!strcasecmp(bm, imx_ldb_bit_mappings[i])) 462 - return i; 407 + of_property_read_u32(np, "fsl,data-width", &datawidth); 463 408 464 - return -EINVAL; 409 + for (i = 0; i < ARRAY_SIZE(imx_ldb_bit_mappings); i++) { 410 + if (!strcasecmp(bm, imx_ldb_bit_mappings[i].mapping) && 411 + datawidth == imx_ldb_bit_mappings[i].datawidth) 412 + return imx_ldb_bit_mappings[i].bus_format; 413 + } 414 + 415 + dev_err(dev, "invalid data mapping: %d-bit \"%s\"\n", datawidth, bm); 416 + 417 + return -ENOENT; 465 418 } 466 419 467 420 static struct bus_mux imx6q_lvds_mux[2] = { ··· 512 437 struct device_node *child; 513 438 const u8 *edidp; 514 439 struct imx_ldb *imx_ldb; 515 - int datawidth; 516 - int mapping; 517 440 int dual; 518 441 int ret; 519 442 int i; ··· 552 479 imx_ldb->clk_sel[i] = NULL; 553 480 break; 554 481 } 482 + 483 + imx_ldb->clk_parent[i] = clk_get_parent(imx_ldb->clk_sel[i]); 555 484 } 556 485 if (i == 0) 557 486 return ret; 558 487 559 488 for_each_child_of_node(np, child) { 560 489 struct imx_ldb_channel *channel; 490 + struct device_node *port; 561 491 562 492 ret = of_property_read_u32(child, "reg", &i); 563 493 if (ret || i < 0 || i > 1) ··· 579 503 channel->chno = i; 580 504 channel->child = child; 581 505 506 + /* 507 + * The output port is port@4 with an external 4-port mux or 508 + * port@2 with the internal 2-port mux. 509 + */ 510 + port = of_graph_get_port_by_id(child, imx_ldb->lvds_mux ? 4 : 2); 511 + if (port) { 512 + struct device_node *endpoint, *remote; 513 + 514 + endpoint = of_get_child_by_name(port, "endpoint"); 515 + if (endpoint) { 516 + remote = of_graph_get_remote_port_parent(endpoint); 517 + if (remote) 518 + channel->panel = of_drm_find_panel(remote); 519 + else 520 + return -EPROBE_DEFER; 521 + if (!channel->panel) { 522 + dev_err(dev, "panel not found: %s\n", 523 + remote->full_name); 524 + return -EPROBE_DEFER; 525 + } 526 + } 527 + } 528 + 582 529 edidp = of_get_property(child, "edid", &channel->edid_len); 583 530 if (edidp) { 584 531 channel->edid = kmemdup(edidp, channel->edid_len, 585 532 GFP_KERNEL); 586 - } else { 533 + } else if (!channel->panel) { 587 534 ret = of_get_drm_display_mode(child, &channel->mode, 0); 588 535 if (!ret) 589 536 channel->mode_valid = 1; 590 537 } 591 538 592 - ret = of_property_read_u32(child, "fsl,data-width", &datawidth); 593 - if (ret) 594 - datawidth = 0; 595 - else if (datawidth != 18 && datawidth != 24) 596 - return -EINVAL; 597 - 598 - mapping = of_get_data_mapping(child); 599 - switch (mapping) { 600 - case LVDS_BIT_MAP_SPWG: 601 - if (datawidth == 24) { 602 - if (i == 0 || dual) 603 - imx_ldb->ldb_ctrl |= 604 - LDB_DATA_WIDTH_CH0_24; 605 - if (i == 1 || dual) 606 - imx_ldb->ldb_ctrl |= 607 - LDB_DATA_WIDTH_CH1_24; 608 - } 609 - break; 610 - case LVDS_BIT_MAP_JEIDA: 611 - if (datawidth == 18) { 612 - dev_err(dev, "JEIDA standard only supported in 24 bit\n"); 613 - return -EINVAL; 614 - } 615 - if (i == 0 || dual) 616 - imx_ldb->ldb_ctrl |= LDB_DATA_WIDTH_CH0_24 | 617 - LDB_BIT_MAP_CH0_JEIDA; 618 - if (i == 1 || dual) 619 - imx_ldb->ldb_ctrl |= LDB_DATA_WIDTH_CH1_24 | 620 - LDB_BIT_MAP_CH1_JEIDA; 621 - break; 622 - default: 623 - dev_err(dev, "data mapping not specified or invalid\n"); 624 - return -EINVAL; 539 + channel->bus_format = of_get_bus_format(dev, child); 540 + if (channel->bus_format == -EINVAL) { 541 + /* 542 + * If no bus format was specified in the device tree, 543 + * we can still get it from the connected panel later. 544 + */ 545 + if (channel->panel && channel->panel->funcs && 546 + channel->panel->funcs->get_modes) 547 + channel->bus_format = 0; 548 + } 549 + if (channel->bus_format < 0) { 550 + dev_err(dev, "could not determine data mapping: %d\n", 551 + channel->bus_format); 552 + return channel->bus_format; 625 553 } 626 554 627 555 ret = imx_ldb_register(drm, channel);

+3 -3

drivers/gpu/drm/imx/imx-tve.c

··· 301 301 302 302 switch (tve->mode) { 303 303 case TVE_MODE_VGA: 304 - imx_drm_panel_format_pins(encoder, IPU_PIX_FMT_GBR24, 305 - tve->hsync_pin, tve->vsync_pin); 304 + imx_drm_set_bus_format_pins(encoder, MEDIA_BUS_FMT_YUV8_1X24, 305 + tve->hsync_pin, tve->vsync_pin); 306 306 break; 307 307 case TVE_MODE_TVOUT: 308 - imx_drm_panel_format(encoder, V4L2_PIX_FMT_YUV444); 308 + imx_drm_set_bus_format(encoder, MEDIA_BUS_FMT_YUV8_1X24); 309 309 break; 310 310 } 311 311 }

+12 -12

drivers/gpu/drm/imx/ipuv3-crtc.c

··· 45 45 struct drm_pending_vblank_event *page_flip_event; 46 46 struct drm_framebuffer *newfb; 47 47 int irq; 48 - u32 interface_pix_fmt; 48 + u32 bus_format; 49 49 int di_hsync_pin; 50 50 int di_vsync_pin; 51 51 }; ··· 145 145 struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc); 146 146 struct ipu_di_signal_cfg sig_cfg = {}; 147 147 unsigned long encoder_types = 0; 148 - u32 out_pixel_fmt; 149 148 int ret; 150 149 151 150 dev_dbg(ipu_crtc->dev, "%s: mode->hdisplay: %d\n", __func__, ··· 160 161 __func__, encoder_types); 161 162 162 163 /* 163 - * If we have DAC, TVDAC or LDB, then we need the IPU DI clock 164 - * to be the same as the LDB DI clock. 164 + * If we have DAC or LDB, then we need the IPU DI clock to be 165 + * the same as the LDB DI clock. For TVDAC, derive the IPU DI 166 + * clock from 27 MHz TVE_DI clock, but allow to divide it. 165 167 */ 166 168 if (encoder_types & (BIT(DRM_MODE_ENCODER_DAC) | 167 - BIT(DRM_MODE_ENCODER_TVDAC) | 168 169 BIT(DRM_MODE_ENCODER_LVDS))) 169 170 sig_cfg.clkflags = IPU_DI_CLKMODE_SYNC | IPU_DI_CLKMODE_EXT; 171 + else if (encoder_types & BIT(DRM_MODE_ENCODER_TVDAC)) 172 + sig_cfg.clkflags = IPU_DI_CLKMODE_EXT; 170 173 else 171 174 sig_cfg.clkflags = 0; 172 175 173 - out_pixel_fmt = ipu_crtc->interface_pix_fmt; 174 - 175 176 sig_cfg.enable_pol = 1; 176 177 sig_cfg.clk_pol = 0; 177 - sig_cfg.pixel_fmt = out_pixel_fmt; 178 + sig_cfg.bus_format = ipu_crtc->bus_format; 178 179 sig_cfg.v_to_h_sync = 0; 179 180 sig_cfg.hsync_pin = ipu_crtc->di_hsync_pin; 180 181 sig_cfg.vsync_pin = ipu_crtc->di_vsync_pin; ··· 183 184 184 185 ret = ipu_dc_init_sync(ipu_crtc->dc, ipu_crtc->di, 185 186 mode->flags & DRM_MODE_FLAG_INTERLACE, 186 - out_pixel_fmt, mode->hdisplay); 187 + ipu_crtc->bus_format, mode->hdisplay); 187 188 if (ret) { 188 189 dev_err(ipu_crtc->dev, 189 190 "initializing display controller failed with %d\n", ··· 201 202 return ipu_plane_mode_set(ipu_crtc->plane[0], crtc, mode, 202 203 crtc->primary->fb, 203 204 0, 0, mode->hdisplay, mode->vdisplay, 204 - x, y, mode->hdisplay, mode->vdisplay); 205 + x, y, mode->hdisplay, mode->vdisplay, 206 + mode->flags & DRM_MODE_FLAG_INTERLACE); 205 207 } 206 208 207 209 static void ipu_crtc_handle_pageflip(struct ipu_crtc *ipu_crtc) ··· 291 291 } 292 292 293 293 static int ipu_set_interface_pix_fmt(struct drm_crtc *crtc, 294 - u32 pixfmt, int hsync_pin, int vsync_pin) 294 + u32 bus_format, int hsync_pin, int vsync_pin) 295 295 { 296 296 struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc); 297 297 298 - ipu_crtc->interface_pix_fmt = pixfmt; 298 + ipu_crtc->bus_format = bus_format; 299 299 ipu_crtc->di_hsync_pin = hsync_pin; 300 300 ipu_crtc->di_vsync_pin = vsync_pin; 301 301

+5 -2

drivers/gpu/drm/imx/ipuv3-plane.c

··· 99 99 struct drm_framebuffer *fb, int crtc_x, int crtc_y, 100 100 unsigned int crtc_w, unsigned int crtc_h, 101 101 uint32_t src_x, uint32_t src_y, 102 - uint32_t src_w, uint32_t src_h) 102 + uint32_t src_w, uint32_t src_h, bool interlaced) 103 103 { 104 104 struct device *dev = ipu_plane->base.dev->dev; 105 105 int ret; ··· 213 213 ret = ipu_plane_set_base(ipu_plane, fb, src_x, src_y); 214 214 if (ret < 0) 215 215 return ret; 216 + if (interlaced) 217 + ipu_cpmem_interlaced_scan(ipu_plane->ipu_ch, fb->pitches[0]); 216 218 217 219 ipu_plane->w = src_w; 218 220 ipu_plane->h = src_h; ··· 314 312 315 313 ret = ipu_plane_mode_set(ipu_plane, crtc, &crtc->hwmode, fb, 316 314 crtc_x, crtc_y, crtc_w, crtc_h, 317 - src_x >> 16, src_y >> 16, src_w >> 16, src_h >> 16); 315 + src_x >> 16, src_y >> 16, src_w >> 16, src_h >> 16, 316 + false); 318 317 if (ret < 0) { 319 318 ipu_plane_put_resources(ipu_plane); 320 319 return ret;

+1 -1

drivers/gpu/drm/imx/ipuv3-plane.h

··· 42 42 struct drm_framebuffer *fb, int crtc_x, int crtc_y, 43 43 unsigned int crtc_w, unsigned int crtc_h, 44 44 uint32_t src_x, uint32_t src_y, uint32_t src_w, 45 - uint32_t src_h); 45 + uint32_t src_h, bool interlaced); 46 46 47 47 void ipu_plane_enable(struct ipu_plane *plane); 48 48 void ipu_plane_disable(struct ipu_plane *plane);

+6 -7

drivers/gpu/drm/imx/parallel-display.c

··· 33 33 struct device *dev; 34 34 void *edid; 35 35 int edid_len; 36 - u32 interface_pix_fmt; 36 + u32 bus_format; 37 37 int mode_valid; 38 38 struct drm_display_mode mode; 39 39 struct drm_panel *panel; ··· 118 118 { 119 119 struct imx_parallel_display *imxpd = enc_to_imxpd(encoder); 120 120 121 - imx_drm_panel_format(encoder, imxpd->interface_pix_fmt); 121 + imx_drm_set_bus_format(encoder, imxpd->bus_format); 122 122 } 123 123 124 124 static void imx_pd_encoder_commit(struct drm_encoder *encoder) ··· 225 225 ret = of_property_read_string(np, "interface-pix-fmt", &fmt); 226 226 if (!ret) { 227 227 if (!strcmp(fmt, "rgb24")) 228 - imxpd->interface_pix_fmt = V4L2_PIX_FMT_RGB24; 228 + imxpd->bus_format = MEDIA_BUS_FMT_RGB888_1X24; 229 229 else if (!strcmp(fmt, "rgb565")) 230 - imxpd->interface_pix_fmt = V4L2_PIX_FMT_RGB565; 230 + imxpd->bus_format = MEDIA_BUS_FMT_RGB565_1X16; 231 231 else if (!strcmp(fmt, "bgr666")) 232 - imxpd->interface_pix_fmt = V4L2_PIX_FMT_BGR666; 232 + imxpd->bus_format = MEDIA_BUS_FMT_RGB666_1X18; 233 233 else if (!strcmp(fmt, "lvds666")) 234 - imxpd->interface_pix_fmt = 235 - v4l2_fourcc('L', 'V', 'D', '6'); 234 + imxpd->bus_format = MEDIA_BUS_FMT_RGB666_1X24_CPADHI; 236 235 } 237 236 238 237 panel_node = of_parse_phandle(np, "fsl,panel", 0);

+9 -9

drivers/gpu/ipu-v3/ipu-dc.c

··· 147 147 writel(reg2, priv->dc_tmpl_reg + word * 8 + 4); 148 148 } 149 149 150 - static int ipu_pixfmt_to_map(u32 fmt) 150 + static int ipu_bus_format_to_map(u32 fmt) 151 151 { 152 152 switch (fmt) { 153 - case V4L2_PIX_FMT_RGB24: 153 + case MEDIA_BUS_FMT_RGB888_1X24: 154 154 return IPU_DC_MAP_RGB24; 155 - case V4L2_PIX_FMT_RGB565: 155 + case MEDIA_BUS_FMT_RGB565_1X16: 156 156 return IPU_DC_MAP_RGB565; 157 - case IPU_PIX_FMT_GBR24: 157 + case MEDIA_BUS_FMT_GBR888_1X24: 158 158 return IPU_DC_MAP_GBR24; 159 - case V4L2_PIX_FMT_BGR666: 159 + case MEDIA_BUS_FMT_RGB666_1X18: 160 160 return IPU_DC_MAP_BGR666; 161 - case v4l2_fourcc('L', 'V', 'D', '6'): 161 + case MEDIA_BUS_FMT_RGB666_1X24_CPADHI: 162 162 return IPU_DC_MAP_LVDS666; 163 - case V4L2_PIX_FMT_BGR24: 163 + case MEDIA_BUS_FMT_BGR888_1X24: 164 164 return IPU_DC_MAP_BGR24; 165 165 default: 166 166 return -EINVAL; ··· 168 168 } 169 169 170 170 int ipu_dc_init_sync(struct ipu_dc *dc, struct ipu_di *di, bool interlaced, 171 - u32 pixel_fmt, u32 width) 171 + u32 bus_format, u32 width) 172 172 { 173 173 struct ipu_dc_priv *priv = dc->priv; 174 174 u32 reg = 0; ··· 176 176 177 177 dc->di = ipu_di_get_num(di); 178 178 179 - map = ipu_pixfmt_to_map(pixel_fmt); 179 + map = ipu_bus_format_to_map(bus_format); 180 180 if (map < 0) { 181 181 dev_dbg(priv->dev, "IPU_DISP: No MAP\n"); 182 182 return map;

+11 -2

include/uapi/linux/media-bus-format.h

··· 33 33 34 34 #define MEDIA_BUS_FMT_FIXED 0x0001 35 35 36 - /* RGB - next is 0x100e */ 36 + /* RGB - next is 0x1016 */ 37 + #define MEDIA_BUS_FMT_RGB444_1X12 0x100e 37 38 #define MEDIA_BUS_FMT_RGB444_2X8_PADHI_BE 0x1001 38 39 #define MEDIA_BUS_FMT_RGB444_2X8_PADHI_LE 0x1002 39 40 #define MEDIA_BUS_FMT_RGB555_2X8_PADHI_BE 0x1003 40 41 #define MEDIA_BUS_FMT_RGB555_2X8_PADHI_LE 0x1004 42 + #define MEDIA_BUS_FMT_RGB565_1X16 0x100f 41 43 #define MEDIA_BUS_FMT_BGR565_2X8_BE 0x1005 42 44 #define MEDIA_BUS_FMT_BGR565_2X8_LE 0x1006 43 45 #define MEDIA_BUS_FMT_RGB565_2X8_BE 0x1007 44 46 #define MEDIA_BUS_FMT_RGB565_2X8_LE 0x1008 45 47 #define MEDIA_BUS_FMT_RGB666_1X18 0x1009 48 + #define MEDIA_BUS_FMT_RGB666_1X24_CPADHI 0x1015 49 + #define MEDIA_BUS_FMT_RGB666_1X7X3_SPWG 0x1010 50 + #define MEDIA_BUS_FMT_BGR888_1X24 0x1013 51 + #define MEDIA_BUS_FMT_GBR888_1X24 0x1014 46 52 #define MEDIA_BUS_FMT_RGB888_1X24 0x100a 47 53 #define MEDIA_BUS_FMT_RGB888_2X12_BE 0x100b 48 54 #define MEDIA_BUS_FMT_RGB888_2X12_LE 0x100c 55 + #define MEDIA_BUS_FMT_RGB888_1X7X4_SPWG 0x1011 56 + #define MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA 0x1012 49 57 #define MEDIA_BUS_FMT_ARGB8888_1X32 0x100d 50 58 51 - /* YUV (including grey) - next is 0x2024 */ 59 + /* YUV (including grey) - next is 0x2025 */ 52 60 #define MEDIA_BUS_FMT_Y8_1X8 0x2001 53 61 #define MEDIA_BUS_FMT_UV8_1X8 0x2015 54 62 #define MEDIA_BUS_FMT_UYVY8_1_5X8 0x2002 ··· 82 74 #define MEDIA_BUS_FMT_VYUY10_1X20 0x201b 83 75 #define MEDIA_BUS_FMT_YUYV10_1X20 0x200d 84 76 #define MEDIA_BUS_FMT_YVYU10_1X20 0x200e 77 + #define MEDIA_BUS_FMT_YUV8_1X24 0x2024 85 78 #define MEDIA_BUS_FMT_YUV10_1X30 0x2016 86 79 #define MEDIA_BUS_FMT_AYUV8_1X32 0x2017 87 80 #define MEDIA_BUS_FMT_UYVY12_2X12 0x201c

+1 -1

include/video/imx-ipu-v3.h

··· 39 39 40 40 struct videomode mode; 41 41 42 - u32 pixel_fmt; 42 + u32 bus_format; 43 43 u32 v_to_h_sync; 44 44 45 45 #define IPU_DI_CLKMODE_SYNC (1 << 0)