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arm64: make mrs_s prefixing implicit in read_cpuid

Commit 0f54b14e76f5302a ("arm64: cpufeature: Change read_cpuid() to use
sysreg's mrs_s macro") changed read_cpuid to require a SYS_ prefix on
register names, to allow manual assembly of registers unknown by the
toolchain, using tables in sysreg.h.

This interacts poorly with commit 42b55734030c1f72 ("efi/arm64: Check
for h/w support before booting a >4 KB granular kernel"), which is
curretly queued via the tip tree, and uses read_cpuid without a SYS_
prefix. Due to this, a build of next-20160304 fails if EFI and 64K pages
are selected.

To avoid this issue when trees are merged, move the required SYS_
prefixing into read_cpuid, and revert all of the updated callsites to
pass plain register names. This effectively reverts the bulk of commit
0f54b14e76f5302a.

Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Cc: James Morse <james.morse@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>

authored by

Mark Rutland and committed by
Catalin Marinas 1cc6ed90 57efac2f

+60 -60
+1 -1
arch/arm64/include/asm/cpufeature.h
··· 181 181 182 182 static inline bool cpu_supports_mixed_endian_el0(void) 183 183 { 184 - return id_aa64mmfr0_mixed_endian_el0(read_cpuid(SYS_ID_AA64MMFR0_EL1)); 184 + return id_aa64mmfr0_mixed_endian_el0(read_cpuid(ID_AA64MMFR0_EL1)); 185 185 } 186 186 187 187 static inline bool system_supports_mixed_endian_el0(void)
+4 -4
arch/arm64/include/asm/cputype.h
··· 90 90 91 91 #define read_cpuid(reg) ({ \ 92 92 u64 __val; \ 93 - asm("mrs_s %0, " __stringify(reg) : "=r" (__val)); \ 93 + asm("mrs_s %0, " __stringify(SYS_ ## reg) : "=r" (__val)); \ 94 94 __val; \ 95 95 }) 96 96 ··· 101 101 */ 102 102 static inline u32 __attribute_const__ read_cpuid_id(void) 103 103 { 104 - return read_cpuid(SYS_MIDR_EL1); 104 + return read_cpuid(MIDR_EL1); 105 105 } 106 106 107 107 static inline u64 __attribute_const__ read_cpuid_mpidr(void) 108 108 { 109 - return read_cpuid(SYS_MPIDR_EL1); 109 + return read_cpuid(MPIDR_EL1); 110 110 } 111 111 112 112 static inline unsigned int __attribute_const__ read_cpuid_implementor(void) ··· 121 121 122 122 static inline u32 __attribute_const__ read_cpuid_cachetype(void) 123 123 { 124 - return read_cpuid(SYS_CTR_EL0); 124 + return read_cpuid(CTR_EL0); 125 125 } 126 126 #endif /* __ASSEMBLY__ */ 127 127
+28 -28
arch/arm64/kernel/cpufeature.c
··· 855 855 static u64 __raw_read_system_reg(u32 sys_id) 856 856 { 857 857 switch (sys_id) { 858 - case SYS_ID_PFR0_EL1: return read_cpuid(SYS_ID_PFR0_EL1); 859 - case SYS_ID_PFR1_EL1: return read_cpuid(SYS_ID_PFR1_EL1); 860 - case SYS_ID_DFR0_EL1: return read_cpuid(SYS_ID_DFR0_EL1); 861 - case SYS_ID_MMFR0_EL1: return read_cpuid(SYS_ID_MMFR0_EL1); 862 - case SYS_ID_MMFR1_EL1: return read_cpuid(SYS_ID_MMFR1_EL1); 863 - case SYS_ID_MMFR2_EL1: return read_cpuid(SYS_ID_MMFR2_EL1); 864 - case SYS_ID_MMFR3_EL1: return read_cpuid(SYS_ID_MMFR3_EL1); 865 - case SYS_ID_ISAR0_EL1: return read_cpuid(SYS_ID_ISAR0_EL1); 866 - case SYS_ID_ISAR1_EL1: return read_cpuid(SYS_ID_ISAR1_EL1); 867 - case SYS_ID_ISAR2_EL1: return read_cpuid(SYS_ID_ISAR2_EL1); 868 - case SYS_ID_ISAR3_EL1: return read_cpuid(SYS_ID_ISAR3_EL1); 869 - case SYS_ID_ISAR4_EL1: return read_cpuid(SYS_ID_ISAR4_EL1); 870 - case SYS_ID_ISAR5_EL1: return read_cpuid(SYS_ID_ISAR4_EL1); 871 - case SYS_MVFR0_EL1: return read_cpuid(SYS_MVFR0_EL1); 872 - case SYS_MVFR1_EL1: return read_cpuid(SYS_MVFR1_EL1); 873 - case SYS_MVFR2_EL1: return read_cpuid(SYS_MVFR2_EL1); 858 + case SYS_ID_PFR0_EL1: return read_cpuid(ID_PFR0_EL1); 859 + case SYS_ID_PFR1_EL1: return read_cpuid(ID_PFR1_EL1); 860 + case SYS_ID_DFR0_EL1: return read_cpuid(ID_DFR0_EL1); 861 + case SYS_ID_MMFR0_EL1: return read_cpuid(ID_MMFR0_EL1); 862 + case SYS_ID_MMFR1_EL1: return read_cpuid(ID_MMFR1_EL1); 863 + case SYS_ID_MMFR2_EL1: return read_cpuid(ID_MMFR2_EL1); 864 + case SYS_ID_MMFR3_EL1: return read_cpuid(ID_MMFR3_EL1); 865 + case SYS_ID_ISAR0_EL1: return read_cpuid(ID_ISAR0_EL1); 866 + case SYS_ID_ISAR1_EL1: return read_cpuid(ID_ISAR1_EL1); 867 + case SYS_ID_ISAR2_EL1: return read_cpuid(ID_ISAR2_EL1); 868 + case SYS_ID_ISAR3_EL1: return read_cpuid(ID_ISAR3_EL1); 869 + case SYS_ID_ISAR4_EL1: return read_cpuid(ID_ISAR4_EL1); 870 + case SYS_ID_ISAR5_EL1: return read_cpuid(ID_ISAR4_EL1); 871 + case SYS_MVFR0_EL1: return read_cpuid(MVFR0_EL1); 872 + case SYS_MVFR1_EL1: return read_cpuid(MVFR1_EL1); 873 + case SYS_MVFR2_EL1: return read_cpuid(MVFR2_EL1); 874 874 875 - case SYS_ID_AA64PFR0_EL1: return read_cpuid(SYS_ID_AA64PFR0_EL1); 876 - case SYS_ID_AA64PFR1_EL1: return read_cpuid(SYS_ID_AA64PFR0_EL1); 877 - case SYS_ID_AA64DFR0_EL1: return read_cpuid(SYS_ID_AA64DFR0_EL1); 878 - case SYS_ID_AA64DFR1_EL1: return read_cpuid(SYS_ID_AA64DFR0_EL1); 879 - case SYS_ID_AA64MMFR0_EL1: return read_cpuid(SYS_ID_AA64MMFR0_EL1); 880 - case SYS_ID_AA64MMFR1_EL1: return read_cpuid(SYS_ID_AA64MMFR1_EL1); 881 - case SYS_ID_AA64MMFR2_EL1: return read_cpuid(SYS_ID_AA64MMFR2_EL1); 882 - case SYS_ID_AA64ISAR0_EL1: return read_cpuid(SYS_ID_AA64ISAR0_EL1); 883 - case SYS_ID_AA64ISAR1_EL1: return read_cpuid(SYS_ID_AA64ISAR1_EL1); 875 + case SYS_ID_AA64PFR0_EL1: return read_cpuid(ID_AA64PFR0_EL1); 876 + case SYS_ID_AA64PFR1_EL1: return read_cpuid(ID_AA64PFR0_EL1); 877 + case SYS_ID_AA64DFR0_EL1: return read_cpuid(ID_AA64DFR0_EL1); 878 + case SYS_ID_AA64DFR1_EL1: return read_cpuid(ID_AA64DFR0_EL1); 879 + case SYS_ID_AA64MMFR0_EL1: return read_cpuid(ID_AA64MMFR0_EL1); 880 + case SYS_ID_AA64MMFR1_EL1: return read_cpuid(ID_AA64MMFR1_EL1); 881 + case SYS_ID_AA64MMFR2_EL1: return read_cpuid(ID_AA64MMFR2_EL1); 882 + case SYS_ID_AA64ISAR0_EL1: return read_cpuid(ID_AA64ISAR0_EL1); 883 + case SYS_ID_AA64ISAR1_EL1: return read_cpuid(ID_AA64ISAR1_EL1); 884 884 885 - case SYS_CNTFRQ_EL0: return read_cpuid(SYS_CNTFRQ_EL0); 886 - case SYS_CTR_EL0: return read_cpuid(SYS_CTR_EL0); 887 - case SYS_DCZID_EL0: return read_cpuid(SYS_DCZID_EL0); 885 + case SYS_CNTFRQ_EL0: return read_cpuid(CNTFRQ_EL0); 886 + case SYS_CTR_EL0: return read_cpuid(CTR_EL0); 887 + case SYS_DCZID_EL0: return read_cpuid(DCZID_EL0); 888 888 default: 889 889 BUG(); 890 890 return 0;
+26 -26
arch/arm64/kernel/cpuinfo.c
··· 203 203 { 204 204 info->reg_cntfrq = arch_timer_get_cntfrq(); 205 205 info->reg_ctr = read_cpuid_cachetype(); 206 - info->reg_dczid = read_cpuid(SYS_DCZID_EL0); 206 + info->reg_dczid = read_cpuid(DCZID_EL0); 207 207 info->reg_midr = read_cpuid_id(); 208 208 209 - info->reg_id_aa64dfr0 = read_cpuid(SYS_ID_AA64DFR0_EL1); 210 - info->reg_id_aa64dfr1 = read_cpuid(SYS_ID_AA64DFR1_EL1); 211 - info->reg_id_aa64isar0 = read_cpuid(SYS_ID_AA64ISAR0_EL1); 212 - info->reg_id_aa64isar1 = read_cpuid(SYS_ID_AA64ISAR1_EL1); 213 - info->reg_id_aa64mmfr0 = read_cpuid(SYS_ID_AA64MMFR0_EL1); 214 - info->reg_id_aa64mmfr1 = read_cpuid(SYS_ID_AA64MMFR1_EL1); 215 - info->reg_id_aa64mmfr2 = read_cpuid(SYS_ID_AA64MMFR2_EL1); 216 - info->reg_id_aa64pfr0 = read_cpuid(SYS_ID_AA64PFR0_EL1); 217 - info->reg_id_aa64pfr1 = read_cpuid(SYS_ID_AA64PFR1_EL1); 209 + info->reg_id_aa64dfr0 = read_cpuid(ID_AA64DFR0_EL1); 210 + info->reg_id_aa64dfr1 = read_cpuid(ID_AA64DFR1_EL1); 211 + info->reg_id_aa64isar0 = read_cpuid(ID_AA64ISAR0_EL1); 212 + info->reg_id_aa64isar1 = read_cpuid(ID_AA64ISAR1_EL1); 213 + info->reg_id_aa64mmfr0 = read_cpuid(ID_AA64MMFR0_EL1); 214 + info->reg_id_aa64mmfr1 = read_cpuid(ID_AA64MMFR1_EL1); 215 + info->reg_id_aa64mmfr2 = read_cpuid(ID_AA64MMFR2_EL1); 216 + info->reg_id_aa64pfr0 = read_cpuid(ID_AA64PFR0_EL1); 217 + info->reg_id_aa64pfr1 = read_cpuid(ID_AA64PFR1_EL1); 218 218 219 - info->reg_id_dfr0 = read_cpuid(SYS_ID_DFR0_EL1); 220 - info->reg_id_isar0 = read_cpuid(SYS_ID_ISAR0_EL1); 221 - info->reg_id_isar1 = read_cpuid(SYS_ID_ISAR1_EL1); 222 - info->reg_id_isar2 = read_cpuid(SYS_ID_ISAR2_EL1); 223 - info->reg_id_isar3 = read_cpuid(SYS_ID_ISAR3_EL1); 224 - info->reg_id_isar4 = read_cpuid(SYS_ID_ISAR4_EL1); 225 - info->reg_id_isar5 = read_cpuid(SYS_ID_ISAR5_EL1); 226 - info->reg_id_mmfr0 = read_cpuid(SYS_ID_MMFR0_EL1); 227 - info->reg_id_mmfr1 = read_cpuid(SYS_ID_MMFR1_EL1); 228 - info->reg_id_mmfr2 = read_cpuid(SYS_ID_MMFR2_EL1); 229 - info->reg_id_mmfr3 = read_cpuid(SYS_ID_MMFR3_EL1); 230 - info->reg_id_pfr0 = read_cpuid(SYS_ID_PFR0_EL1); 231 - info->reg_id_pfr1 = read_cpuid(SYS_ID_PFR1_EL1); 219 + info->reg_id_dfr0 = read_cpuid(ID_DFR0_EL1); 220 + info->reg_id_isar0 = read_cpuid(ID_ISAR0_EL1); 221 + info->reg_id_isar1 = read_cpuid(ID_ISAR1_EL1); 222 + info->reg_id_isar2 = read_cpuid(ID_ISAR2_EL1); 223 + info->reg_id_isar3 = read_cpuid(ID_ISAR3_EL1); 224 + info->reg_id_isar4 = read_cpuid(ID_ISAR4_EL1); 225 + info->reg_id_isar5 = read_cpuid(ID_ISAR5_EL1); 226 + info->reg_id_mmfr0 = read_cpuid(ID_MMFR0_EL1); 227 + info->reg_id_mmfr1 = read_cpuid(ID_MMFR1_EL1); 228 + info->reg_id_mmfr2 = read_cpuid(ID_MMFR2_EL1); 229 + info->reg_id_mmfr3 = read_cpuid(ID_MMFR3_EL1); 230 + info->reg_id_pfr0 = read_cpuid(ID_PFR0_EL1); 231 + info->reg_id_pfr1 = read_cpuid(ID_PFR1_EL1); 232 232 233 - info->reg_mvfr0 = read_cpuid(SYS_MVFR0_EL1); 234 - info->reg_mvfr1 = read_cpuid(SYS_MVFR1_EL1); 235 - info->reg_mvfr2 = read_cpuid(SYS_MVFR2_EL1); 233 + info->reg_mvfr0 = read_cpuid(MVFR0_EL1); 234 + info->reg_mvfr1 = read_cpuid(MVFR1_EL1); 235 + info->reg_mvfr2 = read_cpuid(MVFR2_EL1); 236 236 237 237 cpuinfo_detect_icache_policy(info); 238 238
+1 -1
arch/arm64/mm/context.c
··· 45 45 static u32 get_cpu_asid_bits(void) 46 46 { 47 47 u32 asid; 48 - int fld = cpuid_feature_extract_unsigned_field(read_cpuid(SYS_ID_AA64MMFR0_EL1), 48 + int fld = cpuid_feature_extract_unsigned_field(read_cpuid(ID_AA64MMFR0_EL1), 49 49 ID_AA64MMFR0_ASID_SHIFT); 50 50 51 51 switch (fld) {