tjh.dev / kernel
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ARM: tegra: Fixup pinmux node names

Pinmux node names should have a pinmux- prefix and not use underscores.
Fix up some cases that didn't follow those rules.

Signed-off-by: Thierry Reding <treding@nvidia.com>

Thierry Reding 1ca3b45e 06888f8b

+30 -30
+12 -12
arch/arm/boot/dts/tegra114-asus-tf701t.dts
··· 80 80 }; 81 81 82 82 pinmux@70000868 { 83 - asus_pad_ec_default: asus-pad-ec-default { 83 + asus_pad_ec_default: pinmux-asus-pad-ec-default { 84 84 ec-interrupt { 85 85 nvidia,pins = "kb_col5_pq5"; 86 86 nvidia,function = "kbc"; ··· 98 98 }; 99 99 }; 100 100 101 - backlight_default: backlight-default { 101 + backlight_default: pinmux-backlight-default { 102 102 backlight-enable { 103 103 nvidia,pins = "gmi_ad10_ph2"; 104 104 nvidia,function = "gmi"; ··· 108 108 }; 109 109 }; 110 110 111 - codec_default: codec-default { 111 + codec_default: pinmux-codec-default { 112 112 ldo1-en { 113 113 nvidia,pins = "sdmmc1_wp_n_pv3"; 114 114 nvidia,function = "sdmmc1"; ··· 127 127 }; 128 128 }; 129 129 130 - gpio_keys_default: gpio-keys-default { 130 + gpio_keys_default: pinmux-gpio-keys-default { 131 131 power { 132 132 nvidia,pins = "kb_col0_pq0"; 133 133 nvidia,function = "kbc"; ··· 146 146 }; 147 147 }; 148 148 149 - gpio_hall_sensor_default: gpio-hall-sensor-default { 149 + gpio_hall_sensor_default: pinmux-gpio-hall-sensor-default { 150 150 ulpi_data4_po5 { 151 151 nvidia,pins = "ulpi_data4_po5"; 152 152 nvidia,function = "spi2"; ··· 156 156 }; 157 157 }; 158 158 159 - hp_det_default: hp-det-default { 159 + hp_det_default: pinmux-hp-det-default { 160 160 gmi_iordy_pi5 { 161 161 nvidia,pins = "kb_row7_pr7"; 162 162 nvidia,function = "rsvd2"; ··· 166 166 }; 167 167 }; 168 168 169 - imu_default: imu-default { 169 + imu_default: pinmux-imu-default { 170 170 kb_row3_pr3 { 171 171 nvidia,pins = "kb_row3_pr3"; 172 172 nvidia,function = "rsvd3"; ··· 176 176 }; 177 177 }; 178 178 179 - pwm_default: pwm-default { 179 + pwm_default: pinmux-pwm-default { 180 180 gmi_ad9_ph1 { 181 181 nvidia,pins = "gmi_ad9_ph1"; 182 182 nvidia,function = "pwm1"; ··· 187 187 }; 188 188 189 189 /* XXX make this something more sensible */ 190 - pwm_sleep: pwm-sleep { 190 + pwm_sleep: pinmux-pwm-sleep { 191 191 gmi_ad9_ph1 { 192 192 nvidia,pins = "gmi_ad9_ph1"; 193 193 nvidia,function = "pwm1"; ··· 197 197 }; 198 198 }; 199 199 200 - sdmmc3_default: sdmmc3-default { 200 + sdmmc3_default: pinmux-sdmmc3-default { 201 201 sdmmc3_clk_pa6 { 202 202 nvidia,pins = "sdmmc3_clk_pa6"; 203 203 nvidia,function = "sdmmc3"; ··· 233 233 }; 234 234 }; 235 235 236 - sdmmc3_vdd_default: sdmmc3-vdd-default { 236 + sdmmc3_vdd_default: pinmux-sdmmc3-vdd-default { 237 237 gmi_clk_pk1 { 238 238 nvidia,pins = "gmi_clk_pk1"; 239 239 nvidia,function = "gmi"; ··· 243 243 }; 244 244 }; 245 245 246 - vdd_lcd_default: vdd-lcd-default { 246 + vdd_lcd_default: pinmux-vdd-lcd-default { 247 247 sdmmc4_clk_pcc4 { 248 248 nvidia,pins = "sdmmc4_clk_pcc4"; 249 249 nvidia,function = "sdmmc4";
+1 -1
arch/arm/boot/dts/tegra124-nyan-big.dts
··· 39 39 pinctrl-names = "default"; 40 40 pinctrl-0 = <&pinmux_default>; 41 41 42 - pinmux_default: common { 42 + pinmux_default: pinmux { 43 43 clk_32k_out_pa0 { 44 44 nvidia,pins = "clk_32k_out_pa0"; 45 45 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+1 -1
arch/arm/boot/dts/tegra124-nyan-blaze.dts
··· 37 37 pinctrl-names = "default"; 38 38 pinctrl-0 = <&pinmux_default>; 39 39 40 - pinmux_default: common { 40 + pinmux_default: pinmux { 41 41 clk_32k_out_pa0 { 42 42 nvidia,pins = "clk_32k_out_pa0"; 43 43 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+1 -1
arch/arm/boot/dts/tegra124-venice2.dts
··· 70 70 pinctrl-names = "boot"; 71 71 pinctrl-0 = <&pinmux_boot>; 72 72 73 - pinmux_boot: common { 73 + pinmux_boot: pinmux { 74 74 dap_mclk1_pw4 { 75 75 nvidia,pins = "dap_mclk1_pw4"; 76 76 nvidia,function = "extperiph1";
+3 -3
arch/arm/boot/dts/tegra20-acer-a500-picasso.dts
··· 342 342 }; 343 343 }; 344 344 345 - state_i2cmux_ddc: pinmux_i2cmux_ddc { 345 + state_i2cmux_ddc: pinmux-i2cmux-ddc { 346 346 ddc { 347 347 nvidia,pins = "ddc"; 348 348 nvidia,function = "i2c2"; ··· 353 353 }; 354 354 }; 355 355 356 - state_i2cmux_pta: pinmux_i2cmux_pta { 356 + state_i2cmux_pta: pinmux-i2cmux-pta { 357 357 ddc { 358 358 nvidia,pins = "ddc"; 359 359 nvidia,function = "rsvd4"; ··· 364 364 }; 365 365 }; 366 366 367 - state_i2cmux_idle: pinmux_i2cmux_idle { 367 + state_i2cmux_idle: pinmux-i2cmux-idle { 368 368 ddc { 369 369 nvidia,pins = "ddc"; 370 370 nvidia,function = "rsvd4";
+3 -3
arch/arm/boot/dts/tegra20-asus-tf101.dts
··· 399 399 }; 400 400 }; 401 401 402 - state_i2cmux_ddc: pinmux_i2cmux_ddc { 402 + state_i2cmux_ddc: pinmux-i2cmux-ddc { 403 403 ddc { 404 404 nvidia,pins = "ddc"; 405 405 nvidia,function = "i2c2"; ··· 411 411 }; 412 412 }; 413 413 414 - state_i2cmux_pta: pinmux_i2cmux_pta { 414 + state_i2cmux_pta: pinmux-i2cmux-pta { 415 415 ddc { 416 416 nvidia,pins = "ddc"; 417 417 nvidia,function = "rsvd4"; ··· 423 423 }; 424 424 }; 425 425 426 - state_i2cmux_idle: pinmux_i2cmux_idle { 426 + state_i2cmux_idle: pinmux-i2cmux-idle { 427 427 ddc { 428 428 nvidia,pins = "ddc"; 429 429 nvidia,function = "rsvd4";
+3 -3
arch/arm/boot/dts/tegra20-seaboard.dts
··· 285 285 }; 286 286 }; 287 287 288 - state_i2cmux_ddc: pinmux_i2cmux_ddc { 288 + state_i2cmux_ddc: pinmux-i2cmux-ddc { 289 289 ddc { 290 290 nvidia,pins = "ddc"; 291 291 nvidia,function = "i2c2"; ··· 296 296 }; 297 297 }; 298 298 299 - state_i2cmux_pta: pinmux_i2cmux_pta { 299 + state_i2cmux_pta: pinmux-i2cmux-pta { 300 300 ddc { 301 301 nvidia,pins = "ddc"; 302 302 nvidia,function = "rsvd4"; ··· 307 307 }; 308 308 }; 309 309 310 - state_i2cmux_idle: pinmux_i2cmux_idle { 310 + state_i2cmux_idle: pinmux-i2cmux-idle { 311 311 ddc { 312 312 nvidia,pins = "ddc"; 313 313 nvidia,function = "rsvd4";
+3 -3
arch/arm/boot/dts/tegra20-tamonten.dtsi
··· 249 249 }; 250 250 }; 251 251 252 - state_i2cmux_ddc: pinmux_i2cmux_ddc { 252 + state_i2cmux_ddc: pinmux-i2cmux-ddc { 253 253 ddc { 254 254 nvidia,pins = "ddc"; 255 255 nvidia,function = "i2c2"; ··· 260 260 }; 261 261 }; 262 262 263 - state_i2cmux_pta: pinmux_i2cmux_pta { 263 + state_i2cmux_pta: pinmux-i2cmux-pta { 264 264 ddc { 265 265 nvidia,pins = "ddc"; 266 266 nvidia,function = "rsvd4"; ··· 271 271 }; 272 272 }; 273 273 274 - state_i2cmux_idle: pinmux_i2cmux_idle { 274 + state_i2cmux_idle: pinmux-i2cmux-idle { 275 275 ddc { 276 276 nvidia,pins = "ddc"; 277 277 nvidia,function = "rsvd4";
+3 -3
arch/arm/boot/dts/tegra20-ventana.dts
··· 284 284 }; 285 285 }; 286 286 287 - state_i2cmux_ddc: pinmux_i2cmux_ddc { 287 + state_i2cmux_ddc: pinmux-i2cmux-ddc { 288 288 ddc { 289 289 nvidia,pins = "ddc"; 290 290 nvidia,function = "i2c2"; ··· 295 295 }; 296 296 }; 297 297 298 - state_i2cmux_pta: pinmux_i2cmux_pta { 298 + state_i2cmux_pta: pinmux-i2cmux-pta { 299 299 ddc { 300 300 nvidia,pins = "ddc"; 301 301 nvidia,function = "rsvd4"; ··· 306 306 }; 307 307 }; 308 308 309 - state_i2cmux_idle: pinmux_i2cmux_idle { 309 + state_i2cmux_idle: pinmux-i2cmux-idle { 310 310 ddc { 311 311 nvidia,pins = "ddc"; 312 312 nvidia,function = "rsvd4";