tjh.dev / kernel
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drm/panel: Support for Starry-himax83102-j02 TDDI MIPI-DSI panel

The Starry-himax83102-j02 is a 10.51" WUXGA TFT panel. which fits in nicely
with the existing panel-boe-tv101wum-nl6 driver. From the datasheet[1], MIPI
needs to keep the LP11 state before the lcm_reset pin is pulled high, so
increase lp11_before_reset flag.

[1]: https://github.com/HimaxSoftware/Doc/tree/main/Himax_Chipset_Power_Sequence

Signed-off-by: Cong Yang <yangcong5@huaqin.corp-partner.google.com>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
[dianders: removed some spacing on one line]
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Link: https://patchwork.freedesktop.org/patch/msgid/20230525093151.2338370-3-yangcong5@huaqin.corp-partner.google.com

authored by

Cong Yang and committed by
Douglas Anderson 1bc2ef06 06c3269c

+101
+101
drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c
··· 1301 1301 {}, 1302 1302 }; 1303 1303 1304 + static const struct panel_init_cmd starry_himax83102_j02_init_cmd[] = { 1305 + _INIT_DCS_CMD(0xB9, 0x83, 0x10, 0x21, 0x55, 0x00), 1306 + _INIT_DCS_CMD(0xB1, 0x2C, 0xB5, 0xB5, 0x31, 0xF1, 0x31, 0xD7, 0x2F, 0x36, 0x36, 0x36, 0x36, 0x1A, 0x8B, 0x11, 1307 + 0x65, 0x00, 0x88, 0xFA, 0xFF, 0xFF, 0x8F, 0xFF, 0x08, 0x74, 0x33), 1308 + _INIT_DCS_CMD(0xB2, 0x00, 0x47, 0xB0, 0x80, 0x00, 0x12, 0x72, 0x3C, 0xA3, 0x03, 0x03, 0x00, 0x00, 0x88, 0xF5), 1309 + _INIT_DCS_CMD(0xB4, 0x76, 0x76, 0x76, 0x76, 0x76, 0x76, 0x63, 0x5C, 0x63, 0x5C, 0x01, 0x9E), 1310 + _INIT_DCS_CMD(0xE9, 0xCD), 1311 + _INIT_DCS_CMD(0xBA, 0x84), 1312 + _INIT_DCS_CMD(0xE9, 0x3F), 1313 + _INIT_DCS_CMD(0xBC, 0x1B, 0x04), 1314 + _INIT_DCS_CMD(0xBE, 0x20), 1315 + _INIT_DCS_CMD(0xBF, 0xFC, 0xC4), 1316 + _INIT_DCS_CMD(0xC0, 0x36, 0x36, 0x22, 0x11, 0x22, 0xA0, 0x61, 0x08, 0xF5, 0x03), 1317 + _INIT_DCS_CMD(0xE9, 0xCC), 1318 + _INIT_DCS_CMD(0xC7, 0x80), 1319 + _INIT_DCS_CMD(0xE9, 0x3F), 1320 + _INIT_DCS_CMD(0xE9, 0xC6), 1321 + _INIT_DCS_CMD(0xC8, 0x97), 1322 + _INIT_DCS_CMD(0xE9, 0x3F), 1323 + _INIT_DCS_CMD(0xC9, 0x00, 0x1E, 0x13, 0x88, 0x01), 1324 + _INIT_DCS_CMD(0xCB, 0x08, 0x13, 0x07, 0x00, 0x0F, 0x33), 1325 + _INIT_DCS_CMD(0xCC, 0x02), 1326 + _INIT_DCS_CMD(0xE9, 0xC4), 1327 + _INIT_DCS_CMD(0xD0, 0x03), 1328 + _INIT_DCS_CMD(0xE9, 0x3F), 1329 + _INIT_DCS_CMD(0xD1, 0x37, 0x06, 0x00, 0x02, 0x04, 0x0C, 0xFF), 1330 + _INIT_DCS_CMD(0xD2, 0x1F, 0x11, 0x1F), 1331 + _INIT_DCS_CMD(0xD3, 0x06, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x08, 0x37, 0x47, 0x34, 0x3B, 0x12, 0x12, 0x03, 1332 + 0x03, 0x32, 0x10, 0x10, 0x00, 0x10, 0x32, 0x10, 0x08, 0x00, 0x08, 0x32, 0x17, 0x94, 0x07, 0x94, 0x00, 0x00), 1333 + _INIT_DCS_CMD(0xD5, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x19, 0x19, 0x40, 0x40, 0x1A, 0x1A, 1334 + 0x1B, 0x1B, 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x20, 0x21, 0x28, 0x29, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18), 1335 + _INIT_DCS_CMD(0xD6, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x40, 0x40, 0x19, 0x19, 0x1A, 0x1A, 1336 + 0x1B, 0x1B, 0x07, 0x06, 0x05, 0x04, 0x03, 0x02, 0x01, 0x00, 0x29, 0x28, 0x21, 0x20, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18), 1337 + _INIT_DCS_CMD(0xD8, 0xAA, 0xBA, 0xEA, 0xAA, 0xAA, 0xA0, 0xAA, 0xBA, 0xEA, 0xAA, 0xAA, 0xA0, 0xAA, 0xBA, 0xEA, 0xAA, 1338 + 0xAA, 0xA0, 0xAA, 0xBA, 0xEA, 0xAA, 0xAA, 0xA0, 0xAA, 0xBA, 0xEA, 0xAA, 0xAA, 0xA0, 0xAA, 0xBA, 0xEA, 0xAA, 0xAA, 0xA0), 1339 + _INIT_DCS_CMD(0xE0, 0x00, 0x09, 0x14, 0x1E, 0x26, 0x48, 0x61, 0x67, 0x6C, 0x67, 0x7D, 0x7F, 0x80, 0x8B, 0x87, 0x8F, 0x98, 0xAB, 1340 + 0xAB, 0x55, 0x5C, 0x68, 0x73, 0x00, 0x09, 0x14, 0x1E, 0x26, 0x48, 0x61, 0x67, 0x6C, 0x67, 0x7D, 0x7F, 0x80, 0x8B, 0x87, 0x8F, 0x98, 0xAB, 0xAB, 0x55, 0x5C, 0x68, 0x73), 1341 + _INIT_DCS_CMD(0xE7, 0x0E, 0x10, 0x10, 0x21, 0x2B, 0x9A, 0x02, 0x54, 0x9A, 0x14, 0x14, 0x00, 0x00, 0x00, 0x00, 0x12, 0x05, 0x02, 0x02, 0x10), 1342 + _INIT_DCS_CMD(0xBD, 0x01), 1343 + _INIT_DCS_CMD(0xB1, 0x01, 0xBF, 0x11), 1344 + _INIT_DCS_CMD(0xCB, 0x86), 1345 + _INIT_DCS_CMD(0xD2, 0x3C, 0xFA), 1346 + _INIT_DCS_CMD(0xE9, 0xC5), 1347 + _INIT_DCS_CMD(0xD3, 0x00, 0x00, 0x00, 0x00, 0x80, 0x0C, 0x01), 1348 + _INIT_DCS_CMD(0xE9, 0x3F), 1349 + _INIT_DCS_CMD(0xE7, 0x02, 0x00, 0x28, 0x01, 0x7E, 0x0F, 0x7E, 0x10, 0xA0, 0x00, 0x00, 0x20, 0x40, 0x50, 0x40), 1350 + _INIT_DCS_CMD(0xBD, 0x02), 1351 + _INIT_DCS_CMD(0xD8, 0xFF, 0xFF, 0xBF, 0xFE, 0xAA, 0xA0, 0xFF, 0xFF, 0xBF, 0xFE, 0xAA, 0xA0), 1352 + _INIT_DCS_CMD(0xE7, 0xFE, 0x04, 0xFE, 0x04, 0xFE, 0x04, 0x03, 0x03, 0x03, 0x26, 0x00, 0x26, 0x81, 0x02, 0x40, 0x00, 0x20, 0x9E, 0x04, 0x03, 0x02, 0x01, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00), 1353 + _INIT_DCS_CMD(0xBD, 0x03), 1354 + _INIT_DCS_CMD(0xE9, 0xC6), 1355 + _INIT_DCS_CMD(0xB4, 0x03, 0xFF, 0xF8), 1356 + _INIT_DCS_CMD(0xE9, 0x3F), 1357 + _INIT_DCS_CMD(0xD8, 0x00, 0x2A, 0xAA, 0xA8, 0x00, 0x00, 0x00, 0x2A, 0xAA, 0xA8, 0x00, 0x00, 0x00, 0x3F, 0xFF, 0xFC, 0x00, 0x00, 0x00, 0x3F, 0xFF, 0xFC, 0x00, 0x00, 0x00, 0x2A, 0xAA, 0xA8, 1358 + 0x00, 0x00, 0x00, 0x2A, 0xAA, 0xA8, 0x00, 0x00), 1359 + _INIT_DCS_CMD(0xBD, 0x00), 1360 + _INIT_DCS_CMD(0xE9, 0xC4), 1361 + _INIT_DCS_CMD(0xBA, 0x96), 1362 + _INIT_DCS_CMD(0xE9, 0x3F), 1363 + _INIT_DCS_CMD(0xBD, 0x01), 1364 + _INIT_DCS_CMD(0xE9, 0xC5), 1365 + _INIT_DCS_CMD(0xBA, 0x4F), 1366 + _INIT_DCS_CMD(0xE9, 0x3F), 1367 + _INIT_DCS_CMD(0xBD, 0x00), 1368 + _INIT_DCS_CMD(0x11), 1369 + _INIT_DELAY_CMD(120), 1370 + _INIT_DCS_CMD(0x29), 1371 + {}, 1372 + }; 1373 + 1304 1374 static inline struct boe_panel *to_boe_panel(struct drm_panel *panel) 1305 1375 { 1306 1376 return container_of(panel, struct boe_panel, base); ··· 1768 1698 .init_cmds = starry_qfh032011_53g_init_cmd, 1769 1699 }; 1770 1700 1701 + static const struct drm_display_mode starry_himax83102_j02_default_mode = { 1702 + .clock = 161600, 1703 + .hdisplay = 1200, 1704 + .hsync_start = 1200 + 40, 1705 + .hsync_end = 1200 + 40 + 20, 1706 + .htotal = 1200 + 40 + 20 + 40, 1707 + .vdisplay = 1920, 1708 + .vsync_start = 1920 + 116, 1709 + .vsync_end = 1920 + 116 + 8, 1710 + .vtotal = 1920 + 116 + 8 + 12, 1711 + .type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED, 1712 + }; 1713 + 1714 + static const struct panel_desc starry_himax83102_j02_desc = { 1715 + .modes = &starry_himax83102_j02_default_mode, 1716 + .bpc = 8, 1717 + .size = { 1718 + .width_mm = 141, 1719 + .height_mm = 226, 1720 + }, 1721 + .lanes = 4, 1722 + .format = MIPI_DSI_FMT_RGB888, 1723 + .mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE | 1724 + MIPI_DSI_MODE_LPM, 1725 + .init_cmds = starry_himax83102_j02_init_cmd, 1726 + .lp11_before_reset = true, 1727 + }; 1728 + 1771 1729 static int boe_panel_get_modes(struct drm_panel *panel, 1772 1730 struct drm_connector *connector) 1773 1731 { ··· 1968 1870 }, 1969 1871 { .compatible = "starry,2081101qfh032011-53g", 1970 1872 .data = &starry_qfh032011_53g_desc 1873 + }, 1874 + { .compatible = "starry,himax83102-j02", 1875 + .data = &starry_himax83102_j02_desc 1971 1876 }, 1972 1877 { /* sentinel */ } 1973 1878 };