···352352 reg32 &= ~ROOT_PORT_INTR_ON_MESG_MASK;353353 pci_write_config_dword(dev, pos + PCI_ERR_ROOT_COMMAND, reg32);354354355355- aer_do_secondary_bus_reset(dev);355355+ pci_reset_bridge_secondary_bus(dev);356356 dev_printk(KERN_DEBUG, &dev->dev, "Root Port link has been reset\n");357357358358 /* Clear Root Error Status */
···367367}368368369369/**370370- * aer_do_secondary_bus_reset - perform secondary bus reset371371- * @dev: pointer to bridge's pci_dev data structure372372- *373373- * Invoked when performing link reset at Root Port or Downstream Port.374374- */375375-void aer_do_secondary_bus_reset(struct pci_dev *dev)376376-{377377- u16 p2p_ctrl;378378-379379- /* Assert Secondary Bus Reset */380380- pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &p2p_ctrl);381381- p2p_ctrl |= PCI_BRIDGE_CTL_BUS_RESET;382382- pci_write_config_word(dev, PCI_BRIDGE_CONTROL, p2p_ctrl);383383-384384- /*385385- * we should send hot reset message for 2ms to allow it time to386386- * propagate to all downstream ports387387- */388388- msleep(2);389389-390390- /* De-assert Secondary Bus Reset */391391- p2p_ctrl &= ~PCI_BRIDGE_CTL_BUS_RESET;392392- pci_write_config_word(dev, PCI_BRIDGE_CONTROL, p2p_ctrl);393393-394394- /*395395- * System software must wait for at least 100ms from the end396396- * of a reset of one or more device before it is permitted397397- * to issue Configuration Requests to those devices.398398- */399399- msleep(200);400400-}401401-402402-/**403370 * default_reset_link - default reset function404371 * @dev: pointer to pci_dev data structure405372 *···375408 */376409static pci_ers_result_t default_reset_link(struct pci_dev *dev)377410{378378- aer_do_secondary_bus_reset(dev);411411+ pci_reset_bridge_secondary_bus(dev);379412 dev_printk(KERN_DEBUG, &dev->dev, "downstream link has been reset\n");380413 return PCI_ERS_RESULT_RECOVERED;381414}