tjh.dev
+13
arch/powerpc/kernel/fpu.S
+13
arch/powerpc/kernel/fpu.S
···
23
23
#include <asm/feature-fixups.h>
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#ifdef CONFIG_VSX
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+
#define __REST_1FPVSR(n,c,base) \
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+
BEGIN_FTR_SECTION \
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b 2f; \
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END_FTR_SECTION_IFSET(CPU_FTR_VSX); \
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REST_FPR(n,base); \
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b 3f; \
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2: REST_VSR(n,c,base); \
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3:
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+
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#define __REST_32FPVSRS(n,c,base) \
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BEGIN_FTR_SECTION \
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b 2f; \
···
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2: SAVE_32VSRS(n,c,base); \
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3:
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#else
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#define __REST_1FPVSR(n,b,base) REST_FPR(n, base)
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#define __REST_32FPVSRS(n,b,base) REST_32FPRS(n, base)
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#define __SAVE_32FPVSRS(n,b,base) SAVE_32FPRS(n, base)
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#endif
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#define REST_1FPVSR(n,c,base) __REST_1FPVSR(n,__REG_##c,__REG_##base)
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#define REST_32FPVSRS(n,c,base) __REST_32FPVSRS(n,__REG_##c,__REG_##base)
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#define SAVE_32FPVSRS(n,c,base) __SAVE_32FPVSRS(n,__REG_##c,__REG_##base)
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51
···
78
67
SAVE_32FPVSRS(0, R4, R3)
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mffs fr0
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stfd fr0,FPSTATE_FPSCR(r3)
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REST_1FPVSR(0, R4, R3)
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blr
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EXPORT_SYMBOL(store_fp_state)
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···
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2: SAVE_32FPVSRS(0, R4, R6)
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mffs fr0
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stfd fr0,FPSTATE_FPSCR(r6)
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+
REST_1FPVSR(0, R4, R6)
153
142
blr
+3
-3
arch/powerpc/kernel/process.c
+3
-3
arch/powerpc/kernel/process.c
···
1198
1198
1199
1199
usermsr = current->thread.regs->msr;
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+
/* Caller has enabled FP/VEC/VSX/TM in MSR */
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if (usermsr & MSR_FP)
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-
save_fpu(current);
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-
1203
+
__giveup_fpu(current);
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if (usermsr & MSR_VEC)
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-
save_altivec(current);
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+
__giveup_altivec(current);
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#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
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if (usermsr & MSR_TM) {
+2
arch/powerpc/kernel/vector.S
+2
arch/powerpc/kernel/vector.S