Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux

mfd: asic3: remove SD/SDIO controller register definitions

Only the base addresses remain, as they are needed to set up
the IOMEM resources.

Signed-off-by: Philipp Zabel <philipp.zabel@gmail.com>
Signed-off-by: Samuel Ortiz <sameo@linux.intel.com>

authored by

Philipp Zabel and committed by
Samuel Ortiz
1b89040c be584bd5

+3 -216
+3 -216
include/linux/mfd/asic3.h
··· 286 286 * SDIO_CTRL Control registers for SDIO operations 287 287 * 288 288 *****************************************************************************/ 289 - #define ASIC3_SD_CONFIG_Base 0x0400 /* Assumes 32 bit addressing */ 290 - 291 - #define ASIC3_SD_CONFIG_Command 0x08 /* R/W: Command */ 292 - 293 - /* [0:8] SD Control Register Base Address */ 294 - #define ASIC3_SD_CONFIG_Addr0 0x20 295 - 296 - /* [9:31] SD Control Register Base Address */ 297 - #define ASIC3_SD_CONFIG_Addr1 0x24 298 - 299 - /* R/O: interrupt assigned to pin */ 300 - #define ASIC3_SD_CONFIG_IntPin 0x78 301 - 302 - /* 303 - * Set to 0x1f to clock SD controller, 0 otherwise. 304 - * At 0x82 - Gated Clock Ctrl 305 - */ 306 - #define ASIC3_SD_CONFIG_ClkStop 0x80 307 - 308 - /* Control clock of SD controller */ 309 - #define ASIC3_SD_CONFIG_ClockMode 0x84 310 - #define ASIC3_SD_CONFIG_SDHC_PinStatus 0x88 /* R/0: SD pins status */ 311 - #define ASIC3_SD_CONFIG_SDHC_Power1 0x90 /* Power1 - manual pwr ctrl */ 312 - 313 - /* auto power up after card inserted */ 314 - #define ASIC3_SD_CONFIG_SDHC_Power2 0x92 315 - 316 - /* auto power down when card removed */ 317 - #define ASIC3_SD_CONFIG_SDHC_Power3 0x94 318 - #define ASIC3_SD_CONFIG_SDHC_CardDetect 0x98 319 - #define ASIC3_SD_CONFIG_SDHC_Slot 0xA0 /* R/O: support slot number */ 320 - #define ASIC3_SD_CONFIG_SDHC_ExtGateClk1 0x1E0 /* Not used */ 321 - #define ASIC3_SD_CONFIG_SDHC_ExtGateClk2 0x1E2 /* Not used*/ 322 - 323 - /* GPIO Output Reg. , at 0x1EA - GPIO Output Enable Reg. */ 324 - #define ASIC3_SD_CONFIG_SDHC_GPIO_OutAndEnable 0x1E8 325 - #define ASIC3_SD_CONFIG_SDHC_GPIO_Status 0x1EC /* GPIO Status Reg. */ 326 - 327 - /* Bit 1: double buffer/single buffer */ 328 - #define ASIC3_SD_CONFIG_SDHC_ExtGateClk3 0x1F0 329 - 330 - /* Memory access enable (set to 1 to access SD Controller) */ 331 - #define SD_CONFIG_COMMAND_MAE (1<<1) 332 - 333 - #define SD_CONFIG_CLK_ENABLE_ALL 0x1f 334 - 335 - #define SD_CONFIG_POWER1_PC_33V 0x0200 /* Set for 3.3 volts */ 336 - #define SD_CONFIG_POWER1_PC_OFF 0x0000 /* Turn off power */ 337 - 338 - /* two bits - number of cycles for card detection */ 339 - #define SD_CONFIG_CARDDETECTMODE_CLK ((x) & 0x3) 340 - 341 - 342 - #define ASIC3_SD_CTRL_Base 0x1000 343 - 344 - #define ASIC3_SD_CTRL_Cmd 0x00 345 - #define ASIC3_SD_CTRL_Arg0 0x08 346 - #define ASIC3_SD_CTRL_Arg1 0x0C 347 - #define ASIC3_SD_CTRL_StopInternal 0x10 348 - #define ASIC3_SD_CTRL_TransferSectorCount 0x14 349 - #define ASIC3_SD_CTRL_Response0 0x18 350 - #define ASIC3_SD_CTRL_Response1 0x1C 351 - #define ASIC3_SD_CTRL_Response2 0x20 352 - #define ASIC3_SD_CTRL_Response3 0x24 353 - #define ASIC3_SD_CTRL_Response4 0x28 354 - #define ASIC3_SD_CTRL_Response5 0x2C 355 - #define ASIC3_SD_CTRL_Response6 0x30 356 - #define ASIC3_SD_CTRL_Response7 0x34 357 - #define ASIC3_SD_CTRL_CardStatus 0x38 358 - #define ASIC3_SD_CTRL_BufferCtrl 0x3C 359 - #define ASIC3_SD_CTRL_IntMaskCard 0x40 360 - #define ASIC3_SD_CTRL_IntMaskBuffer 0x44 361 - #define ASIC3_SD_CTRL_CardClockCtrl 0x48 362 - #define ASIC3_SD_CTRL_MemCardXferDataLen 0x4C 363 - #define ASIC3_SD_CTRL_MemCardOptionSetup 0x50 364 - #define ASIC3_SD_CTRL_ErrorStatus0 0x58 365 - #define ASIC3_SD_CTRL_ErrorStatus1 0x5C 366 - #define ASIC3_SD_CTRL_DataPort 0x60 367 - #define ASIC3_SD_CTRL_TransactionCtrl 0x68 368 - #define ASIC3_SD_CTRL_SoftwareReset 0x1C0 369 - 370 - #define SD_CTRL_SOFTWARE_RESET_CLEAR (1<<0) 371 - 372 - #define SD_CTRL_TRANSACTIONCONTROL_SET (1<<8) 373 - 374 - #define SD_CTRL_CARDCLOCKCONTROL_FOR_SD_CARD (1<<15) 375 - #define SD_CTRL_CARDCLOCKCONTROL_ENABLE_CLOCK (1<<8) 376 - #define SD_CTRL_CARDCLOCKCONTROL_CLK_DIV_512 (1<<7) 377 - #define SD_CTRL_CARDCLOCKCONTROL_CLK_DIV_256 (1<<6) 378 - #define SD_CTRL_CARDCLOCKCONTROL_CLK_DIV_128 (1<<5) 379 - #define SD_CTRL_CARDCLOCKCONTROL_CLK_DIV_64 (1<<4) 380 - #define SD_CTRL_CARDCLOCKCONTROL_CLK_DIV_32 (1<<3) 381 - #define SD_CTRL_CARDCLOCKCONTROL_CLK_DIV_16 (1<<2) 382 - #define SD_CTRL_CARDCLOCKCONTROL_CLK_DIV_8 (1<<1) 383 - #define SD_CTRL_CARDCLOCKCONTROL_CLK_DIV_4 (1<<0) 384 - #define SD_CTRL_CARDCLOCKCONTROL_CLK_DIV_2 (0<<0) 385 - 386 - #define MEM_CARD_OPTION_REQUIRED 0x000e 387 - #define MEM_CARD_OPTION_DATA_RESPONSE_TIMEOUT(x) (((x) & 0x0f) << 4) 388 - #define MEM_CARD_OPTION_C2_MODULE_NOT_PRESENT (1<<14) 389 - #define MEM_CARD_OPTION_DATA_XFR_WIDTH_1 (1<<15) 390 - #define MEM_CARD_OPTION_DATA_XFR_WIDTH_4 0 391 - 392 - #define SD_CTRL_COMMAND_INDEX(x) ((x) & 0x3f) 393 - #define SD_CTRL_COMMAND_TYPE_CMD (0 << 6) 394 - #define SD_CTRL_COMMAND_TYPE_ACMD (1 << 6) 395 - #define SD_CTRL_COMMAND_TYPE_AUTHENTICATION (2 << 6) 396 - #define SD_CTRL_COMMAND_RESPONSE_TYPE_NORMAL (0 << 8) 397 - #define SD_CTRL_COMMAND_RESPONSE_TYPE_EXT_R1 (4 << 8) 398 - #define SD_CTRL_COMMAND_RESPONSE_TYPE_EXT_R1B (5 << 8) 399 - #define SD_CTRL_COMMAND_RESPONSE_TYPE_EXT_R2 (6 << 8) 400 - #define SD_CTRL_COMMAND_RESPONSE_TYPE_EXT_R3 (7 << 8) 401 - #define SD_CTRL_COMMAND_DATA_PRESENT (1 << 11) 402 - #define SD_CTRL_COMMAND_TRANSFER_READ (1 << 12) 403 - #define SD_CTRL_COMMAND_TRANSFER_WRITE (0 << 12) 404 - #define SD_CTRL_COMMAND_MULTI_BLOCK (1 << 13) 405 - #define SD_CTRL_COMMAND_SECURITY_CMD (1 << 14) 406 - 407 - #define SD_CTRL_STOP_INTERNAL_ISSSUE_CMD12 (1 << 0) 408 - #define SD_CTRL_STOP_INTERNAL_AUTO_ISSUE_CMD12 (1 << 8) 409 - 410 - #define SD_CTRL_CARDSTATUS_RESPONSE_END (1 << 0) 411 - #define SD_CTRL_CARDSTATUS_RW_END (1 << 2) 412 - #define SD_CTRL_CARDSTATUS_CARD_REMOVED_0 (1 << 3) 413 - #define SD_CTRL_CARDSTATUS_CARD_INSERTED_0 (1 << 4) 414 - #define SD_CTRL_CARDSTATUS_SIGNAL_STATE_PRESENT_0 (1 << 5) 415 - #define SD_CTRL_CARDSTATUS_WRITE_PROTECT (1 << 7) 416 - #define SD_CTRL_CARDSTATUS_CARD_REMOVED_3 (1 << 8) 417 - #define SD_CTRL_CARDSTATUS_CARD_INSERTED_3 (1 << 9) 418 - #define SD_CTRL_CARDSTATUS_SIGNAL_STATE_PRESENT_3 (1 << 10) 419 - 420 - #define SD_CTRL_BUFFERSTATUS_CMD_INDEX_ERROR (1 << 0) 421 - #define SD_CTRL_BUFFERSTATUS_CRC_ERROR (1 << 1) 422 - #define SD_CTRL_BUFFERSTATUS_STOP_BIT_END_ERROR (1 << 2) 423 - #define SD_CTRL_BUFFERSTATUS_DATA_TIMEOUT (1 << 3) 424 - #define SD_CTRL_BUFFERSTATUS_BUFFER_OVERFLOW (1 << 4) 425 - #define SD_CTRL_BUFFERSTATUS_BUFFER_UNDERFLOW (1 << 5) 426 - #define SD_CTRL_BUFFERSTATUS_CMD_TIMEOUT (1 << 6) 427 - #define SD_CTRL_BUFFERSTATUS_UNK7 (1 << 7) 428 - #define SD_CTRL_BUFFERSTATUS_BUFFER_READ_ENABLE (1 << 8) 429 - #define SD_CTRL_BUFFERSTATUS_BUFFER_WRITE_ENABLE (1 << 9) 430 - #define SD_CTRL_BUFFERSTATUS_ILLEGAL_FUNCTION (1 << 13) 431 - #define SD_CTRL_BUFFERSTATUS_CMD_BUSY (1 << 14) 432 - #define SD_CTRL_BUFFERSTATUS_ILLEGAL_ACCESS (1 << 15) 433 - 434 - #define SD_CTRL_INTMASKCARD_RESPONSE_END (1 << 0) 435 - #define SD_CTRL_INTMASKCARD_RW_END (1 << 2) 436 - #define SD_CTRL_INTMASKCARD_CARD_REMOVED_0 (1 << 3) 437 - #define SD_CTRL_INTMASKCARD_CARD_INSERTED_0 (1 << 4) 438 - #define SD_CTRL_INTMASKCARD_SIGNAL_STATE_PRESENT_0 (1 << 5) 439 - #define SD_CTRL_INTMASKCARD_UNK6 (1 << 6) 440 - #define SD_CTRL_INTMASKCARD_WRITE_PROTECT (1 << 7) 441 - #define SD_CTRL_INTMASKCARD_CARD_REMOVED_3 (1 << 8) 442 - #define SD_CTRL_INTMASKCARD_CARD_INSERTED_3 (1 << 9) 443 - #define SD_CTRL_INTMASKCARD_SIGNAL_STATE_PRESENT_3 (1 << 10) 444 - 445 - #define SD_CTRL_INTMASKBUFFER_CMD_INDEX_ERROR (1 << 0) 446 - #define SD_CTRL_INTMASKBUFFER_CRC_ERROR (1 << 1) 447 - #define SD_CTRL_INTMASKBUFFER_STOP_BIT_END_ERROR (1 << 2) 448 - #define SD_CTRL_INTMASKBUFFER_DATA_TIMEOUT (1 << 3) 449 - #define SD_CTRL_INTMASKBUFFER_BUFFER_OVERFLOW (1 << 4) 450 - #define SD_CTRL_INTMASKBUFFER_BUFFER_UNDERFLOW (1 << 5) 451 - #define SD_CTRL_INTMASKBUFFER_CMD_TIMEOUT (1 << 6) 452 - #define SD_CTRL_INTMASKBUFFER_UNK7 (1 << 7) 453 - #define SD_CTRL_INTMASKBUFFER_BUFFER_READ_ENABLE (1 << 8) 454 - #define SD_CTRL_INTMASKBUFFER_BUFFER_WRITE_ENABLE (1 << 9) 455 - #define SD_CTRL_INTMASKBUFFER_ILLEGAL_FUNCTION (1 << 13) 456 - #define SD_CTRL_INTMASKBUFFER_CMD_BUSY (1 << 14) 457 - #define SD_CTRL_INTMASKBUFFER_ILLEGAL_ACCESS (1 << 15) 458 - 459 - #define SD_CTRL_DETAIL0_RESPONSE_CMD_ERROR (1 << 0) 460 - #define SD_CTRL_DETAIL0_END_BIT_ERROR_FOR_RESPONSE_NON_CMD12 (1 << 2) 461 - #define SD_CTRL_DETAIL0_END_BIT_ERROR_FOR_RESPONSE_CMD12 (1 << 3) 462 - #define SD_CTRL_DETAIL0_END_BIT_ERROR_FOR_READ_DATA (1 << 4) 463 - #define SD_CTRL_DETAIL0_END_BIT_ERROR_FOR_WRITE_CRC_STATUS (1 << 5) 464 - #define SD_CTRL_DETAIL0_CRC_ERROR_FOR_RESPONSE_NON_CMD12 (1 << 8) 465 - #define SD_CTRL_DETAIL0_CRC_ERROR_FOR_RESPONSE_CMD12 (1 << 9) 466 - #define SD_CTRL_DETAIL0_CRC_ERROR_FOR_READ_DATA (1 << 10) 467 - #define SD_CTRL_DETAIL0_CRC_ERROR_FOR_WRITE_CMD (1 << 11) 468 - 469 - #define SD_CTRL_DETAIL1_NO_CMD_RESPONSE (1 << 0) 470 - #define SD_CTRL_DETAIL1_TIMEOUT_READ_DATA (1 << 4) 471 - #define SD_CTRL_DETAIL1_TIMEOUT_CRS_STATUS (1 << 5) 472 - #define SD_CTRL_DETAIL1_TIMEOUT_CRC_BUSY (1 << 6) 473 - 474 - #define ASIC3_SDIO_CTRL_Base 0x1200 475 - 476 - #define ASIC3_SDIO_CTRL_Cmd 0x00 477 - #define ASIC3_SDIO_CTRL_CardPortSel 0x04 478 - #define ASIC3_SDIO_CTRL_Arg0 0x08 479 - #define ASIC3_SDIO_CTRL_Arg1 0x0C 480 - #define ASIC3_SDIO_CTRL_TransferBlockCount 0x14 481 - #define ASIC3_SDIO_CTRL_Response0 0x18 482 - #define ASIC3_SDIO_CTRL_Response1 0x1C 483 - #define ASIC3_SDIO_CTRL_Response2 0x20 484 - #define ASIC3_SDIO_CTRL_Response3 0x24 485 - #define ASIC3_SDIO_CTRL_Response4 0x28 486 - #define ASIC3_SDIO_CTRL_Response5 0x2C 487 - #define ASIC3_SDIO_CTRL_Response6 0x30 488 - #define ASIC3_SDIO_CTRL_Response7 0x34 489 - #define ASIC3_SDIO_CTRL_CardStatus 0x38 490 - #define ASIC3_SDIO_CTRL_BufferCtrl 0x3C 491 - #define ASIC3_SDIO_CTRL_IntMaskCard 0x40 492 - #define ASIC3_SDIO_CTRL_IntMaskBuffer 0x44 493 - #define ASIC3_SDIO_CTRL_CardXferDataLen 0x4C 494 - #define ASIC3_SDIO_CTRL_CardOptionSetup 0x50 495 - #define ASIC3_SDIO_CTRL_ErrorStatus0 0x54 496 - #define ASIC3_SDIO_CTRL_ErrorStatus1 0x58 497 - #define ASIC3_SDIO_CTRL_DataPort 0x60 498 - #define ASIC3_SDIO_CTRL_TransactionCtrl 0x68 499 - #define ASIC3_SDIO_CTRL_CardIntCtrl 0x6C 500 - #define ASIC3_SDIO_CTRL_ClocknWaitCtrl 0x70 501 - #define ASIC3_SDIO_CTRL_HostInformation 0x74 502 - #define ASIC3_SDIO_CTRL_ErrorCtrl 0x78 503 - #define ASIC3_SDIO_CTRL_LEDCtrl 0x7C 504 - #define ASIC3_SDIO_CTRL_SoftwareReset 0x1C0 289 + #define ASIC3_SD_CONFIG_BASE 0x0400 /* Assumes 32 bit addressing */ 290 + #define ASIC3_SD_CTRL_BASE 0x1000 291 + #define ASIC3_SDIO_CTRL_BASE 0x1200 505 292 506 293 #define ASIC3_MAP_SIZE_32BIT 0x2000 507 294 #define ASIC3_MAP_SIZE_16BIT 0x1000