Merge branch 'bnxt_en-driver-updates' · tjh.dev/kernel@1b3d6ec

+1

drivers/net/ethernet/broadcom/bnxt/bnxt.h

··· 2116 2116 #define BNXT_PHY_FL_NO_FCS PORT_PHY_QCAPS_RESP_FLAGS_NO_FCS 2117 2117 #define BNXT_PHY_FL_NO_PAUSE (PORT_PHY_QCAPS_RESP_FLAGS2_PAUSE_UNSUPPORTED << 8) 2118 2118 #define BNXT_PHY_FL_NO_PFC (PORT_PHY_QCAPS_RESP_FLAGS2_PFC_UNSUPPORTED << 8) 2119 + #define BNXT_PHY_FL_BANK_SEL (PORT_PHY_QCAPS_RESP_FLAGS2_BANK_ADDR_SUPPORTED << 8) 2119 2120 2120 2121 u8 num_tests; 2121 2122 struct bnxt_test_info *test_info;

+102 -7

drivers/net/ethernet/broadcom/bnxt/bnxt_ethtool.c

··· 2514 2514 #define MSG_INTERNAL_ERR "PKG install error : Internal error" 2515 2515 #define MSG_NO_PKG_UPDATE_AREA_ERR "PKG update area not created in nvram" 2516 2516 #define MSG_NO_SPACE_ERR "PKG insufficient update area in nvram" 2517 + #define MSG_RESIZE_UPDATE_ERR "Resize UPDATE entry error" 2517 2518 #define MSG_ANTI_ROLLBACK_ERR "HWRM_NVM_INSTALL_UPDATE failure due to Anti-rollback detected" 2518 2519 #define MSG_GENERIC_FAILURE_ERR "HWRM_NVM_INSTALL_UPDATE failure" 2519 2520 ··· 2565 2564 #define BNXT_NVM_MORE_FLAG (cpu_to_le16(NVM_MODIFY_REQ_FLAGS_BATCH_MODE)) 2566 2565 #define BNXT_NVM_LAST_FLAG (cpu_to_le16(NVM_MODIFY_REQ_FLAGS_BATCH_LAST)) 2567 2566 2567 + static int bnxt_resize_update_entry(struct net_device *dev, size_t fw_size, 2568 + struct netlink_ext_ack *extack) 2569 + { 2570 + u32 item_len; 2571 + int rc; 2572 + 2573 + rc = bnxt_find_nvram_item(dev, BNX_DIR_TYPE_UPDATE, 2574 + BNX_DIR_ORDINAL_FIRST, BNX_DIR_EXT_NONE, NULL, 2575 + &item_len, NULL); 2576 + if (rc) { 2577 + BNXT_NVM_ERR_MSG(dev, extack, MSG_NO_PKG_UPDATE_AREA_ERR); 2578 + return rc; 2579 + } 2580 + 2581 + if (fw_size > item_len) { 2582 + rc = bnxt_flash_nvram(dev, BNX_DIR_TYPE_UPDATE, 2583 + BNX_DIR_ORDINAL_FIRST, 0, 1, 2584 + round_up(fw_size, 4096), NULL, 0); 2585 + if (rc) { 2586 + BNXT_NVM_ERR_MSG(dev, extack, MSG_RESIZE_UPDATE_ERR); 2587 + return rc; 2588 + } 2589 + } 2590 + return 0; 2591 + } 2592 + 2568 2593 int bnxt_flash_package_from_fw_obj(struct net_device *dev, const struct firmware *fw, 2569 2594 u32 install_type, struct netlink_ext_ack *extack) 2570 2595 { ··· 2606 2579 u8 cmd_err; 2607 2580 u16 index; 2608 2581 int rc; 2582 + 2583 + /* resize before flashing larger image than available space */ 2584 + rc = bnxt_resize_update_entry(dev, fw->size, extack); 2585 + if (rc) 2586 + return rc; 2609 2587 2610 2588 bnxt_hwrm_fw_set_time(bp); 2611 2589 ··· 3178 3146 } 3179 3147 3180 3148 static int bnxt_read_sfp_module_eeprom_info(struct bnxt *bp, u16 i2c_addr, 3181 - u16 page_number, u16 start_addr, 3182 - u16 data_length, u8 *buf) 3149 + u16 page_number, u8 bank, 3150 + u16 start_addr, u16 data_length, 3151 + u8 *buf) 3183 3152 { 3184 3153 struct hwrm_port_phy_i2c_read_output *output; 3185 3154 struct hwrm_port_phy_i2c_read_input *req; ··· 3201 3168 data_length -= xfer_size; 3202 3169 req->page_offset = cpu_to_le16(start_addr + byte_offset); 3203 3170 req->data_length = xfer_size; 3204 - req->enables = cpu_to_le32(start_addr + byte_offset ? 3205 - PORT_PHY_I2C_READ_REQ_ENABLES_PAGE_OFFSET : 0); 3171 + req->enables = 3172 + cpu_to_le32((start_addr + byte_offset ? 3173 + PORT_PHY_I2C_READ_REQ_ENABLES_PAGE_OFFSET : 3174 + 0) | 3175 + (bank ? 3176 + PORT_PHY_I2C_READ_REQ_ENABLES_BANK_NUMBER : 3177 + 0)); 3206 3178 rc = hwrm_req_send(bp, req); 3207 3179 if (!rc) 3208 3180 memcpy(buf + byte_offset, output->data, xfer_size); ··· 3237 3199 if (bp->hwrm_spec_code < 0x10202) 3238 3200 return -EOPNOTSUPP; 3239 3201 3240 - rc = bnxt_read_sfp_module_eeprom_info(bp, I2C_DEV_ADDR_A0, 0, 0, 3202 + rc = bnxt_read_sfp_module_eeprom_info(bp, I2C_DEV_ADDR_A0, 0, 0, 0, 3241 3203 SFF_DIAG_SUPPORT_OFFSET + 1, 3242 3204 data); 3243 3205 if (!rc) { ··· 3282 3244 if (start < ETH_MODULE_SFF_8436_LEN) { 3283 3245 if (start + eeprom->len > ETH_MODULE_SFF_8436_LEN) 3284 3246 length = ETH_MODULE_SFF_8436_LEN - start; 3285 - rc = bnxt_read_sfp_module_eeprom_info(bp, I2C_DEV_ADDR_A0, 0, 3247 + rc = bnxt_read_sfp_module_eeprom_info(bp, I2C_DEV_ADDR_A0, 0, 0, 3286 3248 start, length, data); 3287 3249 if (rc) 3288 3250 return rc; ··· 3294 3256 /* Read A2 portion of the EEPROM */ 3295 3257 if (length) { 3296 3258 start -= ETH_MODULE_SFF_8436_LEN; 3297 - rc = bnxt_read_sfp_module_eeprom_info(bp, I2C_DEV_ADDR_A2, 0, 3259 + rc = bnxt_read_sfp_module_eeprom_info(bp, I2C_DEV_ADDR_A2, 0, 0, 3298 3260 start, length, data); 3299 3261 } 3300 3262 return rc; 3263 + } 3264 + 3265 + static int bnxt_get_module_status(struct bnxt *bp, struct netlink_ext_ack *extack) 3266 + { 3267 + if (bp->link_info.module_status <= 3268 + PORT_PHY_QCFG_RESP_MODULE_STATUS_WARNINGMSG) 3269 + return 0; 3270 + 3271 + switch (bp->link_info.module_status) { 3272 + case PORT_PHY_QCFG_RESP_MODULE_STATUS_PWRDOWN: 3273 + NL_SET_ERR_MSG_MOD(extack, "Transceiver module is powering down"); 3274 + break; 3275 + case PORT_PHY_QCFG_RESP_MODULE_STATUS_NOTINSERTED: 3276 + NL_SET_ERR_MSG_MOD(extack, "Transceiver module not inserted"); 3277 + break; 3278 + case PORT_PHY_QCFG_RESP_MODULE_STATUS_CURRENTFAULT: 3279 + NL_SET_ERR_MSG_MOD(extack, "Transceiver module disabled due to current fault"); 3280 + break; 3281 + default: 3282 + NL_SET_ERR_MSG_MOD(extack, "Unknown error"); 3283 + break; 3284 + } 3285 + return -EINVAL; 3286 + } 3287 + 3288 + static int bnxt_get_module_eeprom_by_page(struct net_device *dev, 3289 + const struct ethtool_module_eeprom *page_data, 3290 + struct netlink_ext_ack *extack) 3291 + { 3292 + struct bnxt *bp = netdev_priv(dev); 3293 + int rc; 3294 + 3295 + rc = bnxt_get_module_status(bp, extack); 3296 + if (rc) 3297 + return rc; 3298 + 3299 + if (bp->hwrm_spec_code < 0x10202) { 3300 + NL_SET_ERR_MSG_MOD(extack, "Firmware version too old"); 3301 + return -EINVAL; 3302 + } 3303 + 3304 + if (page_data->bank && !(bp->phy_flags & BNXT_PHY_FL_BANK_SEL)) { 3305 + NL_SET_ERR_MSG_MOD(extack, "Firmware not capable for bank selection"); 3306 + return -EINVAL; 3307 + } 3308 + 3309 + rc = bnxt_read_sfp_module_eeprom_info(bp, page_data->i2c_address << 1, 3310 + page_data->page, page_data->bank, 3311 + page_data->offset, 3312 + page_data->length, 3313 + page_data->data); 3314 + if (rc) { 3315 + NL_SET_ERR_MSG_MOD(extack, "Module`s eeprom read failed"); 3316 + return rc; 3317 + } 3318 + return page_data->length; 3301 3319 } 3302 3320 3303 3321 static int bnxt_nway_reset(struct net_device *dev) ··· 4165 4071 .set_eee = bnxt_set_eee, 4166 4072 .get_module_info = bnxt_get_module_info, 4167 4073 .get_module_eeprom = bnxt_get_module_eeprom, 4074 + .get_module_eeprom_by_page = bnxt_get_module_eeprom_by_page, 4168 4075 .nway_reset = bnxt_nway_reset, 4169 4076 .set_phys_id = bnxt_set_phys_id, 4170 4077 .self_test = bnxt_self_test,

+169 -65

drivers/net/ethernet/broadcom/bnxt/bnxt_hsi.h

··· 254 254 #define HWRM_PORT_DSC_DUMP 0xd9UL 255 255 #define HWRM_PORT_EP_TX_QCFG 0xdaUL 256 256 #define HWRM_PORT_EP_TX_CFG 0xdbUL 257 + #define HWRM_PORT_CFG 0xdcUL 258 + #define HWRM_PORT_QCFG 0xddUL 257 259 #define HWRM_TEMP_MONITOR_QUERY 0xe0UL 258 260 #define HWRM_REG_POWER_QUERY 0xe1UL 259 261 #define HWRM_CORE_FREQUENCY_QUERY 0xe2UL ··· 381 379 #define HWRM_FUNC_BACKING_STORE_QCAPS_V2 0x1a8UL 382 380 #define HWRM_FUNC_DBR_PACING_NQLIST_QUERY 0x1a9UL 383 381 #define HWRM_FUNC_DBR_RECOVERY_COMPLETED 0x1aaUL 382 + #define HWRM_FUNC_SYNCE_CFG 0x1abUL 383 + #define HWRM_FUNC_SYNCE_QCFG 0x1acUL 384 384 #define HWRM_SELFTEST_QLIST 0x200UL 385 385 #define HWRM_SELFTEST_EXEC 0x201UL 386 386 #define HWRM_SELFTEST_IRQ 0x202UL ··· 421 417 #define HWRM_TF_SESSION_RESC_FREE 0x2ceUL 422 418 #define HWRM_TF_SESSION_RESC_FLUSH 0x2cfUL 423 419 #define HWRM_TF_SESSION_RESC_INFO 0x2d0UL 420 + #define HWRM_TF_SESSION_HOTUP_STATE_SET 0x2d1UL 421 + #define HWRM_TF_SESSION_HOTUP_STATE_GET 0x2d2UL 424 422 #define HWRM_TF_TBL_TYPE_GET 0x2daUL 425 423 #define HWRM_TF_TBL_TYPE_SET 0x2dbUL 426 424 #define HWRM_TF_TBL_TYPE_BULK_GET 0x2dcUL ··· 446 440 #define HWRM_TF_GLOBAL_CFG_GET 0x2fdUL 447 441 #define HWRM_TF_IF_TBL_SET 0x2feUL 448 442 #define HWRM_TF_IF_TBL_GET 0x2ffUL 443 + #define HWRM_TFC_TBL_SCOPE_QCAPS 0x380UL 444 + #define HWRM_TFC_TBL_SCOPE_ID_ALLOC 0x381UL 445 + #define HWRM_TFC_TBL_SCOPE_CONFIG 0x382UL 446 + #define HWRM_TFC_TBL_SCOPE_DECONFIG 0x383UL 447 + #define HWRM_TFC_TBL_SCOPE_FID_ADD 0x384UL 448 + #define HWRM_TFC_TBL_SCOPE_FID_REM 0x385UL 449 + #define HWRM_TFC_TBL_SCOPE_POOL_ALLOC 0x386UL 450 + #define HWRM_TFC_TBL_SCOPE_POOL_FREE 0x387UL 451 + #define HWRM_TFC_SESSION_ID_ALLOC 0x388UL 452 + #define HWRM_TFC_SESSION_FID_ADD 0x389UL 453 + #define HWRM_TFC_SESSION_FID_REM 0x38aUL 454 + #define HWRM_TFC_IDENT_ALLOC 0x38bUL 455 + #define HWRM_TFC_IDENT_FREE 0x38cUL 456 + #define HWRM_TFC_IDX_TBL_ALLOC 0x38dUL 457 + #define HWRM_TFC_IDX_TBL_ALLOC_SET 0x38eUL 458 + #define HWRM_TFC_IDX_TBL_SET 0x38fUL 459 + #define HWRM_TFC_IDX_TBL_GET 0x390UL 460 + #define HWRM_TFC_IDX_TBL_FREE 0x391UL 461 + #define HWRM_TFC_GLOBAL_ID_ALLOC 0x392UL 449 462 #define HWRM_SV 0x400UL 450 463 #define HWRM_DBG_READ_DIRECT 0xff10UL 451 464 #define HWRM_DBG_READ_INDIRECT 0xff11UL ··· 571 546 #define HWRM_VERSION_MAJOR 1 572 547 #define HWRM_VERSION_MINOR 10 573 548 #define HWRM_VERSION_UPDATE 2 574 - #define HWRM_VERSION_RSVD 95 575 - #define HWRM_VERSION_STR "1.10.2.95" 549 + #define HWRM_VERSION_RSVD 118 550 + #define HWRM_VERSION_STR "1.10.2.118" 576 551 577 552 /* hwrm_ver_get_input (size:192b/24B) */ 578 553 struct hwrm_ver_get_input { ··· 1682 1657 #define FUNC_QCAPS_RESP_FLAGS_EXT2_DBR_PACING_EXT_SUPPORTED 0x8UL 1683 1658 #define FUNC_QCAPS_RESP_FLAGS_EXT2_SW_DBR_DROP_RECOVERY_SUPPORTED 0x10UL 1684 1659 #define FUNC_QCAPS_RESP_FLAGS_EXT2_GENERIC_STATS_SUPPORTED 0x20UL 1660 + #define FUNC_QCAPS_RESP_FLAGS_EXT2_UDP_GSO_SUPPORTED 0x40UL 1661 + #define FUNC_QCAPS_RESP_FLAGS_EXT2_SYNCE_SUPPORTED 0x80UL 1662 + #define FUNC_QCAPS_RESP_FLAGS_EXT2_DBR_PACING_V0_SUPPORTED 0x100UL 1663 + #define FUNC_QCAPS_RESP_FLAGS_EXT2_TX_PKT_TS_CMPL_SUPPORTED 0x200UL 1685 1664 __le16 tunnel_disable_flag; 1686 1665 #define FUNC_QCAPS_RESP_TUNNEL_DISABLE_FLAG_DISABLE_VXLAN 0x1UL 1687 1666 #define FUNC_QCAPS_RESP_TUNNEL_DISABLE_FLAG_DISABLE_NGE 0x2UL ··· 1833 1804 #define FUNC_QCFG_RESP_MPC_CHNLS_TE_CFA_ENABLED 0x4UL 1834 1805 #define FUNC_QCFG_RESP_MPC_CHNLS_RE_CFA_ENABLED 0x8UL 1835 1806 #define FUNC_QCFG_RESP_MPC_CHNLS_PRIMATE_ENABLED 0x10UL 1836 - u8 unused_2[3]; 1807 + u8 db_page_size; 1808 + #define FUNC_QCFG_RESP_DB_PAGE_SIZE_4KB 0x0UL 1809 + #define FUNC_QCFG_RESP_DB_PAGE_SIZE_8KB 0x1UL 1810 + #define FUNC_QCFG_RESP_DB_PAGE_SIZE_16KB 0x2UL 1811 + #define FUNC_QCFG_RESP_DB_PAGE_SIZE_32KB 0x3UL 1812 + #define FUNC_QCFG_RESP_DB_PAGE_SIZE_64KB 0x4UL 1813 + #define FUNC_QCFG_RESP_DB_PAGE_SIZE_128KB 0x5UL 1814 + #define FUNC_QCFG_RESP_DB_PAGE_SIZE_256KB 0x6UL 1815 + #define FUNC_QCFG_RESP_DB_PAGE_SIZE_512KB 0x7UL 1816 + #define FUNC_QCFG_RESP_DB_PAGE_SIZE_1MB 0x8UL 1817 + #define FUNC_QCFG_RESP_DB_PAGE_SIZE_2MB 0x9UL 1818 + #define FUNC_QCFG_RESP_DB_PAGE_SIZE_4MB 0xaUL 1819 + #define FUNC_QCFG_RESP_DB_PAGE_SIZE_LAST FUNC_QCFG_RESP_DB_PAGE_SIZE_4MB 1820 + u8 unused_2[2]; 1837 1821 __le32 partition_min_bw; 1838 1822 #define FUNC_QCFG_RESP_PARTITION_MIN_BW_BW_VALUE_MASK 0xfffffffUL 1839 1823 #define FUNC_QCFG_RESP_PARTITION_MIN_BW_BW_VALUE_SFT 0 ··· 1918 1876 #define FUNC_CFG_REQ_FLAGS_PPP_PUSH_MODE_DISABLE 0x10000000UL 1919 1877 #define FUNC_CFG_REQ_FLAGS_BD_METADATA_ENABLE 0x20000000UL 1920 1878 #define FUNC_CFG_REQ_FLAGS_BD_METADATA_DISABLE 0x40000000UL 1879 + #define FUNC_CFG_REQ_FLAGS_KEY_CTX_ASSETS_TEST 0x80000000UL 1921 1880 __le32 enables; 1922 1881 #define FUNC_CFG_REQ_ENABLES_ADMIN_MTU 0x1UL 1923 1882 #define FUNC_CFG_REQ_ENABLES_MRU 0x2UL ··· 2064 2021 __le16 num_tx_key_ctxs; 2065 2022 __le16 num_rx_key_ctxs; 2066 2023 __le32 enables2; 2067 - #define FUNC_CFG_REQ_ENABLES2_KDNET 0x1UL 2024 + #define FUNC_CFG_REQ_ENABLES2_KDNET 0x1UL 2025 + #define FUNC_CFG_REQ_ENABLES2_DB_PAGE_SIZE 0x2UL 2068 2026 u8 port_kdnet_mode; 2069 2027 #define FUNC_CFG_REQ_PORT_KDNET_MODE_DISABLED 0x0UL 2070 2028 #define FUNC_CFG_REQ_PORT_KDNET_MODE_ENABLED 0x1UL 2071 2029 #define FUNC_CFG_REQ_PORT_KDNET_MODE_LAST FUNC_CFG_REQ_PORT_KDNET_MODE_ENABLED 2072 - u8 unused_0[7]; 2030 + u8 db_page_size; 2031 + #define FUNC_CFG_REQ_DB_PAGE_SIZE_4KB 0x0UL 2032 + #define FUNC_CFG_REQ_DB_PAGE_SIZE_8KB 0x1UL 2033 + #define FUNC_CFG_REQ_DB_PAGE_SIZE_16KB 0x2UL 2034 + #define FUNC_CFG_REQ_DB_PAGE_SIZE_32KB 0x3UL 2035 + #define FUNC_CFG_REQ_DB_PAGE_SIZE_64KB 0x4UL 2036 + #define FUNC_CFG_REQ_DB_PAGE_SIZE_128KB 0x5UL 2037 + #define FUNC_CFG_REQ_DB_PAGE_SIZE_256KB 0x6UL 2038 + #define FUNC_CFG_REQ_DB_PAGE_SIZE_512KB 0x7UL 2039 + #define FUNC_CFG_REQ_DB_PAGE_SIZE_1MB 0x8UL 2040 + #define FUNC_CFG_REQ_DB_PAGE_SIZE_2MB 0x9UL 2041 + #define FUNC_CFG_REQ_DB_PAGE_SIZE_4MB 0xaUL 2042 + #define FUNC_CFG_REQ_DB_PAGE_SIZE_LAST FUNC_CFG_REQ_DB_PAGE_SIZE_4MB 2043 + u8 unused_0[6]; 2073 2044 }; 2074 2045 2075 2046 /* hwrm_func_cfg_output (size:128b/16B) */ ··· 2117 2060 __le64 resp_addr; 2118 2061 __le16 fid; 2119 2062 u8 flags; 2120 - #define FUNC_QSTATS_REQ_FLAGS_UNUSED 0x0UL 2121 - #define FUNC_QSTATS_REQ_FLAGS_ROCE_ONLY 0x1UL 2122 - #define FUNC_QSTATS_REQ_FLAGS_COUNTER_MASK 0x2UL 2123 - #define FUNC_QSTATS_REQ_FLAGS_LAST FUNC_QSTATS_REQ_FLAGS_COUNTER_MASK 2063 + #define FUNC_QSTATS_REQ_FLAGS_ROCE_ONLY 0x1UL 2064 + #define FUNC_QSTATS_REQ_FLAGS_COUNTER_MASK 0x2UL 2065 + #define FUNC_QSTATS_REQ_FLAGS_L2_ONLY 0x4UL 2124 2066 u8 unused_0[5]; 2125 2067 }; 2126 2068 ··· 2149 2093 __le64 rx_agg_bytes; 2150 2094 __le64 rx_agg_events; 2151 2095 __le64 rx_agg_aborts; 2152 - u8 unused_0[7]; 2096 + u8 clear_seq; 2097 + u8 unused_0[6]; 2153 2098 u8 valid; 2154 2099 }; 2155 2100 ··· 2163 2106 __le64 resp_addr; 2164 2107 __le16 fid; 2165 2108 u8 flags; 2166 - #define FUNC_QSTATS_EXT_REQ_FLAGS_UNUSED 0x0UL 2167 - #define FUNC_QSTATS_EXT_REQ_FLAGS_ROCE_ONLY 0x1UL 2168 - #define FUNC_QSTATS_EXT_REQ_FLAGS_COUNTER_MASK 0x2UL 2169 - #define FUNC_QSTATS_EXT_REQ_FLAGS_LAST FUNC_QSTATS_EXT_REQ_FLAGS_COUNTER_MASK 2109 + #define FUNC_QSTATS_EXT_REQ_FLAGS_ROCE_ONLY 0x1UL 2110 + #define FUNC_QSTATS_EXT_REQ_FLAGS_COUNTER_MASK 0x2UL 2170 2111 u8 unused_0[1]; 2171 2112 __le32 enables; 2172 2113 #define FUNC_QSTATS_EXT_REQ_ENABLES_SCHQ_ID 0x1UL ··· 2265 2210 #define FUNC_DRV_RGTR_REQ_FLAGS_FAST_RESET_SUPPORT 0x80UL 2266 2211 #define FUNC_DRV_RGTR_REQ_FLAGS_RSS_STRICT_HASH_TYPE_SUPPORT 0x100UL 2267 2212 #define FUNC_DRV_RGTR_REQ_FLAGS_NPAR_1_2_SUPPORT 0x200UL 2213 + #define FUNC_DRV_RGTR_REQ_FLAGS_ASYM_QUEUE_CFG_SUPPORT 0x400UL 2268 2214 __le32 enables; 2269 2215 #define FUNC_DRV_RGTR_REQ_ENABLES_OS_TYPE 0x1UL 2270 2216 #define FUNC_DRV_RGTR_REQ_ENABLES_VER 0x2UL ··· 3211 3155 #define FUNC_PTP_PIN_QCFG_RESP_PIN1_USAGE_SYNC_OUT 0x4UL 3212 3156 #define FUNC_PTP_PIN_QCFG_RESP_PIN1_USAGE_LAST FUNC_PTP_PIN_QCFG_RESP_PIN1_USAGE_SYNC_OUT 3213 3157 u8 pin2_usage; 3214 - #define FUNC_PTP_PIN_QCFG_RESP_PIN2_USAGE_NONE 0x0UL 3215 - #define FUNC_PTP_PIN_QCFG_RESP_PIN2_USAGE_PPS_IN 0x1UL 3216 - #define FUNC_PTP_PIN_QCFG_RESP_PIN2_USAGE_PPS_OUT 0x2UL 3217 - #define FUNC_PTP_PIN_QCFG_RESP_PIN2_USAGE_SYNC_IN 0x3UL 3218 - #define FUNC_PTP_PIN_QCFG_RESP_PIN2_USAGE_SYNC_OUT 0x4UL 3219 - #define FUNC_PTP_PIN_QCFG_RESP_PIN2_USAGE_LAST FUNC_PTP_PIN_QCFG_RESP_PIN2_USAGE_SYNC_OUT 3158 + #define FUNC_PTP_PIN_QCFG_RESP_PIN2_USAGE_NONE 0x0UL 3159 + #define FUNC_PTP_PIN_QCFG_RESP_PIN2_USAGE_PPS_IN 0x1UL 3160 + #define FUNC_PTP_PIN_QCFG_RESP_PIN2_USAGE_PPS_OUT 0x2UL 3161 + #define FUNC_PTP_PIN_QCFG_RESP_PIN2_USAGE_SYNC_IN 0x3UL 3162 + #define FUNC_PTP_PIN_QCFG_RESP_PIN2_USAGE_SYNC_OUT 0x4UL 3163 + #define FUNC_PTP_PIN_QCFG_RESP_PIN2_USAGE_SYNCE_PRIMARY_CLOCK_OUT 0x5UL 3164 + #define FUNC_PTP_PIN_QCFG_RESP_PIN2_USAGE_SYNCE_SECONDARY_CLOCK_OUT 0x6UL 3165 + #define FUNC_PTP_PIN_QCFG_RESP_PIN2_USAGE_LAST FUNC_PTP_PIN_QCFG_RESP_PIN2_USAGE_SYNCE_SECONDARY_CLOCK_OUT 3220 3166 u8 pin3_usage; 3221 - #define FUNC_PTP_PIN_QCFG_RESP_PIN3_USAGE_NONE 0x0UL 3222 - #define FUNC_PTP_PIN_QCFG_RESP_PIN3_USAGE_PPS_IN 0x1UL 3223 - #define FUNC_PTP_PIN_QCFG_RESP_PIN3_USAGE_PPS_OUT 0x2UL 3224 - #define FUNC_PTP_PIN_QCFG_RESP_PIN3_USAGE_SYNC_IN 0x3UL 3225 - #define FUNC_PTP_PIN_QCFG_RESP_PIN3_USAGE_SYNC_OUT 0x4UL 3226 - #define FUNC_PTP_PIN_QCFG_RESP_PIN3_USAGE_LAST FUNC_PTP_PIN_QCFG_RESP_PIN3_USAGE_SYNC_OUT 3167 + #define FUNC_PTP_PIN_QCFG_RESP_PIN3_USAGE_NONE 0x0UL 3168 + #define FUNC_PTP_PIN_QCFG_RESP_PIN3_USAGE_PPS_IN 0x1UL 3169 + #define FUNC_PTP_PIN_QCFG_RESP_PIN3_USAGE_PPS_OUT 0x2UL 3170 + #define FUNC_PTP_PIN_QCFG_RESP_PIN3_USAGE_SYNC_IN 0x3UL 3171 + #define FUNC_PTP_PIN_QCFG_RESP_PIN3_USAGE_SYNC_OUT 0x4UL 3172 + #define FUNC_PTP_PIN_QCFG_RESP_PIN3_USAGE_SYNCE_PRIMARY_CLOCK_OUT 0x5UL 3173 + #define FUNC_PTP_PIN_QCFG_RESP_PIN3_USAGE_SYNCE_SECONDARY_CLOCK_OUT 0x6UL 3174 + #define FUNC_PTP_PIN_QCFG_RESP_PIN3_USAGE_LAST FUNC_PTP_PIN_QCFG_RESP_PIN3_USAGE_SYNCE_SECONDARY_CLOCK_OUT 3227 3175 u8 unused_0; 3228 3176 u8 valid; 3229 3177 }; ··· 3275 3215 #define FUNC_PTP_PIN_CFG_REQ_PIN2_STATE_ENABLED 0x1UL 3276 3216 #define FUNC_PTP_PIN_CFG_REQ_PIN2_STATE_LAST FUNC_PTP_PIN_CFG_REQ_PIN2_STATE_ENABLED 3277 3217 u8 pin2_usage; 3278 - #define FUNC_PTP_PIN_CFG_REQ_PIN2_USAGE_NONE 0x0UL 3279 - #define FUNC_PTP_PIN_CFG_REQ_PIN2_USAGE_PPS_IN 0x1UL 3280 - #define FUNC_PTP_PIN_CFG_REQ_PIN2_USAGE_PPS_OUT 0x2UL 3281 - #define FUNC_PTP_PIN_CFG_REQ_PIN2_USAGE_SYNC_IN 0x3UL 3282 - #define FUNC_PTP_PIN_CFG_REQ_PIN2_USAGE_SYNC_OUT 0x4UL 3283 - #define FUNC_PTP_PIN_CFG_REQ_PIN2_USAGE_LAST FUNC_PTP_PIN_CFG_REQ_PIN2_USAGE_SYNC_OUT 3218 + #define FUNC_PTP_PIN_CFG_REQ_PIN2_USAGE_NONE 0x0UL 3219 + #define FUNC_PTP_PIN_CFG_REQ_PIN2_USAGE_PPS_IN 0x1UL 3220 + #define FUNC_PTP_PIN_CFG_REQ_PIN2_USAGE_PPS_OUT 0x2UL 3221 + #define FUNC_PTP_PIN_CFG_REQ_PIN2_USAGE_SYNC_IN 0x3UL 3222 + #define FUNC_PTP_PIN_CFG_REQ_PIN2_USAGE_SYNC_OUT 0x4UL 3223 + #define FUNC_PTP_PIN_CFG_REQ_PIN2_USAGE_SYNCE_PRIMARY_CLOCK_OUT 0x5UL 3224 + #define FUNC_PTP_PIN_CFG_REQ_PIN2_USAGE_SYNCE_SECONDARY_CLOCK_OUT 0x6UL 3225 + #define FUNC_PTP_PIN_CFG_REQ_PIN2_USAGE_LAST FUNC_PTP_PIN_CFG_REQ_PIN2_USAGE_SYNCE_SECONDARY_CLOCK_OUT 3284 3226 u8 pin3_state; 3285 3227 #define FUNC_PTP_PIN_CFG_REQ_PIN3_STATE_DISABLED 0x0UL 3286 3228 #define FUNC_PTP_PIN_CFG_REQ_PIN3_STATE_ENABLED 0x1UL 3287 3229 #define FUNC_PTP_PIN_CFG_REQ_PIN3_STATE_LAST FUNC_PTP_PIN_CFG_REQ_PIN3_STATE_ENABLED 3288 3230 u8 pin3_usage; 3289 - #define FUNC_PTP_PIN_CFG_REQ_PIN3_USAGE_NONE 0x0UL 3290 - #define FUNC_PTP_PIN_CFG_REQ_PIN3_USAGE_PPS_IN 0x1UL 3291 - #define FUNC_PTP_PIN_CFG_REQ_PIN3_USAGE_PPS_OUT 0x2UL 3292 - #define FUNC_PTP_PIN_CFG_REQ_PIN3_USAGE_SYNC_IN 0x3UL 3293 - #define FUNC_PTP_PIN_CFG_REQ_PIN3_USAGE_SYNC_OUT 0x4UL 3294 - #define FUNC_PTP_PIN_CFG_REQ_PIN3_USAGE_LAST FUNC_PTP_PIN_CFG_REQ_PIN3_USAGE_SYNC_OUT 3231 + #define FUNC_PTP_PIN_CFG_REQ_PIN3_USAGE_NONE 0x0UL 3232 + #define FUNC_PTP_PIN_CFG_REQ_PIN3_USAGE_PPS_IN 0x1UL 3233 + #define FUNC_PTP_PIN_CFG_REQ_PIN3_USAGE_PPS_OUT 0x2UL 3234 + #define FUNC_PTP_PIN_CFG_REQ_PIN3_USAGE_SYNC_IN 0x3UL 3235 + #define FUNC_PTP_PIN_CFG_REQ_PIN3_USAGE_SYNC_OUT 0x4UL 3236 + #define FUNC_PTP_PIN_CFG_REQ_PIN3_USAGE_SYNCE_PRIMARY_CLOCK_OUT 0x5UL 3237 + #define FUNC_PTP_PIN_CFG_REQ_PIN3_USAGE_SYNCE_SECONDARY_CLOCK_OUT 0x6UL 3238 + #define FUNC_PTP_PIN_CFG_REQ_PIN3_USAGE_LAST FUNC_PTP_PIN_CFG_REQ_PIN3_USAGE_SYNCE_SECONDARY_CLOCK_OUT 3295 3239 u8 unused_0[4]; 3296 3240 }; 3297 3241 ··· 3383 3319 __le16 seq_id; 3384 3320 __le16 resp_len; 3385 3321 __le64 pps_event_ts; 3386 - __le64 ptm_res_local_ts; 3387 - __le64 ptm_pmstr_ts; 3388 - __le32 ptm_mstr_prop_dly; 3322 + __le64 ptm_local_ts; 3323 + __le64 ptm_system_ts; 3324 + __le32 ptm_link_delay; 3389 3325 u8 unused_0[3]; 3390 3326 u8 valid; 3391 3327 }; ··· 3481 3417 #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_LAST FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_INVALID 3482 3418 __le16 instance; 3483 3419 __le32 flags; 3484 - #define FUNC_BACKING_STORE_CFG_V2_REQ_FLAGS_PREBOOT_MODE 0x1UL 3420 + #define FUNC_BACKING_STORE_CFG_V2_REQ_FLAGS_PREBOOT_MODE 0x1UL 3421 + #define FUNC_BACKING_STORE_CFG_V2_REQ_FLAGS_BS_CFG_ALL_DONE 0x2UL 3422 + #define FUNC_BACKING_STORE_CFG_V2_REQ_FLAGS_BS_EXTEND 0x4UL 3485 3423 __le64 page_dir; 3486 3424 __le32 num_entries; 3487 3425 __le16 entry_size; ··· 3919 3853 u8 unused_0[6]; 3920 3854 }; 3921 3855 3922 - /* hwrm_port_phy_qcfg_output (size:768b/96B) */ 3856 + /* hwrm_port_phy_qcfg_output (size:832b/104B) */ 3923 3857 struct hwrm_port_phy_qcfg_output { 3924 3858 __le16 error_code; 3925 3859 __le16 req_type; ··· 4216 4150 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_PAM4_ADV_SPEEDS_50GB 0x1UL 4217 4151 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_PAM4_ADV_SPEEDS_100GB 0x2UL 4218 4152 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_PAM4_ADV_SPEEDS_200GB 0x4UL 4153 + u8 link_down_reason; 4154 + #define PORT_PHY_QCFG_RESP_LINK_DOWN_REASON_RF 0x1UL 4155 + u8 unused_0[7]; 4219 4156 u8 valid; 4220 4157 }; 4221 4158 ··· 4491 4422 __le64 resp_addr; 4492 4423 __le16 port_id; 4493 4424 u8 flags; 4494 - #define PORT_QSTATS_REQ_FLAGS_UNUSED 0x0UL 4495 - #define PORT_QSTATS_REQ_FLAGS_COUNTER_MASK 0x1UL 4496 - #define PORT_QSTATS_REQ_FLAGS_LAST PORT_QSTATS_REQ_FLAGS_COUNTER_MASK 4425 + #define PORT_QSTATS_REQ_FLAGS_COUNTER_MASK 0x1UL 4497 4426 u8 unused_0[5]; 4498 4427 __le64 tx_stat_host_addr; 4499 4428 __le64 rx_stat_host_addr; ··· 4619 4552 __le16 tx_stat_size; 4620 4553 __le16 rx_stat_size; 4621 4554 u8 flags; 4622 - #define PORT_QSTATS_EXT_REQ_FLAGS_UNUSED 0x0UL 4623 - #define PORT_QSTATS_EXT_REQ_FLAGS_COUNTER_MASK 0x1UL 4624 - #define PORT_QSTATS_EXT_REQ_FLAGS_LAST PORT_QSTATS_EXT_REQ_FLAGS_COUNTER_MASK 4555 + #define PORT_QSTATS_EXT_REQ_FLAGS_COUNTER_MASK 0x1UL 4625 4556 u8 unused_0; 4626 4557 __le64 tx_stat_host_addr; 4627 4558 __le64 rx_stat_host_addr; ··· 4678 4613 __le16 port_id; 4679 4614 __le16 ecn_stat_buf_size; 4680 4615 u8 flags; 4681 - #define PORT_ECN_QSTATS_REQ_FLAGS_UNUSED 0x0UL 4682 - #define PORT_ECN_QSTATS_REQ_FLAGS_COUNTER_MASK 0x1UL 4683 - #define PORT_ECN_QSTATS_REQ_FLAGS_LAST PORT_ECN_QSTATS_REQ_FLAGS_COUNTER_MASK 4616 + #define PORT_ECN_QSTATS_REQ_FLAGS_COUNTER_MASK 0x1UL 4684 4617 u8 unused_0[3]; 4685 4618 __le64 ecn_stat_host_addr; 4686 4619 }; ··· 4877 4814 #define PORT_PHY_QCAPS_RESP_SUPPORTED_PAM4_SPEEDS_FORCE_MODE_100G 0x2UL 4878 4815 #define PORT_PHY_QCAPS_RESP_SUPPORTED_PAM4_SPEEDS_FORCE_MODE_200G 0x4UL 4879 4816 __le16 flags2; 4880 - #define PORT_PHY_QCAPS_RESP_FLAGS2_PAUSE_UNSUPPORTED 0x1UL 4881 - #define PORT_PHY_QCAPS_RESP_FLAGS2_PFC_UNSUPPORTED 0x2UL 4817 + #define PORT_PHY_QCAPS_RESP_FLAGS2_PAUSE_UNSUPPORTED 0x1UL 4818 + #define PORT_PHY_QCAPS_RESP_FLAGS2_PFC_UNSUPPORTED 0x2UL 4819 + #define PORT_PHY_QCAPS_RESP_FLAGS2_BANK_ADDR_SUPPORTED 0x4UL 4882 4820 u8 internal_port_cnt; 4883 4821 u8 valid; 4884 4822 }; ··· 4894 4830 __le32 flags; 4895 4831 __le32 enables; 4896 4832 #define PORT_PHY_I2C_READ_REQ_ENABLES_PAGE_OFFSET 0x1UL 4833 + #define PORT_PHY_I2C_READ_REQ_ENABLES_BANK_NUMBER 0x2UL 4897 4834 __le16 port_id; 4898 4835 u8 i2c_slave_addr; 4899 - u8 unused_0; 4836 + u8 bank_number; 4900 4837 __le16 page_number; 4901 4838 __le16 page_offset; 4902 4839 u8 data_length; ··· 6602 6537 #define VNIC_QCAPS_RESP_FLAGS_RSS_IPSEC_ESP_SPI_IPV4_CAP 0x400000UL 6603 6538 #define VNIC_QCAPS_RESP_FLAGS_RSS_IPSEC_AH_SPI_IPV6_CAP 0x800000UL 6604 6539 #define VNIC_QCAPS_RESP_FLAGS_RSS_IPSEC_ESP_SPI_IPV6_CAP 0x1000000UL 6540 + #define VNIC_QCAPS_RESP_FLAGS_OUTERMOST_RSS_TRUSTED_VF_CAP 0x2000000UL 6605 6541 __le16 max_aggs_supported; 6606 6542 u8 unused_1[5]; 6607 6543 u8 valid; ··· 6893 6827 #define RING_ALLOC_REQ_FLAGS_RX_SOP_PAD 0x1UL 6894 6828 #define RING_ALLOC_REQ_FLAGS_DISABLE_CQ_OVERFLOW_DETECTION 0x2UL 6895 6829 #define RING_ALLOC_REQ_FLAGS_NQ_DBR_PACING 0x4UL 6830 + #define RING_ALLOC_REQ_FLAGS_TX_PKT_TS_CMPL_ENABLE 0x8UL 6896 6831 __le64 page_tbl_addr; 6897 6832 __le32 fbo; 6898 6833 u8 page_size; ··· 7693 7626 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_UNKNOWN 0x0UL 7694 7627 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_TCP 0x6UL 7695 7628 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_UDP 0x11UL 7696 - #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_LAST CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_UDP 7629 + #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_ICMP 0x1UL 7630 + #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_ICMPV6 0x3aUL 7631 + #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_RSVD 0xffUL 7632 + #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_LAST CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_RSVD 7697 7633 __le16 dst_id; 7698 7634 __le16 mirror_vnic_id; 7699 7635 u8 tunnel_type; ··· 8407 8337 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_LAG_SUPPORTED 0x20000UL 8408 8338 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_NTUPLE_FLOW_NO_L2CTX_SUPPORTED 0x40000UL 8409 8339 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_NIC_FLOW_STATS_SUPPORTED 0x80000UL 8340 + #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_NTUPLE_FLOW_RX_EXT_IP_PROTO_SUPPORTED 0x100000UL 8410 8341 u8 unused_0[3]; 8411 8342 u8 valid; 8412 8343 }; ··· 8426 8355 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL 8427 8356 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL 8428 8357 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 0xcUL 8429 - #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_LAST TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 8358 + #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_CUSTOM_GRE 0xdUL 8359 + #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_ECPRI 0xeUL 8360 + #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_LAST TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_ECPRI 8430 8361 u8 unused_0[7]; 8431 8362 }; 8432 8363 ··· 8440 8367 __le16 resp_len; 8441 8368 __le16 tunnel_dst_port_id; 8442 8369 __be16 tunnel_dst_port_val; 8443 - u8 unused_0[3]; 8370 + u8 upar_in_use; 8371 + #define TUNNEL_DST_PORT_QUERY_RESP_UPAR_IN_USE_UPAR0 0x1UL 8372 + #define TUNNEL_DST_PORT_QUERY_RESP_UPAR_IN_USE_UPAR1 0x2UL 8373 + #define TUNNEL_DST_PORT_QUERY_RESP_UPAR_IN_USE_UPAR2 0x4UL 8374 + #define TUNNEL_DST_PORT_QUERY_RESP_UPAR_IN_USE_UPAR3 0x8UL 8375 + #define TUNNEL_DST_PORT_QUERY_RESP_UPAR_IN_USE_UPAR4 0x10UL 8376 + #define TUNNEL_DST_PORT_QUERY_RESP_UPAR_IN_USE_UPAR5 0x20UL 8377 + #define TUNNEL_DST_PORT_QUERY_RESP_UPAR_IN_USE_UPAR6 0x40UL 8378 + #define TUNNEL_DST_PORT_QUERY_RESP_UPAR_IN_USE_UPAR7 0x80UL 8379 + u8 unused_0[2]; 8444 8380 u8 valid; 8445 8381 }; 8446 8382 ··· 8467 8385 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL 8468 8386 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL 8469 8387 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 0xcUL 8470 - #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_LAST TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 8388 + #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_CUSTOM_GRE 0xdUL 8389 + #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_ECPRI 0xeUL 8390 + #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_LAST TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_ECPRI 8471 8391 u8 unused_0; 8472 8392 __be16 tunnel_dst_port_val; 8473 8393 u8 unused_1[4]; ··· 8482 8398 __le16 seq_id; 8483 8399 __le16 resp_len; 8484 8400 __le16 tunnel_dst_port_id; 8485 - u8 unused_0[5]; 8401 + u8 error_info; 8402 + #define TUNNEL_DST_PORT_ALLOC_RESP_ERROR_INFO_SUCCESS 0x0UL 8403 + #define TUNNEL_DST_PORT_ALLOC_RESP_ERROR_INFO_ERR_ALLOCATED 0x1UL 8404 + #define TUNNEL_DST_PORT_ALLOC_RESP_ERROR_INFO_ERR_NO_RESOURCE 0x2UL 8405 + #define TUNNEL_DST_PORT_ALLOC_RESP_ERROR_INFO_LAST TUNNEL_DST_PORT_ALLOC_RESP_ERROR_INFO_ERR_NO_RESOURCE 8406 + u8 upar_in_use; 8407 + #define TUNNEL_DST_PORT_ALLOC_RESP_UPAR_IN_USE_UPAR0 0x1UL 8408 + #define TUNNEL_DST_PORT_ALLOC_RESP_UPAR_IN_USE_UPAR1 0x2UL 8409 + #define TUNNEL_DST_PORT_ALLOC_RESP_UPAR_IN_USE_UPAR2 0x4UL 8410 + #define TUNNEL_DST_PORT_ALLOC_RESP_UPAR_IN_USE_UPAR3 0x8UL 8411 + #define TUNNEL_DST_PORT_ALLOC_RESP_UPAR_IN_USE_UPAR4 0x10UL 8412 + #define TUNNEL_DST_PORT_ALLOC_RESP_UPAR_IN_USE_UPAR5 0x20UL 8413 + #define TUNNEL_DST_PORT_ALLOC_RESP_UPAR_IN_USE_UPAR6 0x40UL 8414 + #define TUNNEL_DST_PORT_ALLOC_RESP_UPAR_IN_USE_UPAR7 0x80UL 8415 + u8 unused_0[3]; 8486 8416 u8 valid; 8487 8417 }; 8488 8418 ··· 8514 8416 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL 8515 8417 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL 8516 8418 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 0xcUL 8517 - #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_LAST TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 8419 + #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_CUSTOM_GRE 0xdUL 8420 + #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_ECPRI 0xeUL 8421 + #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_LAST TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_ECPRI 8518 8422 u8 unused_0; 8519 8423 __le16 tunnel_dst_port_id; 8520 8424 u8 unused_1[4]; ··· 8528 8428 __le16 req_type; 8529 8429 __le16 seq_id; 8530 8430 __le16 resp_len; 8531 - u8 unused_1[7]; 8431 + u8 error_info; 8432 + #define TUNNEL_DST_PORT_FREE_RESP_ERROR_INFO_SUCCESS 0x0UL 8433 + #define TUNNEL_DST_PORT_FREE_RESP_ERROR_INFO_ERR_NOT_OWNER 0x1UL 8434 + #define TUNNEL_DST_PORT_FREE_RESP_ERROR_INFO_ERR_NOT_ALLOCATED 0x2UL 8435 + #define TUNNEL_DST_PORT_FREE_RESP_ERROR_INFO_LAST TUNNEL_DST_PORT_FREE_RESP_ERROR_INFO_ERR_NOT_ALLOCATED 8436 + u8 unused_1[6]; 8532 8437 u8 valid; 8533 8438 }; 8534 8439 ··· 8791 8686 __le64 resp_addr; 8792 8687 __le16 generic_stat_size; 8793 8688 u8 flags; 8794 - #define STAT_GENERIC_QSTATS_REQ_FLAGS_COUNTER 0x0UL 8795 - #define STAT_GENERIC_QSTATS_REQ_FLAGS_COUNTER_MASK 0x1UL 8796 - #define STAT_GENERIC_QSTATS_REQ_FLAGS_LAST STAT_GENERIC_QSTATS_REQ_FLAGS_COUNTER_MASK 8689 + #define STAT_GENERIC_QSTATS_REQ_FLAGS_COUNTER_MASK 0x1UL 8797 8690 u8 unused_0[5]; 8798 8691 __le64 generic_stat_host_addr; 8799 8692 }; ··· 10305 10202 #define FW_STATUS_REG_SHUTDOWN 0x100000UL 10306 10203 #define FW_STATUS_REG_CRASHED_NO_MASTER 0x200000UL 10307 10204 #define FW_STATUS_REG_RECOVERING 0x400000UL 10205 + #define FW_STATUS_REG_MANU_DEBUG_STATUS 0x800000UL 10308 10206 }; 10309 10207 10310 10208 /* hcomm_status (size:64b/8B) */