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[PATCH] PPC 44x EMAC driver: add 440GR support

Add PowerPC 440GR support

Signed-off-by: Stefan Roese <sr@denx.de>
Signed-off-by: Eugene Surovegin <ebs@ebshome.net>
Signed-off-by: Jeff Garzik <jgarzik@pobox.com>

authored by

Eugene Surovegin and committed by
Jeff Garzik 1b195916 7ad8a89c

+8 -6
+1 -1
drivers/net/Kconfig
··· 1203 1203 1204 1204 config IBM_EMAC_PHY_RX_CLK_FIX 1205 1205 bool "PHY Rx clock workaround" 1206 - depends on IBM_EMAC && (405EP || 440GX || 440EP) 1206 + depends on IBM_EMAC && (405EP || 440GX || 440EP || 440GR) 1207 1207 help 1208 1208 Enable this if EMAC attached to a PHY which doesn't generate 1209 1209 RX clock if there is no link, if this is the case, you will
+2 -1
drivers/net/ibm_emac/ibm_emac.h
··· 26 26 /* This is a simple check to prevent use of this driver on non-tested SoCs */ 27 27 #if !defined(CONFIG_405GP) && !defined(CONFIG_405GPR) && !defined(CONFIG_405EP) && \ 28 28 !defined(CONFIG_440GP) && !defined(CONFIG_440GX) && !defined(CONFIG_440SP) && \ 29 - !defined(CONFIG_440EP) && !defined(CONFIG_NP405H) && !defined(CONFIG_440SPE) 29 + !defined(CONFIG_440EP) && !defined(CONFIG_NP405H) && !defined(CONFIG_440SPE) && \ 30 + !defined(CONFIG_440GR) 30 31 #error "Unknown SoC. Please, check chip user manual and make sure EMAC defines are OK" 31 32 #endif 32 33
+4 -3
drivers/net/ibm_emac/ibm_emac_core.c
··· 87 87 */ 88 88 static u32 busy_phy_map; 89 89 90 - #if defined(CONFIG_IBM_EMAC_PHY_RX_CLK_FIX) && (defined(CONFIG_405EP) || defined(CONFIG_440EP)) 90 + #if defined(CONFIG_IBM_EMAC_PHY_RX_CLK_FIX) && \ 91 + (defined(CONFIG_405EP) || defined(CONFIG_440EP) || defined(CONFIG_440GR)) 91 92 /* 405EP has "EMAC to PHY Control Register" (CPC0_EPCTL) which can help us 92 93 * with PHY RX clock problem. 93 - * 440EP has more sane SDR0_MFR register implementation than 440GX, which 94 + * 440EP/440GR has more sane SDR0_MFR register implementation than 440GX, which 94 95 * also allows controlling each EMAC clock 95 96 */ 96 97 static inline void EMAC_RX_CLK_TX(int idx) ··· 101 100 102 101 #if defined(CONFIG_405EP) 103 102 mtdcr(0xf3, mfdcr(0xf3) | (1 << idx)); 104 - #else /* CONFIG_440EP */ 103 + #else /* CONFIG_440EP || CONFIG_440GR */ 105 104 SDR_WRITE(DCRN_SDR_MFR, SDR_READ(DCRN_SDR_MFR) | (0x08000000 >> idx)); 106 105 #endif 107 106
+1 -1
drivers/net/ibm_emac/ibm_emac_mal.h
··· 32 32 * reflect the fact that 40x and 44x have slightly different MALs. --ebs 33 33 */ 34 34 #if defined(CONFIG_405GP) || defined(CONFIG_405GPR) || defined(CONFIG_405EP) || \ 35 - defined(CONFIG_440EP) || defined(CONFIG_NP405H) 35 + defined(CONFIG_440EP) || defined(CONFIG_440GR) || defined(CONFIG_NP405H) 36 36 #define MAL_VERSION 1 37 37 #elif defined(CONFIG_440GP) || defined(CONFIG_440GX) || defined(CONFIG_440SP) || \ 38 38 defined(CONFIG_440SPE)