tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
MIPS: Hardcode cpu_has_mips* where target ISA allows
In the same vein as commit 93e01942a6eb ("MIPS: Hardcode cpu_has_* where
known at compile time due to ISA"), we can use our knowledge of the ISA
being targeted by the kernel build to make cpu_has_mips* macros
compile-time constant in some cases. This allows the compiler greater
opportunity to optimize out code which will never execute.
Signed-off-by: Paul Burton <paul.burton@mips.com>
Patchwork: https://patchwork.linux-mips.org/patch/21245/
Cc: linux-mips@linux-mips.org
+24
-11
+24
-11
arch/mips/include/asm/cpu-features.h
+24
-11
arch/mips/include/asm/cpu-features.h
···
15
15
#include <cpu-feature-overrides.h>
16
16
17
17
#define __ase(ase) (cpu_data[0].ases & (ase))
18
+
#define __isa(isa) (cpu_data[0].isa_level & (isa))
18
19
#define __opt(opt) (cpu_data[0].options & (opt))
19
20
20
21
/*
···
52
51
*/
53
52
#define __isa_lt_and_ase(isa, ase) ((MIPS_ISA_REV < (isa)) && __ase(ase))
54
53
#define __isa_lt_and_opt(isa, opt) ((MIPS_ISA_REV < (isa)) && __opt(opt))
54
+
55
+
/*
56
+
* Similarly allow for ISA level checks that take into account knowledge of the
57
+
* ISA targeted by the kernel build, provided by MIPS_ISA_REV.
58
+
*/
59
+
#define __isa_ge_and_flag(isa, flag) ((MIPS_ISA_REV >= (isa)) && __isa(flag))
60
+
#define __isa_ge_or_flag(isa, flag) ((MIPS_ISA_REV >= (isa)) || __isa(flag))
61
+
#define __isa_lt_and_flag(isa, flag) ((MIPS_ISA_REV < (isa)) && __isa(flag))
62
+
#define __isa_range(ge, lt) \
63
+
((MIPS_ISA_REV >= (ge)) && (MIPS_ISA_REV < (lt)))
64
+
#define __isa_range_or_flag(ge, lt, flag) \
65
+
(__isa_range(ge, lt) || ((MIPS_ISA_REV < (lt)) && __isa(flag)))
55
66
56
67
/*
57
68
* SMP assumption: Options of CPU 0 are a superset of all processors.
···
267
254
#endif
268
255
269
256
#ifndef cpu_has_mips_1
270
-
# define cpu_has_mips_1 (!cpu_has_mips_r6)
257
+
# define cpu_has_mips_1 (MIPS_ISA_REV < 6)
271
258
#endif
272
259
#ifndef cpu_has_mips_2
273
-
# define cpu_has_mips_2 (cpu_data[0].isa_level & MIPS_CPU_ISA_II)
260
+
# define cpu_has_mips_2 __isa_lt_and_flag(6, MIPS_CPU_ISA_II)
274
261
#endif
275
262
#ifndef cpu_has_mips_3
276
-
# define cpu_has_mips_3 (cpu_data[0].isa_level & MIPS_CPU_ISA_III)
263
+
# define cpu_has_mips_3 __isa_lt_and_flag(6, MIPS_CPU_ISA_III)
277
264
#endif
278
265
#ifndef cpu_has_mips_4
279
-
# define cpu_has_mips_4 (cpu_data[0].isa_level & MIPS_CPU_ISA_IV)
266
+
# define cpu_has_mips_4 __isa_lt_and_flag(6, MIPS_CPU_ISA_IV)
280
267
#endif
281
268
#ifndef cpu_has_mips_5
282
-
# define cpu_has_mips_5 (cpu_data[0].isa_level & MIPS_CPU_ISA_V)
269
+
# define cpu_has_mips_5 __isa_lt_and_flag(6, MIPS_CPU_ISA_V)
283
270
#endif
284
271
#ifndef cpu_has_mips32r1
285
-
# define cpu_has_mips32r1 (cpu_data[0].isa_level & MIPS_CPU_ISA_M32R1)
272
+
# define cpu_has_mips32r1 __isa_range_or_flag(1, 6, MIPS_CPU_ISA_M32R1)
286
273
#endif
287
274
#ifndef cpu_has_mips32r2
288
-
# define cpu_has_mips32r2 (cpu_data[0].isa_level & MIPS_CPU_ISA_M32R2)
275
+
# define cpu_has_mips32r2 __isa_range_or_flag(2, 6, MIPS_CPU_ISA_M32R2)
289
276
#endif
290
277
#ifndef cpu_has_mips32r6
291
-
# define cpu_has_mips32r6 (cpu_data[0].isa_level & MIPS_CPU_ISA_M32R6)
278
+
# define cpu_has_mips32r6 __isa_ge_or_flag(6, MIPS_CPU_ISA_M32R6)
292
279
#endif
293
280
#ifndef cpu_has_mips64r1
294
-
# define cpu_has_mips64r1 (cpu_data[0].isa_level & MIPS_CPU_ISA_M64R1)
281
+
# define cpu_has_mips64r1 __isa_range_or_flag(1, 6, MIPS_CPU_ISA_M64R1)
295
282
#endif
296
283
#ifndef cpu_has_mips64r2
297
-
# define cpu_has_mips64r2 (cpu_data[0].isa_level & MIPS_CPU_ISA_M64R2)
284
+
# define cpu_has_mips64r2 __isa_range_or_flag(2, 6, MIPS_CPU_ISA_M64R2)
298
285
#endif
299
286
#ifndef cpu_has_mips64r6
300
-
# define cpu_has_mips64r6 (cpu_data[0].isa_level & MIPS_CPU_ISA_M64R6)
287
+
# define cpu_has_mips64r6 __isa_ge_and_flag(6, MIPS_CPU_ISA_M64R6)
301
288
#endif
302
289
303
290
/*