tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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cxgb4: get on-chip queue info from FW and create a memory window for them

Get info about the availability of Tx on-chip queues from FW and if they
are supported set up a memory window for them. iw_cxgb4 will be using them.
Move the existing window setup later in the init sequence, after we have
collected the new info.

Signed-off-by: Dimitris Michailidis <dm@chelsio.com>
Signed-off-by: David S. Miller <davem@davemloft.net>

authored by

Dimitris Michailidis and committed by
David S. Miller 1ae970e0 625ac6ae

+29 -2
+22 -2
drivers/net/cxgb4/cxgb4_main.c
··· 2897 2897 t4_write_reg(adap, PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN, 2), 2898 2898 (bar0 + MEMWIN2_BASE) | BIR(0) | 2899 2899 WINDOW(ilog2(MEMWIN2_APERTURE) - 10)); 2900 + if (adap->vres.ocq.size) { 2901 + unsigned int start, sz_kb; 2902 + 2903 + start = pci_resource_start(adap->pdev, 2) + 2904 + OCQ_WIN_OFFSET(adap->pdev, &adap->vres); 2905 + sz_kb = roundup_pow_of_two(adap->vres.ocq.size) >> 10; 2906 + t4_write_reg(adap, 2907 + PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN, 3), 2908 + start | BIR(1) | WINDOW(ilog2(sz_kb))); 2909 + t4_write_reg(adap, 2910 + PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET, 3), 2911 + adap->vres.ocq.start); 2912 + t4_read_reg(adap, 2913 + PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET, 3)); 2914 + } 2900 2915 } 2901 2916 2902 2917 static int adap_init1(struct adapter *adap, struct fw_caps_config_cmd *c) ··· 2969 2954 t4_write_reg(adap, TP_PIO_ADDR, TP_INGRESS_CONFIG); 2970 2955 v = t4_read_reg(adap, TP_PIO_DATA); 2971 2956 t4_write_reg(adap, TP_PIO_DATA, v & ~CSUM_HAS_PSEUDO_HDR); 2972 - setup_memwin(adap); 2973 2957 return 0; 2974 2958 } 2975 2959 ··· 3087 3073 params[1] = FW_PARAM_PFVF(SQRQ_END); 3088 3074 params[2] = FW_PARAM_PFVF(CQ_START); 3089 3075 params[3] = FW_PARAM_PFVF(CQ_END); 3090 - ret = t4_query_params(adap, 0, 0, 0, 4, params, val); 3076 + params[4] = FW_PARAM_PFVF(OCQ_START); 3077 + params[5] = FW_PARAM_PFVF(OCQ_END); 3078 + ret = t4_query_params(adap, 0, 0, 0, 6, params, val); 3091 3079 if (ret < 0) 3092 3080 goto bye; 3093 3081 adap->vres.qp.start = val[0]; 3094 3082 adap->vres.qp.size = val[1] - val[0] + 1; 3095 3083 adap->vres.cq.start = val[2]; 3096 3084 adap->vres.cq.size = val[3] - val[2] + 1; 3085 + adap->vres.ocq.start = val[4]; 3086 + adap->vres.ocq.size = val[5] - val[4] + 1; 3097 3087 } 3098 3088 if (c.iscsicaps) { 3099 3089 params[0] = FW_PARAM_PFVF(ISCSI_START); ··· 3157 3139 } 3158 3140 #endif 3159 3141 3142 + setup_memwin(adap); 3160 3143 return 0; 3161 3144 3162 3145 /* ··· 3240 3221 3241 3222 t4_load_mtus(adap, adap->params.mtus, adap->params.a_wnd, 3242 3223 adap->params.b_wnd); 3224 + setup_memwin(adap); 3243 3225 if (cxgb_up(adap)) 3244 3226 return PCI_ERS_RESULT_DISCONNECT; 3245 3227 return PCI_ERS_RESULT_RECOVERED;
+4
drivers/net/cxgb4/cxgb4_uld.h
··· 187 187 struct cxgb4_range pbl; 188 188 struct cxgb4_range qp; 189 189 struct cxgb4_range cq; 190 + struct cxgb4_range ocq; 190 191 }; 192 + 193 + #define OCQ_WIN_OFFSET(pdev, vres) \ 194 + (pci_resource_len((pdev), 2) - roundup_pow_of_two((vres)->ocq.size)) 191 195 192 196 /* 193 197 * Block of information the LLD provides to ULDs attaching to a device.
+1
drivers/net/cxgb4/t4_regs.h
··· 232 232 #define WINDOW_MASK 0x000000ffU 233 233 #define WINDOW_SHIFT 0 234 234 #define WINDOW(x) ((x) << WINDOW_SHIFT) 235 + #define PCIE_MEM_ACCESS_OFFSET 0x306c 235 236 236 237 #define PCIE_CORE_UTL_SYSTEM_BUS_AGENT_STATUS 0x5908 237 238 #define RNPP 0x80000000U
+2
drivers/net/cxgb4/t4fw_api.h
··· 485 485 FW_PARAMS_PARAM_PFVF_SCHEDCLASS_ETH = 0x20, 486 486 FW_PARAMS_PARAM_PFVF_VIID = 0x24, 487 487 FW_PARAMS_PARAM_PFVF_CPMASK = 0x25, 488 + FW_PARAMS_PARAM_PFVF_OCQ_START = 0x26, 489 + FW_PARAMS_PARAM_PFVF_OCQ_END = 0x27, 488 490 }; 489 491 490 492 /*