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kernel os linux

ARM: dts: rockchip: add power controller for RK3036

Add the power controller node and the correspondending qos nodes for
RK3036.
Also add the power-domain property to the nodes that are already
present.
Note: Since the regiser offsets of the axi interconnect QoS are missing
in the TRM (RK3036 TRM V1.0), they have been taken from vendor kernel.

Signed-off-by: Alex Bee <knaerzche@gmail.com>
Link: https://lore.kernel.org/r/20210527154455.358869-9-knaerzche@gmail.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>

authored by

Alex Bee and committed by
Heiko Stuebner
1a4eb37f 3fedcc63

+50
+50
arch/arm/boot/dts/rk3036.dtsi
··· 6 6 #include <dt-bindings/pinctrl/rockchip.h> 7 7 #include <dt-bindings/clock/rk3036-cru.h> 8 8 #include <dt-bindings/soc/rockchip,boot-mode.h> 9 + #include <dt-bindings/power/rk3036-power.h> 9 10 10 11 / { 11 12 #address-cells = <1>; ··· 112 111 assigned-clock-rates = <100000000>; 113 112 clocks = <&cru SCLK_GPU>, <&cru SCLK_GPU>; 114 113 clock-names = "bus", "core"; 114 + power-domains = <&power RK3036_PD_GPU>; 115 115 resets = <&cru SRST_GPU>; 116 116 status = "disabled"; 117 117 }; ··· 126 124 resets = <&cru SRST_LCDC1_A>, <&cru SRST_LCDC1_H>, <&cru SRST_LCDC1_D>; 127 125 reset-names = "axi", "ahb", "dclk"; 128 126 iommus = <&vop_mmu>; 127 + power-domains = <&power RK3036_PD_VIO>; 129 128 status = "disabled"; 130 129 131 130 vop_out: port { ··· 145 142 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; 146 143 clocks = <&cru ACLK_LCDC>, <&cru HCLK_LCDC>; 147 144 clock-names = "aclk", "iface"; 145 + power-domains = <&power RK3036_PD_VIO>; 148 146 #iommu-cells = <0>; 149 147 status = "disabled"; 148 + }; 149 + 150 + qos_gpu: qos@1012d000 { 151 + compatible = "rockchip,rk3036-qos", "syscon"; 152 + reg = <0x1012d000 0x20>; 153 + }; 154 + 155 + qos_vpu: qos@1012e000 { 156 + compatible = "rockchip,rk3036-qos", "syscon"; 157 + reg = <0x1012e000 0x20>; 158 + }; 159 + 160 + qos_vio: qos@1012f000 { 161 + compatible = "rockchip,rk3036-qos", "syscon"; 162 + reg = <0x1012f000 0x20>; 150 163 }; 151 164 152 165 gic: interrupt-controller@10139000 { ··· 319 300 grf: syscon@20008000 { 320 301 compatible = "rockchip,rk3036-grf", "syscon", "simple-mfd"; 321 302 reg = <0x20008000 0x1000>; 303 + 304 + power: power-controller { 305 + compatible = "rockchip,rk3036-power-controller"; 306 + #power-domain-cells = <1>; 307 + #address-cells = <1>; 308 + #size-cells = <0>; 309 + 310 + power-domain@RK3036_PD_VIO { 311 + reg = <RK3036_PD_VIO>; 312 + clocks = <&cru ACLK_LCDC>, 313 + <&cru HCLK_LCDC>, 314 + <&cru SCLK_LCDC>; 315 + pm_qos = <&qos_vio>; 316 + #power-domain-cells = <0>; 317 + }; 318 + 319 + power-domain@RK3036_PD_VPU { 320 + reg = <RK3036_PD_VPU>; 321 + clocks = <&cru ACLK_VCODEC>, 322 + <&cru HCLK_VCODEC>; 323 + pm_qos = <&qos_vpu>; 324 + #power-domain-cells = <0>; 325 + }; 326 + 327 + power-domain@RK3036_PD_GPU { 328 + reg = <RK3036_PD_GPU>; 329 + clocks = <&cru SCLK_GPU>; 330 + pm_qos = <&qos_gpu>; 331 + #power-domain-cells = <0>; 332 + }; 333 + }; 322 334 323 335 reboot-mode { 324 336 compatible = "syscon-reboot-mode";