tjh.dev / kernel
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ARM: proc-*.S: place cpu_reset functions into .idmap.text section

The CPU reset functions disable the MMU and therefore must be executed
with an identity mapping in place.

This patch places the CPU reset functions into the .idmap.text section,
causing the idmap code to include them as part of the identity mapping.

Acked-by: Dave Martin <dave.martin@linaro.org>
Signed-off-by: Will Deacon <will.deacon@arm.com>

Will Deacon 1a4baafa e6eadc67

+72
+3
arch/arm/mm/proc-arm1020.S
··· 95 95 * loc: location to jump to for soft reset 96 96 */ 97 97 .align 5 98 + .pushsection .idmap.text, "ax" 98 99 ENTRY(cpu_arm1020_reset) 99 100 mov ip, #0 100 101 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches ··· 108 107 bic ip, ip, #0x1100 @ ...i...s........ 109 108 mcr p15, 0, ip, c1, c0, 0 @ ctrl register 110 109 mov pc, r0 110 + ENDPROC(cpu_arm1020_reset) 111 + .popsection 111 112 112 113 /* 113 114 * cpu_arm1020_do_idle()
+3
arch/arm/mm/proc-arm1020e.S
··· 95 95 * loc: location to jump to for soft reset 96 96 */ 97 97 .align 5 98 + .pushsection .idmap.text, "ax" 98 99 ENTRY(cpu_arm1020e_reset) 99 100 mov ip, #0 100 101 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches ··· 108 107 bic ip, ip, #0x1100 @ ...i...s........ 109 108 mcr p15, 0, ip, c1, c0, 0 @ ctrl register 110 109 mov pc, r0 110 + ENDPROC(cpu_arm1020e_reset) 111 + .popsection 111 112 112 113 /* 113 114 * cpu_arm1020e_do_idle()
+3
arch/arm/mm/proc-arm1022.S
··· 84 84 * loc: location to jump to for soft reset 85 85 */ 86 86 .align 5 87 + .pushsection .idmap.text, "ax" 87 88 ENTRY(cpu_arm1022_reset) 88 89 mov ip, #0 89 90 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches ··· 97 96 bic ip, ip, #0x1100 @ ...i...s........ 98 97 mcr p15, 0, ip, c1, c0, 0 @ ctrl register 99 98 mov pc, r0 99 + ENDPROC(cpu_arm1022_reset) 100 + .popsection 100 101 101 102 /* 102 103 * cpu_arm1022_do_idle()
+3
arch/arm/mm/proc-arm1026.S
··· 84 84 * loc: location to jump to for soft reset 85 85 */ 86 86 .align 5 87 + .pushsection .idmap.text, "ax" 87 88 ENTRY(cpu_arm1026_reset) 88 89 mov ip, #0 89 90 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches ··· 97 96 bic ip, ip, #0x1100 @ ...i...s........ 98 97 mcr p15, 0, ip, c1, c0, 0 @ ctrl register 99 98 mov pc, r0 99 + ENDPROC(cpu_arm1026_reset) 100 + .popsection 100 101 101 102 /* 102 103 * cpu_arm1026_do_idle()
+4
arch/arm/mm/proc-arm6_7.S
··· 225 225 * Params : r0 = address to jump to 226 226 * Notes : This sets up everything for a reset 227 227 */ 228 + .pushsection .idmap.text, "ax" 228 229 ENTRY(cpu_arm6_reset) 229 230 ENTRY(cpu_arm7_reset) 230 231 mov r1, #0 ··· 236 235 mov r1, #0x30 237 236 mcr p15, 0, r1, c1, c0, 0 @ turn off MMU etc 238 237 mov pc, r0 238 + ENDPROC(cpu_arm6_reset) 239 + ENDPROC(cpu_arm7_reset) 240 + .popsection 239 241 240 242 __CPUINIT 241 243
+3
arch/arm/mm/proc-arm720.S
··· 101 101 * Params : r0 = address to jump to 102 102 * Notes : This sets up everything for a reset 103 103 */ 104 + .pushsection .idmap.text, "ax" 104 105 ENTRY(cpu_arm720_reset) 105 106 mov ip, #0 106 107 mcr p15, 0, ip, c7, c7, 0 @ invalidate cache ··· 113 112 bic ip, ip, #0x2100 @ ..v....s........ 114 113 mcr p15, 0, ip, c1, c0, 0 @ ctrl register 115 114 mov pc, r0 115 + ENDPROC(cpu_arm720_reset) 116 + .popsection 116 117 117 118 __CPUINIT 118 119
+3
arch/arm/mm/proc-arm740.S
··· 49 49 * Params : r0 = address to jump to 50 50 * Notes : This sets up everything for a reset 51 51 */ 52 + .pushsection .idmap.text, "ax" 52 53 ENTRY(cpu_arm740_reset) 53 54 mov ip, #0 54 55 mcr p15, 0, ip, c7, c0, 0 @ invalidate cache ··· 57 56 bic ip, ip, #0x0000000c @ ............wc.. 58 57 mcr p15, 0, ip, c1, c0, 0 @ ctrl register 59 58 mov pc, r0 59 + ENDPROC(cpu_arm740_reset) 60 + .popsection 60 61 61 62 __CPUINIT 62 63
+3
arch/arm/mm/proc-arm7tdmi.S
··· 45 45 * Params : loc(r0) address to jump to 46 46 * Purpose : Sets up everything for a reset and jump to the location for soft reset. 47 47 */ 48 + .pushsection .idmap.text, "ax" 48 49 ENTRY(cpu_arm7tdmi_reset) 49 50 mov pc, r0 51 + ENDPROC(cpu_arm7tdmi_reset) 52 + .popsection 50 53 51 54 __CPUINIT 52 55
+3
arch/arm/mm/proc-arm920.S
··· 85 85 * loc: location to jump to for soft reset 86 86 */ 87 87 .align 5 88 + .pushsection .idmap.text, "ax" 88 89 ENTRY(cpu_arm920_reset) 89 90 mov ip, #0 90 91 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches ··· 98 97 bic ip, ip, #0x1100 @ ...i...s........ 99 98 mcr p15, 0, ip, c1, c0, 0 @ ctrl register 100 99 mov pc, r0 100 + ENDPROC(cpu_arm920_reset) 101 + .popsection 101 102 102 103 /* 103 104 * cpu_arm920_do_idle()
+3
arch/arm/mm/proc-arm922.S
··· 87 87 * loc: location to jump to for soft reset 88 88 */ 89 89 .align 5 90 + .pushsection .idmap.text, "ax" 90 91 ENTRY(cpu_arm922_reset) 91 92 mov ip, #0 92 93 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches ··· 100 99 bic ip, ip, #0x1100 @ ...i...s........ 101 100 mcr p15, 0, ip, c1, c0, 0 @ ctrl register 102 101 mov pc, r0 102 + ENDPROC(cpu_arm922_reset) 103 + .popsection 103 104 104 105 /* 105 106 * cpu_arm922_do_idle()
+3
arch/arm/mm/proc-arm925.S
··· 108 108 * loc: location to jump to for soft reset 109 109 */ 110 110 .align 5 111 + .pushsection .idmap.text, "ax" 111 112 ENTRY(cpu_arm925_reset) 112 113 /* Send software reset to MPU and DSP */ 113 114 mov ip, #0xff000000 ··· 116 115 orr ip, ip, #0x0000ce00 117 116 mov r4, #1 118 117 strh r4, [ip, #0x10] 118 + ENDPROC(cpu_arm925_reset) 119 + .popsection 119 120 120 121 mov ip, #0 121 122 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
+3
arch/arm/mm/proc-arm926.S
··· 77 77 * loc: location to jump to for soft reset 78 78 */ 79 79 .align 5 80 + .pushsection .idmap.text, "ax" 80 81 ENTRY(cpu_arm926_reset) 81 82 mov ip, #0 82 83 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches ··· 90 89 bic ip, ip, #0x1100 @ ...i...s........ 91 90 mcr p15, 0, ip, c1, c0, 0 @ ctrl register 92 91 mov pc, r0 92 + ENDPROC(cpu_arm926_reset) 93 + .popsection 93 94 94 95 /* 95 96 * cpu_arm926_do_idle()
+3
arch/arm/mm/proc-arm940.S
··· 48 48 * Params : r0 = address to jump to 49 49 * Notes : This sets up everything for a reset 50 50 */ 51 + .pushsection .idmap.text, "ax" 51 52 ENTRY(cpu_arm940_reset) 52 53 mov ip, #0 53 54 mcr p15, 0, ip, c7, c5, 0 @ flush I cache ··· 59 58 bic ip, ip, #0x00001000 @ i-cache 60 59 mcr p15, 0, ip, c1, c0, 0 @ ctrl register 61 60 mov pc, r0 61 + ENDPROC(cpu_arm940_reset) 62 + .popsection 62 63 63 64 /* 64 65 * cpu_arm940_do_idle()
+3
arch/arm/mm/proc-arm946.S
··· 55 55 * Params : r0 = address to jump to 56 56 * Notes : This sets up everything for a reset 57 57 */ 58 + .pushsection .idmap.text, "ax" 58 59 ENTRY(cpu_arm946_reset) 59 60 mov ip, #0 60 61 mcr p15, 0, ip, c7, c5, 0 @ flush I cache ··· 66 65 bic ip, ip, #0x00001000 @ i-cache 67 66 mcr p15, 0, ip, c1, c0, 0 @ ctrl register 68 67 mov pc, r0 68 + ENDPROC(cpu_arm946_reset) 69 + .popsection 69 70 70 71 /* 71 72 * cpu_arm946_do_idle()
+3
arch/arm/mm/proc-arm9tdmi.S
··· 45 45 * Params : loc(r0) address to jump to 46 46 * Purpose : Sets up everything for a reset and jump to the location for soft reset. 47 47 */ 48 + .pushsection .idmap.text, "ax" 48 49 ENTRY(cpu_arm9tdmi_reset) 49 50 mov pc, r0 51 + ENDPROC(cpu_arm9tdmi_reset) 52 + .popsection 50 53 51 54 __CPUINIT 52 55
+3
arch/arm/mm/proc-fa526.S
··· 57 57 * loc: location to jump to for soft reset 58 58 */ 59 59 .align 4 60 + .pushsection .idmap.text, "ax" 60 61 ENTRY(cpu_fa526_reset) 61 62 /* TODO: Use CP8 if possible... */ 62 63 mov ip, #0 ··· 74 73 nop 75 74 nop 76 75 mov pc, r0 76 + ENDPROC(cpu_fa526_reset) 77 + .popsection 77 78 78 79 /* 79 80 * cpu_fa526_do_idle()
+3
arch/arm/mm/proc-feroceon.S
··· 98 98 * loc: location to jump to for soft reset 99 99 */ 100 100 .align 5 101 + .pushsection .idmap.text, "ax" 101 102 ENTRY(cpu_feroceon_reset) 102 103 mov ip, #0 103 104 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches ··· 111 110 bic ip, ip, #0x1100 @ ...i...s........ 112 111 mcr p15, 0, ip, c1, c0, 0 @ ctrl register 113 112 mov pc, r0 113 + ENDPROC(cpu_feroceon_reset) 114 + .popsection 114 115 115 116 /* 116 117 * cpu_feroceon_do_idle()
+3
arch/arm/mm/proc-mohawk.S
··· 69 69 * (same as arm926) 70 70 */ 71 71 .align 5 72 + .pushsection .idmap.text, "ax" 72 73 ENTRY(cpu_mohawk_reset) 73 74 mov ip, #0 74 75 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches ··· 80 79 bic ip, ip, #0x1100 @ ...i...s........ 81 80 mcr p15, 0, ip, c1, c0, 0 @ ctrl register 82 81 mov pc, r0 82 + ENDPROC(cpu_mohawk_reset) 83 + .popsection 83 84 84 85 /* 85 86 * cpu_mohawk_do_idle()
+3
arch/arm/mm/proc-sa110.S
··· 62 62 * loc: location to jump to for soft reset 63 63 */ 64 64 .align 5 65 + .pushsection .idmap.text, "ax" 65 66 ENTRY(cpu_sa110_reset) 66 67 mov ip, #0 67 68 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches ··· 75 74 bic ip, ip, #0x1100 @ ...i...s........ 76 75 mcr p15, 0, ip, c1, c0, 0 @ ctrl register 77 76 mov pc, r0 77 + ENDPROC(cpu_sa110_reset) 78 + .popsection 78 79 79 80 /* 80 81 * cpu_sa110_do_idle(type)
+3
arch/arm/mm/proc-sa1100.S
··· 70 70 * loc: location to jump to for soft reset 71 71 */ 72 72 .align 5 73 + .pushsection .idmap.text, "ax" 73 74 ENTRY(cpu_sa1100_reset) 74 75 mov ip, #0 75 76 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches ··· 83 82 bic ip, ip, #0x1100 @ ...i...s........ 84 83 mcr p15, 0, ip, c1, c0, 0 @ ctrl register 85 84 mov pc, r0 85 + ENDPROC(cpu_sa1100_reset) 86 + .popsection 86 87 87 88 /* 88 89 * cpu_sa1100_do_idle(type)
+3
arch/arm/mm/proc-v6.S
··· 55 55 * - loc - location to jump to for soft reset 56 56 */ 57 57 .align 5 58 + .pushsection .idmap.text, "ax" 58 59 ENTRY(cpu_v6_reset) 59 60 mrc p15, 0, r1, c1, c0, 0 @ ctrl register 60 61 bic r1, r1, #0x1 @ ...............m ··· 63 62 mov r1, #0 64 63 mcr p15, 0, r1, c7, c5, 4 @ ISB 65 64 mov pc, r0 65 + ENDPROC(cpu_v6_reset) 66 + .popsection 66 67 67 68 /* 68 69 * cpu_v6_do_idle()
+2
arch/arm/mm/proc-v7.S
··· 63 63 * caches disabled. 64 64 */ 65 65 .align 5 66 + .pushsection .idmap.text, "ax" 66 67 ENTRY(cpu_v7_reset) 67 68 mrc p15, 0, r1, c1, c0, 0 @ ctrl register 68 69 bic r1, r1, #0x1 @ ...............m ··· 72 71 isb 73 72 mov pc, r0 74 73 ENDPROC(cpu_v7_reset) 74 + .popsection 75 75 76 76 /* 77 77 * cpu_v7_do_idle()
+3
arch/arm/mm/proc-xsc3.S
··· 105 105 * loc: location to jump to for soft reset 106 106 */ 107 107 .align 5 108 + .pushsection .idmap.text, "ax" 108 109 ENTRY(cpu_xsc3_reset) 109 110 mov r1, #PSR_F_BIT|PSR_I_BIT|SVC_MODE 110 111 msr cpsr_c, r1 @ reset CPSR ··· 120 119 @ already containing those two last instructions to survive. 121 120 mcr p15, 0, ip, c8, c7, 0 @ invalidate I and D TLBs 122 121 mov pc, r0 122 + ENDPROC(cpu_xsc3_reset) 123 + .popsection 123 124 124 125 /* 125 126 * cpu_xsc3_do_idle()
+3
arch/arm/mm/proc-xscale.S
··· 142 142 * Beware PXA270 erratum E7. 143 143 */ 144 144 .align 5 145 + .pushsection .idmap.text, "ax" 145 146 ENTRY(cpu_xscale_reset) 146 147 mov r1, #PSR_F_BIT|PSR_I_BIT|SVC_MODE 147 148 msr cpsr_c, r1 @ reset CPSR ··· 161 160 @ already containing those two last instructions to survive. 162 161 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 163 162 mov pc, r0 163 + ENDPROC(cpu_xscale_reset) 164 + .popsection 164 165 165 166 /* 166 167 * cpu_xscale_do_idle()