Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux

drm/dsc: Define VESA Display Stream Compression Capabilities

This defines all the DSC parameters as per the VESA DSC spec
that will be required for DSC encoder/decoder

v6: (From Manasi)
* Add a bit mask for RANGE_BPG_OFFSET for 6 bits(Manasi)
v5 (From Manasi)
* Add the RC constants as per the spec
v4 (From Manasi)
* Add the DSC_MUX_WORD_SIZE constants (Manasi)

v3 (From Manasi)
* Remove the duplicate define (Suggested By:Harry Wentland)

v2: Define this struct in DRM (From Manasi)
* Changed the data types to u8/u16 instead of unsigned longs (Manasi)
* Remove driver specific fields (Manasi)
* Move this struct definition to DRM (Manasi)
* Define DSC 1.2 parameters (Manasi)
* Use DSC_NUM_BUF_RANGES (Manasi)
* Call it drm_dsc_config (Manasi)

Cc: dri-devel@lists.freedesktop.org
Cc: Jani Nikula <jani.nikula@linux.intel.com>
Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
Cc: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
Signed-off-by: Gaurav K Singh <gaurav.k.singh@intel.com>
Co-developed-by: Gaurav K Singh <gaurav.k.singh@intel.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Acked-by: Sean Paul <seanpaul@chromium.org> (For merging through
drm-intel)
Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20181127214125.17658-3-manasi.d.navare@intel.com

+114 -1
+114 -1
include/drm/drm_dsc.h
··· 11 11 #include <drm/drm_dp_helper.h> 12 12 13 13 /* VESA Display Stream Compression DSC 1.2 constants */ 14 - #define DSC_NUM_BUF_RANGES 15 14 + #define DSC_NUM_BUF_RANGES 15 15 + #define DSC_MUX_WORD_SIZE_8_10_BPC 48 16 + #define DSC_MUX_WORD_SIZE_12_BPC 64 17 + #define DSC_RC_PIXELS_PER_GROUP 3 18 + #define DSC_SCALE_DECREMENT_INTERVAL_MAX 4095 19 + #define DSC_RANGE_BPG_OFFSET_MASK 0x3f 20 + 21 + /* Configuration for a single Rate Control model range */ 22 + struct drm_dsc_rc_range_parameters { 23 + /* Min Quantization Parameters allowed for this range */ 24 + u8 range_min_qp; 25 + /* Max Quantization Parameters allowed for this range */ 26 + u8 range_max_qp; 27 + /* Bits/group offset to apply to target for this group */ 28 + u8 range_bpg_offset; 29 + }; 30 + 31 + struct drm_dsc_config { 32 + /* Bits / component for previous reconstructed line buffer */ 33 + u8 line_buf_depth; 34 + /* Bits per component to code (must be 8, 10, or 12) */ 35 + u8 bits_per_component; 36 + /* 37 + * Flag indicating to do RGB - YCoCg conversion 38 + * and back (should be 1 for RGB input) 39 + */ 40 + bool convert_rgb; 41 + u8 slice_count; 42 + /* Slice Width */ 43 + u16 slice_width; 44 + /* Slice Height */ 45 + u16 slice_height; 46 + /* 47 + * 4:2:2 enable mode (from PPS, 4:2:2 conversion happens 48 + * outside of DSC encode/decode algorithm) 49 + */ 50 + bool enable422; 51 + /* Picture Width */ 52 + u16 pic_width; 53 + /* Picture Height */ 54 + u16 pic_height; 55 + /* Offset to bits/group used by RC to determine QP adjustment */ 56 + u8 rc_tgt_offset_high; 57 + /* Offset to bits/group used by RC to determine QP adjustment */ 58 + u8 rc_tgt_offset_low; 59 + /* Bits/pixel target << 4 (ie., 4 fractional bits) */ 60 + u16 bits_per_pixel; 61 + /* 62 + * Factor to determine if an edge is present based 63 + * on the bits produced 64 + */ 65 + u8 rc_edge_factor; 66 + /* Slow down incrementing once the range reaches this value */ 67 + u8 rc_quant_incr_limit1; 68 + /* Slow down incrementing once the range reaches this value */ 69 + u8 rc_quant_incr_limit0; 70 + /* Number of pixels to delay the initial transmission */ 71 + u16 initial_xmit_delay; 72 + /* Number of pixels to delay the VLD on the decoder,not including SSM */ 73 + u16 initial_dec_delay; 74 + /* Block prediction enable */ 75 + bool block_pred_enable; 76 + /* Bits/group offset to use for first line of the slice */ 77 + u8 first_line_bpg_offset; 78 + /* Value to use for RC model offset at slice start */ 79 + u16 initial_offset; 80 + /* Thresholds defining each of the buffer ranges */ 81 + u16 rc_buf_thresh[DSC_NUM_BUF_RANGES - 1]; 82 + /* Parameters for each of the RC ranges */ 83 + struct drm_dsc_rc_range_parameters rc_range_params[DSC_NUM_BUF_RANGES]; 84 + /* Total size of RC model */ 85 + u16 rc_model_size; 86 + /* Minimum QP where flatness information is sent */ 87 + u8 flatness_min_qp; 88 + /* Maximum QP where flatness information is sent */ 89 + u8 flatness_max_qp; 90 + /* Initial value for scale factor */ 91 + u8 initial_scale_value; 92 + /* Decrement scale factor every scale_decrement_interval groups */ 93 + u16 scale_decrement_interval; 94 + /* Increment scale factor every scale_increment_interval groups */ 95 + u16 scale_increment_interval; 96 + /* Non-first line BPG offset to use */ 97 + u16 nfl_bpg_offset; 98 + /* BPG offset used to enforce slice bit */ 99 + u16 slice_bpg_offset; 100 + /* Final RC linear transformation offset value */ 101 + u16 final_offset; 102 + /* Enable on-off VBR (ie., disable stuffing bits) */ 103 + bool vbr_enable; 104 + /* Mux word size (in bits) for SSM mode */ 105 + u8 mux_word_size; 106 + /* 107 + * The (max) size in bytes of the "chunks" that are 108 + * used in slice multiplexing 109 + */ 110 + u16 slice_chunk_size; 111 + /* Rate Control buffer siz in bits */ 112 + u16 rc_bits; 113 + /* DSC Minor Version */ 114 + u8 dsc_version_minor; 115 + /* DSC Major version */ 116 + u8 dsc_version_major; 117 + /* Native 4:2:2 support */ 118 + bool native_422; 119 + /* Native 4:2:0 support */ 120 + bool native_420; 121 + /* Additional bits/grp for seconnd line of slice for native 4:2:0 */ 122 + u8 second_line_bpg_offset; 123 + /* Num of bits deallocated for each grp that is not in second line of slice */ 124 + u16 nsl_bpg_offset; 125 + /* Offset adj fr second line in Native 4:2:0 mode */ 126 + u16 second_line_offset_adj; 127 + }; 15 128 16 129 /** 17 130 * struct picture_parameter_set - Represents 128 bytes of Picture Parameter Set