Merge branches 'x86-build-for-linus', 'x86-cleanups-for-linus' and 'x86-debug-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip

+3 -6

arch/x86/Makefile

··· 15 15 # that way we can complain to the user if the CPU is insufficient. 16 16 # 17 17 # The -m16 option is supported by GCC >= 4.9 and clang >= 3.5. For 18 - # older versions of GCC, we need to play evil and unreliable tricks to 19 - # attempt to ensure that our asm(".code16gcc") is first in the asm 20 - # output. 21 - CODE16GCC_CFLAGS := -m32 -include $(srctree)/arch/x86/boot/code16gcc.h \ 22 - $(call cc-option, -fno-toplevel-reorder,\ 23 - $(call cc-option, -fno-unit-at-a-time)) 18 + # older versions of GCC, include an *assembly* header to make sure that 19 + # gcc doesn't play any games behind our back. 20 + CODE16GCC_CFLAGS := -m32 -Wa,$(srctree)/arch/x86/boot/code16gcc.h 24 21 M16_CFLAGS := $(call cc-option, -m16, $(CODE16GCC_CFLAGS)) 25 22 26 23 REALMODE_CFLAGS := $(M16_CFLAGS) -g -Os -D__KERNEL__ \

+10 -14

arch/x86/boot/code16gcc.h

··· 1 - /* 2 - * code16gcc.h 3 - * 4 - * This file is -include'd when compiling 16-bit C code. 5 - * Note: this asm() needs to be emitted before gcc emits any code. 6 - * Depending on gcc version, this requires -fno-unit-at-a-time or 7 - * -fno-toplevel-reorder. 8 - * 9 - * Hopefully gcc will eventually have a real -m16 option so we can 10 - * drop this hack long term. 11 - */ 1 + # 2 + # code16gcc.h 3 + # 4 + # This file is added to the assembler via -Wa when compiling 16-bit C code. 5 + # This is done this way instead via asm() to make sure gcc does not reorder 6 + # things around us. 7 + # 8 + # gcc 4.9+ has a real -m16 option so we can drop this hack long term. 9 + # 12 10 13 - #ifndef __ASSEMBLY__ 14 - asm(".code16gcc"); 15 - #endif 11 + .code16gcc

+2 -2

arch/x86/include/asm/cmpxchg.h

··· 4 4 #include <linux/compiler.h> 5 5 #include <asm/alternative.h> /* Provides LOCK_PREFIX */ 6 6 7 + #define __HAVE_ARCH_CMPXCHG 1 8 + 7 9 /* 8 10 * Non-existant functions to indicate usage errors at link time 9 11 * (or compile-time if the compiler implements __compiletime_error(). ··· 145 143 # include <asm/cmpxchg_64.h> 146 144 #endif 147 145 148 - #ifdef __HAVE_ARCH_CMPXCHG 149 146 #define cmpxchg(ptr, old, new) \ 150 147 __cmpxchg(ptr, old, new, sizeof(*(ptr))) 151 148 ··· 153 152 154 153 #define cmpxchg_local(ptr, old, new) \ 155 154 __cmpxchg_local(ptr, old, new, sizeof(*(ptr))) 156 - #endif 157 155 158 156 /* 159 157 * xadd() adds "inc" to "*ptr" and atomically returns the previous

-2

arch/x86/include/asm/cmpxchg_32.h

··· 34 34 : "memory"); 35 35 } 36 36 37 - #define __HAVE_ARCH_CMPXCHG 1 38 - 39 37 #ifdef CONFIG_X86_CMPXCHG64 40 38 #define cmpxchg64(ptr, o, n) \ 41 39 ((__typeof__(*(ptr)))__cmpxchg64((ptr), (unsigned long long)(o), \

-2

arch/x86/include/asm/cmpxchg_64.h

··· 6 6 *ptr = val; 7 7 } 8 8 9 - #define __HAVE_ARCH_CMPXCHG 1 10 - 11 9 #define cmpxchg64(ptr, o, n) \ 12 10 ({ \ 13 11 BUILD_BUG_ON(sizeof(*(ptr)) != 8); \

+1 -1

arch/x86/include/asm/mc146818rtc.h

··· 13 13 #define RTC_ALWAYS_BCD 1 /* RTC operates in binary mode */ 14 14 #endif 15 15 16 - #if defined(CONFIG_X86_32) && defined(__HAVE_ARCH_CMPXCHG) 16 + #if defined(CONFIG_X86_32) 17 17 /* 18 18 * This lock provides nmi access to the CMOS/RTC registers. It has some 19 19 * special properties. It is owned by a CPU and stores the index register

+2 -14

arch/x86/include/asm/mutex_32.h

··· 100 100 static inline int __mutex_fastpath_trylock(atomic_t *count, 101 101 int (*fail_fn)(atomic_t *)) 102 102 { 103 - /* 104 - * We have two variants here. The cmpxchg based one is the best one 105 - * because it never induce a false contention state. It is included 106 - * here because architectures using the inc/dec algorithms over the 107 - * xchg ones are much more likely to support cmpxchg natively. 108 - * 109 - * If not we fall back to the spinlock based variant - that is 110 - * just as efficient (and simpler) as a 'destructive' probing of 111 - * the mutex state would be. 112 - */ 113 - #ifdef __HAVE_ARCH_CMPXCHG 103 + /* cmpxchg because it never induces a false contention state. */ 114 104 if (likely(atomic_cmpxchg(count, 1, 0) == 1)) 115 105 return 1; 106 + 116 107 return 0; 117 - #else 118 - return fail_fn(count); 119 - #endif 120 108 } 121 109 122 110 #endif /* _ASM_X86_MUTEX_32_H */

-4

arch/x86/kernel/acpi/boot.c

··· 74 74 static u64 acpi_lapic_addr __initdata = APIC_DEFAULT_PHYS_BASE; 75 75 #endif 76 76 77 - #ifndef __HAVE_ARCH_CMPXCHG 78 - #warning ACPI uses CMPXCHG, i486 and later hardware 79 - #endif 80 - 81 77 /* -------------------------------------------------------------------------- 82 78 Boot-time Configuration 83 79 -------------------------------------------------------------------------- */

+26 -26

arch/x86/kernel/entry_64.S

··· 207 207 */ 208 208 .macro XCPT_FRAME start=1 offset=0 209 209 INTR_FRAME \start, RIP+\offset-ORIG_RAX 210 - /*CFI_REL_OFFSET orig_rax, ORIG_RAX-ORIG_RAX*/ 211 210 .endm 212 211 213 212 /* ··· 286 287 ENTRY(save_paranoid) 287 288 XCPT_FRAME 1 RDI+8 288 289 cld 289 - movq_cfi rdi, RDI+8 290 - movq_cfi rsi, RSI+8 290 + movq %rdi, RDI+8(%rsp) 291 + movq %rsi, RSI+8(%rsp) 291 292 movq_cfi rdx, RDX+8 292 293 movq_cfi rcx, RCX+8 293 294 movq_cfi rax, RAX+8 294 - movq_cfi r8, R8+8 295 - movq_cfi r9, R9+8 296 - movq_cfi r10, R10+8 297 - movq_cfi r11, R11+8 295 + movq %r8, R8+8(%rsp) 296 + movq %r9, R9+8(%rsp) 297 + movq %r10, R10+8(%rsp) 298 + movq %r11, R11+8(%rsp) 298 299 movq_cfi rbx, RBX+8 299 - movq_cfi rbp, RBP+8 300 - movq_cfi r12, R12+8 301 - movq_cfi r13, R13+8 302 - movq_cfi r14, R14+8 303 - movq_cfi r15, R15+8 300 + movq %rbp, RBP+8(%rsp) 301 + movq %r12, R12+8(%rsp) 302 + movq %r13, R13+8(%rsp) 303 + movq %r14, R14+8(%rsp) 304 + movq %r15, R15+8(%rsp) 304 305 movl $1,%ebx 305 306 movl $MSR_GS_BASE,%ecx 306 307 rdmsr ··· 1386 1387 CFI_ADJUST_CFA_OFFSET 15*8 1387 1388 /* oldrax contains error code */ 1388 1389 cld 1389 - movq_cfi rdi, RDI+8 1390 - movq_cfi rsi, RSI+8 1391 - movq_cfi rdx, RDX+8 1392 - movq_cfi rcx, RCX+8 1393 - movq_cfi rax, RAX+8 1394 - movq_cfi r8, R8+8 1395 - movq_cfi r9, R9+8 1396 - movq_cfi r10, R10+8 1397 - movq_cfi r11, R11+8 1390 + movq %rdi, RDI+8(%rsp) 1391 + movq %rsi, RSI+8(%rsp) 1392 + movq %rdx, RDX+8(%rsp) 1393 + movq %rcx, RCX+8(%rsp) 1394 + movq %rax, RAX+8(%rsp) 1395 + movq %r8, R8+8(%rsp) 1396 + movq %r9, R9+8(%rsp) 1397 + movq %r10, R10+8(%rsp) 1398 + movq %r11, R11+8(%rsp) 1398 1399 movq_cfi rbx, RBX+8 1399 - movq_cfi rbp, RBP+8 1400 - movq_cfi r12, R12+8 1401 - movq_cfi r13, R13+8 1402 - movq_cfi r14, R14+8 1403 - movq_cfi r15, R15+8 1400 + movq %rbp, RBP+8(%rsp) 1401 + movq %r12, R12+8(%rsp) 1402 + movq %r13, R13+8(%rsp) 1403 + movq %r14, R14+8(%rsp) 1404 + movq %r15, R15+8(%rsp) 1404 1405 xorl %ebx,%ebx 1405 1406 testl $3,CS+8(%rsp) 1406 1407 je error_kernelspace ··· 1418 1419 * compat mode. Check for these here too. 1419 1420 */ 1420 1421 error_kernelspace: 1422 + CFI_REL_OFFSET rcx, RCX+8 1421 1423 incl %ebx 1422 1424 leaq native_irq_return_iret(%rip),%rcx 1423 1425 cmpq %rcx,RIP+8(%rsp)

+3 -4

arch/x86/kernel/tsc.c

··· 234 234 return ns; 235 235 } 236 236 237 - /* XXX surely we already have this someplace in the kernel?! */ 238 - #define DIV_ROUND(n, d) (((n) + ((d) / 2)) / (d)) 239 - 240 237 static void set_cyc2ns_scale(unsigned long cpu_khz, int cpu) 241 238 { 242 239 unsigned long long tsc_now, ns_now; ··· 256 259 * time function is continuous; see the comment near struct 257 260 * cyc2ns_data. 258 261 */ 259 - data->cyc2ns_mul = DIV_ROUND(NSEC_PER_MSEC << CYC2NS_SCALE_FACTOR, cpu_khz); 262 + data->cyc2ns_mul = 263 + DIV_ROUND_CLOSEST(NSEC_PER_MSEC << CYC2NS_SCALE_FACTOR, 264 + cpu_khz); 260 265 data->cyc2ns_shift = CYC2NS_SCALE_FACTOR; 261 266 data->cyc2ns_offset = ns_now - 262 267 mul_u64_u32_shr(tsc_now, data->cyc2ns_mul, CYC2NS_SCALE_FACTOR);