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drm/amdgpu: use proper defines, shifts and masks in DCE6 code

By replacing VGA_VSTATUS_CNTL by VGA_RENDER_CONTROL__VGA_VSTATUS_CNTL_MASK,
we also need to fix its usage in GMC6.

Note: VGA_VSTATUS_CNTL's binary value was inverted in dce_6_0_sh_mask.h,
so we need to invert its value where it was used.

Signed-off-by: Alexandre Demers <alexandre.f.demers@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

authored by

Alexandre Demers and committed by
Alex Deucher 193e0880 de81b86e

+12 -35
+9 -9
drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
··· 412 412 { 413 413 if (!render) 414 414 WREG32(mmVGA_RENDER_CONTROL, 415 - RREG32(mmVGA_RENDER_CONTROL) & VGA_VSTATUS_CNTL); 415 + RREG32(mmVGA_RENDER_CONTROL) & ~VGA_RENDER_CONTROL__VGA_VSTATUS_CNTL_MASK); 416 416 } 417 417 418 418 static int dce_v6_0_get_num_crtc(struct amdgpu_device *adev) ··· 2108 2108 2109 2109 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 2110 2110 WREG32(mmDATA_FORMAT + amdgpu_crtc->crtc_offset, 2111 - INTERLEAVE_EN); 2111 + DATA_FORMAT__INTERLEAVE_EN_MASK); 2112 2112 else 2113 2113 WREG32(mmDATA_FORMAT + amdgpu_crtc->crtc_offset, 0); 2114 2114 } ··· 2162 2162 WREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset, 2163 2163 ((0 << DEGAMMA_CONTROL__GRPH_DEGAMMA_MODE__SHIFT) | 2164 2164 (0 << DEGAMMA_CONTROL__OVL_DEGAMMA_MODE__SHIFT) | 2165 - ICON_DEGAMMA_MODE(0) | 2165 + (0 << DEGAMMA_CONTROL__ICON_DEGAMMA_MODE__SHIFT) | 2166 2166 (0 << DEGAMMA_CONTROL__CURSOR_DEGAMMA_MODE__SHIFT))); 2167 2167 WREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset, 2168 2168 ((0 << GAMUT_REMAP_CONTROL__GRPH_GAMUT_REMAP_MODE__SHIFT) | ··· 2986 2986 switch (state) { 2987 2987 case AMDGPU_IRQ_STATE_DISABLE: 2988 2988 interrupt_mask = RREG32(mmINT_MASK + reg_block); 2989 - interrupt_mask &= ~VBLANK_INT_MASK; 2989 + interrupt_mask &= ~INT_MASK__VBLANK_INT_MASK; 2990 2990 WREG32(mmINT_MASK + reg_block, interrupt_mask); 2991 2991 break; 2992 2992 case AMDGPU_IRQ_STATE_ENABLE: 2993 2993 interrupt_mask = RREG32(mmINT_MASK + reg_block); 2994 - interrupt_mask |= VBLANK_INT_MASK; 2994 + interrupt_mask |= INT_MASK__VBLANK_INT_MASK; 2995 2995 WREG32(mmINT_MASK + reg_block, interrupt_mask); 2996 2996 break; 2997 2997 default: ··· 3021 3021 switch (state) { 3022 3022 case AMDGPU_IRQ_STATE_DISABLE: 3023 3023 dc_hpd_int_cntl = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[type]); 3024 - dc_hpd_int_cntl &= ~DC_HPDx_INT_EN; 3024 + dc_hpd_int_cntl &= ~DC_HPD1_INT_CONTROL__DC_HPD1_INT_EN_MASK; 3025 3025 WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[type], dc_hpd_int_cntl); 3026 3026 break; 3027 3027 case AMDGPU_IRQ_STATE_ENABLE: 3028 3028 dc_hpd_int_cntl = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[type]); 3029 - dc_hpd_int_cntl |= DC_HPDx_INT_EN; 3029 + dc_hpd_int_cntl |= DC_HPD1_INT_CONTROL__DC_HPD1_INT_EN_MASK; 3030 3030 WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[type], dc_hpd_int_cntl); 3031 3031 break; 3032 3032 default: ··· 3096 3096 switch (entry->src_data[0]) { 3097 3097 case 0: /* vblank */ 3098 3098 if (disp_int & interrupt_status_offsets[crtc].vblank) 3099 - WREG32(mmVBLANK_STATUS + crtc_offsets[crtc], VBLANK_ACK); 3099 + WREG32(mmVBLANK_STATUS + crtc_offsets[crtc], VBLANK_STATUS__VBLANK_ACK_MASK); 3100 3100 else 3101 3101 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n"); 3102 3102 ··· 3107 3107 break; 3108 3108 case 1: /* vline */ 3109 3109 if (disp_int & interrupt_status_offsets[crtc].vline) 3110 - WREG32(mmVLINE_STATUS + crtc_offsets[crtc], VLINE_ACK); 3110 + WREG32(mmVLINE_STATUS + crtc_offsets[crtc], VLINE_STATUS__VLINE_ACK_MASK); 3111 3111 else 3112 3112 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n"); 3113 3113
+1 -1
drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
··· 249 249 250 250 /* disable VGA render */ 251 251 tmp = RREG32(mmVGA_RENDER_CONTROL); 252 - tmp &= ~VGA_VSTATUS_CNTL; 252 + tmp &= VGA_RENDER_CONTROL__VGA_VSTATUS_CNTL_MASK; 253 253 WREG32(mmVGA_RENDER_CONTROL, tmp); 254 254 } 255 255 /* Update configuration */
-5
drivers/gpu/drm/amd/amdgpu/si_enums.h
··· 23 23 #ifndef SI_ENUMS_H 24 24 #define SI_ENUMS_H 25 25 26 - #define VBLANK_INT_MASK (1 << 0) 27 - #define DC_HPDx_INT_EN (1 << 16) 28 26 #define VBLANK_ACK (1 << 4) 29 27 #define VLINE_ACK (1 << 4) 30 28 31 29 #define CURSOR_WIDTH 64 32 30 #define CURSOR_HEIGHT 64 33 31 34 - #define VGA_VSTATUS_CNTL 0xFFFCFFFF 35 32 #define PRIORITY_MARK_MASK 0x7fff 36 33 #define PRIORITY_OFF (1 << 16) 37 34 #define PRIORITY_ALWAYS_ON (1 << 20) 38 - #define INTERLEAVE_EN (1 << 0) 39 35 40 36 #define LATENCY_WATERMARK_MASK(x) ((x) << 16) 41 37 #define DC_LB_MEMORY_CONFIG(x) ((x) << 20) 42 - #define ICON_DEGAMMA_MODE(x) (((x) & 0x3) << 8) 43 38 44 39 #define GRPH_ENDIAN_SWAP(x) (((x) & 0x3) << 0) 45 40 #define GRPH_ENDIAN_NONE 0
-20
drivers/gpu/drm/amd/amdgpu/sid.h
··· 787 787 # define LATENCY_LOW_WATERMARK(x) ((x) << 0) 788 788 # define LATENCY_HIGH_WATERMARK(x) ((x) << 16) 789 789 790 - /* 0x6bb8, 0x77b8, 0x103b8, 0x10fb8, 0x11bb8, 0x127b8 */ 791 - #define VLINE_STATUS 0x1AEE 792 - # define VLINE_OCCURRED (1 << 0) 793 - # define VLINE_ACK (1 << 4) 794 - # define VLINE_STAT (1 << 12) 795 - # define VLINE_INTERRUPT (1 << 16) 796 - # define VLINE_INTERRUPT_TYPE (1 << 17) 797 - /* 0x6bbc, 0x77bc, 0x103bc, 0x10fbc, 0x11bbc, 0x127bc */ 798 - #define VBLANK_STATUS 0x1AEF 799 - # define VBLANK_OCCURRED (1 << 0) 800 - # define VBLANK_ACK (1 << 4) 801 - # define VBLANK_STAT (1 << 12) 802 - # define VBLANK_INTERRUPT (1 << 16) 803 - # define VBLANK_INTERRUPT_TYPE (1 << 17) 804 - 805 - /* 0x6b40, 0x7740, 0x10340, 0x10f40, 0x11b40, 0x12740 */ 806 - #define INT_MASK 0x1AD0 807 - # define VBLANK_INT_MASK (1 << 0) 808 - # define VLINE_INT_MASK (1 << 4) 809 - 810 790 #define DISP_INTERRUPT_STATUS 0x183D 811 791 # define LB_D1_VLINE_INTERRUPT (1 << 2) 812 792 # define LB_D1_VBLANK_INTERRUPT (1 << 3)
+2
drivers/gpu/drm/amd/include/asic_reg/dce/dce_6_0_sh_mask.h
··· 5242 5242 #define DEGAMMA_CONTROL__CURSOR_DEGAMMA_MODE__SHIFT 0x0000000c 5243 5243 #define DEGAMMA_CONTROL__GRPH_DEGAMMA_MODE_MASK 0x00000003L 5244 5244 #define DEGAMMA_CONTROL__GRPH_DEGAMMA_MODE__SHIFT 0x00000000 5245 + #define DEGAMMA_CONTROL__ICON_DEGAMMA_MODE_MASK 0x00000300L 5246 + #define DEGAMMA_CONTROL__ICON_DEGAMMA_MODE__SHIFT 0x00000008 5245 5247 #define DEGAMMA_CONTROL__OVL_DEGAMMA_MODE_MASK 0x00000030L 5246 5248 #define DEGAMMA_CONTROL__OVL_DEGAMMA_MODE__SHIFT 0x00000004 5247 5249 #define DENORM_CONTROL__DENORM_MODE_MASK 0x00000007L