tjh.dev / kernel
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drm/amd/display: Select correct DTO source

[WHY&HOW]
Change criteria for setting DTO source value, and always set it regardless of
the signal type.

Signed-off-by: Dillon Varone <dillon.varone@amd.com>
Acked-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

authored by

Dillon Varone and committed by
Alex Deucher 1908a07c cbd3e844

+27
+27
drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
··· 992 992 REG_WRITE(PHASE[inst], pll_settings->actual_pix_clk_100hz * 100); 993 993 REG_WRITE(MODULO[inst], dp_dto_ref_khz * 1000); 994 994 } 995 + #if defined(CONFIG_DRM_AMD_DC_DCN) 996 + /* Enable DTO */ 997 + if (clk_src->cs_mask->PIPE0_DTO_SRC_SEL) 998 + REG_UPDATE_2(PIXEL_RATE_CNTL[inst], 999 + DP_DTO0_ENABLE, 1, 1000 + PIPE0_DTO_SRC_SEL, 1); 1001 + else 1002 + REG_UPDATE(PIXEL_RATE_CNTL[inst], 1003 + DP_DTO0_ENABLE, 1); 1004 + #else 995 1005 REG_UPDATE(PIXEL_RATE_CNTL[inst], DP_DTO0_ENABLE, 1); 1006 + #endif 996 1007 } else { 997 1008 if (IS_FPGA_MAXIMUS_DC(clock_source->ctx->dce_environment)) { 998 1009 unsigned int inst = pix_clk_params->controller_id - CONTROLLER_ID_D0; ··· 1015 1004 REG_WRITE(MODULO[inst], dp_dto_ref_100hz); 1016 1005 1017 1006 /* Enable DTO */ 1007 + #if defined(CONFIG_DRM_AMD_DC_DCN) 1008 + if (clk_src->cs_mask->PIPE0_DTO_SRC_SEL) 1009 + REG_UPDATE_2(PIXEL_RATE_CNTL[inst], 1010 + DP_DTO0_ENABLE, 1, 1011 + PIPE0_DTO_SRC_SEL, 1); 1012 + else 1013 + REG_UPDATE(PIXEL_RATE_CNTL[inst], 1014 + DP_DTO0_ENABLE, 1); 1015 + #else 1018 1016 REG_UPDATE(PIXEL_RATE_CNTL[inst], DP_DTO0_ENABLE, 1); 1017 + #endif 1019 1018 return true; 1020 1019 } 1020 + 1021 + #if defined(CONFIG_DRM_AMD_DC_DCN) 1022 + if (clk_src->cs_mask->PIPE0_DTO_SRC_SEL) 1023 + REG_UPDATE(PIXEL_RATE_CNTL[inst], 1024 + PIPE0_DTO_SRC_SEL, 0); 1025 + #endif 1021 1026 1022 1027 /*ATOMBIOS expects pixel rate adjusted by deep color ratio)*/ 1023 1028 bp_pc_params.controller_id = pix_clk_params->controller_id;