Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux

gpu: host1x: Use the correct HW headers for host1x02

An earlier patch added a subset of the required HW specific header files
but didn't actually include the right ones when compiling for host1x02.

Signed-off-by: Thierry Reding <treding@nvidia.com>

+150 -2
+2 -2
drivers/gpu/host1x/hw/host1x02.c
··· 17 17 */ 18 18 19 19 /* include hw specification */ 20 - #include "host1x01.h" 21 - #include "host1x01_hardware.h" 20 + #include "host1x02.h" 21 + #include "host1x02_hardware.h" 22 22 23 23 /* include code */ 24 24 #include "cdma_hw.c"
+142
drivers/gpu/host1x/hw/host1x02_hardware.h
··· 1 + /* 2 + * Tegra host1x Register Offsets for Tegra114 3 + * 4 + * Copyright (c) 2010-2013 NVIDIA Corporation. 5 + * 6 + * This program is free software; you can redistribute it and/or modify it 7 + * under the terms and conditions of the GNU General Public License, 8 + * version 2, as published by the Free Software Foundation. 9 + * 10 + * This program is distributed in the hope it will be useful, but WITHOUT 11 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 + * more details. 14 + * 15 + * You should have received a copy of the GNU General Public License 16 + * along with this program. If not, see <http://www.gnu.org/licenses/>. 17 + */ 18 + 19 + #ifndef __HOST1X_HOST1X02_HARDWARE_H 20 + #define __HOST1X_HOST1X02_HARDWARE_H 21 + 22 + #include <linux/types.h> 23 + #include <linux/bitops.h> 24 + 25 + #include "hw_host1x02_channel.h" 26 + #include "hw_host1x02_sync.h" 27 + #include "hw_host1x02_uclass.h" 28 + 29 + static inline u32 host1x_class_host_wait_syncpt( 30 + unsigned indx, unsigned threshold) 31 + { 32 + return host1x_uclass_wait_syncpt_indx_f(indx) 33 + | host1x_uclass_wait_syncpt_thresh_f(threshold); 34 + } 35 + 36 + static inline u32 host1x_class_host_load_syncpt_base( 37 + unsigned indx, unsigned threshold) 38 + { 39 + return host1x_uclass_load_syncpt_base_base_indx_f(indx) 40 + | host1x_uclass_load_syncpt_base_value_f(threshold); 41 + } 42 + 43 + static inline u32 host1x_class_host_wait_syncpt_base( 44 + unsigned indx, unsigned base_indx, unsigned offset) 45 + { 46 + return host1x_uclass_wait_syncpt_base_indx_f(indx) 47 + | host1x_uclass_wait_syncpt_base_base_indx_f(base_indx) 48 + | host1x_uclass_wait_syncpt_base_offset_f(offset); 49 + } 50 + 51 + static inline u32 host1x_class_host_incr_syncpt_base( 52 + unsigned base_indx, unsigned offset) 53 + { 54 + return host1x_uclass_incr_syncpt_base_base_indx_f(base_indx) 55 + | host1x_uclass_incr_syncpt_base_offset_f(offset); 56 + } 57 + 58 + static inline u32 host1x_class_host_incr_syncpt( 59 + unsigned cond, unsigned indx) 60 + { 61 + return host1x_uclass_incr_syncpt_cond_f(cond) 62 + | host1x_uclass_incr_syncpt_indx_f(indx); 63 + } 64 + 65 + static inline u32 host1x_class_host_indoff_reg_write( 66 + unsigned mod_id, unsigned offset, bool auto_inc) 67 + { 68 + u32 v = host1x_uclass_indoff_indbe_f(0xf) 69 + | host1x_uclass_indoff_indmodid_f(mod_id) 70 + | host1x_uclass_indoff_indroffset_f(offset); 71 + if (auto_inc) 72 + v |= host1x_uclass_indoff_autoinc_f(1); 73 + return v; 74 + } 75 + 76 + static inline u32 host1x_class_host_indoff_reg_read( 77 + unsigned mod_id, unsigned offset, bool auto_inc) 78 + { 79 + u32 v = host1x_uclass_indoff_indmodid_f(mod_id) 80 + | host1x_uclass_indoff_indroffset_f(offset) 81 + | host1x_uclass_indoff_rwn_read_v(); 82 + if (auto_inc) 83 + v |= host1x_uclass_indoff_autoinc_f(1); 84 + return v; 85 + } 86 + 87 + /* cdma opcodes */ 88 + static inline u32 host1x_opcode_setclass( 89 + unsigned class_id, unsigned offset, unsigned mask) 90 + { 91 + return (0 << 28) | (offset << 16) | (class_id << 6) | mask; 92 + } 93 + 94 + static inline u32 host1x_opcode_incr(unsigned offset, unsigned count) 95 + { 96 + return (1 << 28) | (offset << 16) | count; 97 + } 98 + 99 + static inline u32 host1x_opcode_nonincr(unsigned offset, unsigned count) 100 + { 101 + return (2 << 28) | (offset << 16) | count; 102 + } 103 + 104 + static inline u32 host1x_opcode_mask(unsigned offset, unsigned mask) 105 + { 106 + return (3 << 28) | (offset << 16) | mask; 107 + } 108 + 109 + static inline u32 host1x_opcode_imm(unsigned offset, unsigned value) 110 + { 111 + return (4 << 28) | (offset << 16) | value; 112 + } 113 + 114 + static inline u32 host1x_opcode_imm_incr_syncpt(unsigned cond, unsigned indx) 115 + { 116 + return host1x_opcode_imm(host1x_uclass_incr_syncpt_r(), 117 + host1x_class_host_incr_syncpt(cond, indx)); 118 + } 119 + 120 + static inline u32 host1x_opcode_restart(unsigned address) 121 + { 122 + return (5 << 28) | (address >> 4); 123 + } 124 + 125 + static inline u32 host1x_opcode_gather(unsigned count) 126 + { 127 + return (6 << 28) | count; 128 + } 129 + 130 + static inline u32 host1x_opcode_gather_nonincr(unsigned offset, unsigned count) 131 + { 132 + return (6 << 28) | (offset << 16) | BIT(15) | count; 133 + } 134 + 135 + static inline u32 host1x_opcode_gather_incr(unsigned offset, unsigned count) 136 + { 137 + return (6 << 28) | (offset << 16) | BIT(15) | BIT(14) | count; 138 + } 139 + 140 + #define HOST1X_OPCODE_NOP host1x_opcode_nonincr(0, 0) 141 + 142 + #endif
+6
drivers/gpu/host1x/hw/hw_host1x02_uclass.h
··· 111 111 } 112 112 #define HOST1X_UCLASS_WAIT_SYNCPT_BASE_OFFSET_F(v) \ 113 113 host1x_uclass_wait_syncpt_base_offset_f(v) 114 + static inline u32 host1x_uclass_load_syncpt_base_r(void) 115 + { 116 + return 0xb; 117 + } 118 + #define HOST1X_UCLASS_LOAD_SYNCPT_BASE \ 119 + host1x_uclass_load_syncpt_base_r() 114 120 static inline u32 host1x_uclass_load_syncpt_base_base_indx_f(u32 v) 115 121 { 116 122 return (v & 0xff) << 24;