tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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drm/radeon: add get_allowed_info_register function for r1xx-r5xx

Just a stub.

Tested-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

Alex Deucher 18b53e90 4ce4728b

+15
+15
drivers/gpu/drm/radeon/radeon_asic.c
··· 136 136 } 137 137 } 138 138 139 + static int radeon_invalid_get_allowed_info_register(struct radeon_device *rdev, 140 + u32 reg, u32 *val) 141 + { 142 + return -EINVAL; 143 + } 139 144 140 145 /* helper to disable agp */ 141 146 /** ··· 204 199 .mmio_hdp_flush = NULL, 205 200 .gui_idle = &r100_gui_idle, 206 201 .mc_wait_for_idle = &r100_mc_wait_for_idle, 202 + .get_allowed_info_register = radeon_invalid_get_allowed_info_register, 207 203 .gart = { 208 204 .tlb_flush = &r100_pci_gart_tlb_flush, 209 205 .get_page_entry = &r100_pci_gart_get_page_entry, ··· 272 266 .mmio_hdp_flush = NULL, 273 267 .gui_idle = &r100_gui_idle, 274 268 .mc_wait_for_idle = &r100_mc_wait_for_idle, 269 + .get_allowed_info_register = radeon_invalid_get_allowed_info_register, 275 270 .gart = { 276 271 .tlb_flush = &r100_pci_gart_tlb_flush, 277 272 .get_page_entry = &r100_pci_gart_get_page_entry, ··· 368 361 .mmio_hdp_flush = NULL, 369 362 .gui_idle = &r100_gui_idle, 370 363 .mc_wait_for_idle = &r300_mc_wait_for_idle, 364 + .get_allowed_info_register = radeon_invalid_get_allowed_info_register, 371 365 .gart = { 372 366 .tlb_flush = &r100_pci_gart_tlb_flush, 373 367 .get_page_entry = &r100_pci_gart_get_page_entry, ··· 436 428 .mmio_hdp_flush = NULL, 437 429 .gui_idle = &r100_gui_idle, 438 430 .mc_wait_for_idle = &r300_mc_wait_for_idle, 431 + .get_allowed_info_register = radeon_invalid_get_allowed_info_register, 439 432 .gart = { 440 433 .tlb_flush = &rv370_pcie_gart_tlb_flush, 441 434 .get_page_entry = &rv370_pcie_gart_get_page_entry, ··· 504 495 .mmio_hdp_flush = NULL, 505 496 .gui_idle = &r100_gui_idle, 506 497 .mc_wait_for_idle = &r300_mc_wait_for_idle, 498 + .get_allowed_info_register = radeon_invalid_get_allowed_info_register, 507 499 .gart = { 508 500 .tlb_flush = &rv370_pcie_gart_tlb_flush, 509 501 .get_page_entry = &rv370_pcie_gart_get_page_entry, ··· 572 562 .mmio_hdp_flush = NULL, 573 563 .gui_idle = &r100_gui_idle, 574 564 .mc_wait_for_idle = &rs400_mc_wait_for_idle, 565 + .get_allowed_info_register = radeon_invalid_get_allowed_info_register, 575 566 .gart = { 576 567 .tlb_flush = &rs400_gart_tlb_flush, 577 568 .get_page_entry = &rs400_gart_get_page_entry, ··· 640 629 .mmio_hdp_flush = NULL, 641 630 .gui_idle = &r100_gui_idle, 642 631 .mc_wait_for_idle = &rs600_mc_wait_for_idle, 632 + .get_allowed_info_register = radeon_invalid_get_allowed_info_register, 643 633 .gart = { 644 634 .tlb_flush = &rs600_gart_tlb_flush, 645 635 .get_page_entry = &rs600_gart_get_page_entry, ··· 708 696 .mmio_hdp_flush = NULL, 709 697 .gui_idle = &r100_gui_idle, 710 698 .mc_wait_for_idle = &rs690_mc_wait_for_idle, 699 + .get_allowed_info_register = radeon_invalid_get_allowed_info_register, 711 700 .gart = { 712 701 .tlb_flush = &rs400_gart_tlb_flush, 713 702 .get_page_entry = &rs400_gart_get_page_entry, ··· 776 763 .mmio_hdp_flush = NULL, 777 764 .gui_idle = &r100_gui_idle, 778 765 .mc_wait_for_idle = &rv515_mc_wait_for_idle, 766 + .get_allowed_info_register = radeon_invalid_get_allowed_info_register, 779 767 .gart = { 780 768 .tlb_flush = &rv370_pcie_gart_tlb_flush, 781 769 .get_page_entry = &rv370_pcie_gart_get_page_entry, ··· 844 830 .mmio_hdp_flush = NULL, 845 831 .gui_idle = &r100_gui_idle, 846 832 .mc_wait_for_idle = &r520_mc_wait_for_idle, 833 + .get_allowed_info_register = radeon_invalid_get_allowed_info_register, 847 834 .gart = { 848 835 .tlb_flush = &rv370_pcie_gart_tlb_flush, 849 836 .get_page_entry = &rv370_pcie_gart_get_page_entry,