tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
dt-bindings: net: Add Tegra234 MGBE
Add device-tree binding documentation for the Multi-Gigabit Ethernet
(MGBE) controller found on NVIDIA Tegra234 SoCs.
Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Bhadram Varka <vbhadram@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
authored by
Bhadram Varka
and committed by
Thierry Reding
189c2e5c
568035b0
+162
+162
Documentation/devicetree/bindings/net/nvidia,tegra234-mgbe.yaml
+162
Documentation/devicetree/bindings/net/nvidia,tegra234-mgbe.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/net/nvidia,tegra234-mgbe.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Tegra234 MGBE Multi-Gigabit Ethernet Controller
8
+
9
+
maintainers:
10
+
- Thierry Reding <treding@nvidia.com>
11
+
- Jon Hunter <jonathanh@nvidia.com>
12
+
13
+
properties:
14
+
compatible:
15
+
const: nvidia,tegra234-mgbe
16
+
17
+
reg:
18
+
maxItems: 3
19
+
20
+
reg-names:
21
+
items:
22
+
- const: hypervisor
23
+
- const: mac
24
+
- const: xpcs
25
+
26
+
interrupts:
27
+
minItems: 1
28
+
maxItems: 3
29
+
30
+
interrupt-names:
31
+
minItems: 1
32
+
items:
33
+
- const: common
34
+
- const: macsec-ns
35
+
- const: macsec
36
+
37
+
clocks:
38
+
maxItems: 12
39
+
40
+
clock-names:
41
+
items:
42
+
- const: mgbe
43
+
- const: mac
44
+
- const: mac-divider
45
+
- const: ptp-ref
46
+
- const: rx-input-m
47
+
- const: rx-input
48
+
- const: tx
49
+
- const: eee-pcs
50
+
- const: rx-pcs-input
51
+
- const: rx-pcs-m
52
+
- const: rx-pcs
53
+
- const: tx-pcs
54
+
55
+
resets:
56
+
maxItems: 2
57
+
58
+
reset-names:
59
+
items:
60
+
- const: mac
61
+
- const: pcs
62
+
63
+
interconnects:
64
+
items:
65
+
- description: memory read client
66
+
- description: memory write client
67
+
68
+
interconnect-names:
69
+
items:
70
+
- const: dma-mem
71
+
- const: write
72
+
73
+
iommus:
74
+
maxItems: 1
75
+
76
+
power-domains:
77
+
maxItems: 1
78
+
79
+
phy-handle: true
80
+
81
+
phy-mode:
82
+
contains:
83
+
enum:
84
+
- usxgmii
85
+
- 10gbase-kr
86
+
87
+
mdio:
88
+
$ref: mdio.yaml#
89
+
unevaluatedProperties: false
90
+
description:
91
+
Optional node for embedded MDIO controller.
92
+
93
+
required:
94
+
- compatible
95
+
- reg
96
+
- interrupts
97
+
- interrupt-names
98
+
- clocks
99
+
- clock-names
100
+
- resets
101
+
- reset-names
102
+
- power-domains
103
+
- phy-handle
104
+
- phy-mode
105
+
106
+
additionalProperties: false
107
+
108
+
examples:
109
+
- |
110
+
#include <dt-bindings/clock/tegra234-clock.h>
111
+
#include <dt-bindings/interrupt-controller/arm-gic.h>
112
+
#include <dt-bindings/memory/tegra234-mc.h>
113
+
#include <dt-bindings/power/tegra234-powergate.h>
114
+
#include <dt-bindings/reset/tegra234-reset.h>
115
+
116
+
ethernet@6800000 {
117
+
compatible = "nvidia,tegra234-mgbe";
118
+
reg = <0x06800000 0x10000>,
119
+
<0x06810000 0x10000>,
120
+
<0x068a0000 0x10000>;
121
+
reg-names = "hypervisor", "mac", "xpcs";
122
+
interrupts = <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>;
123
+
interrupt-names = "common";
124
+
clocks = <&bpmp TEGRA234_CLK_MGBE0_APP>,
125
+
<&bpmp TEGRA234_CLK_MGBE0_MAC>,
126
+
<&bpmp TEGRA234_CLK_MGBE0_MAC_DIVIDER>,
127
+
<&bpmp TEGRA234_CLK_MGBE0_PTP_REF>,
128
+
<&bpmp TEGRA234_CLK_MGBE0_RX_INPUT_M>,
129
+
<&bpmp TEGRA234_CLK_MGBE0_RX_INPUT>,
130
+
<&bpmp TEGRA234_CLK_MGBE0_TX>,
131
+
<&bpmp TEGRA234_CLK_MGBE0_EEE_PCS>,
132
+
<&bpmp TEGRA234_CLK_MGBE0_RX_PCS_INPUT>,
133
+
<&bpmp TEGRA234_CLK_MGBE0_RX_PCS_M>,
134
+
<&bpmp TEGRA234_CLK_MGBE0_RX_PCS>,
135
+
<&bpmp TEGRA234_CLK_MGBE0_TX_PCS>;
136
+
clock-names = "mgbe", "mac", "mac-divider", "ptp-ref", "rx-input-m",
137
+
"rx-input", "tx", "eee-pcs", "rx-pcs-input", "rx-pcs-m",
138
+
"rx-pcs", "tx-pcs";
139
+
resets = <&bpmp TEGRA234_RESET_MGBE0_MAC>,
140
+
<&bpmp TEGRA234_RESET_MGBE0_PCS>;
141
+
reset-names = "mac", "pcs";
142
+
interconnects = <&mc TEGRA234_MEMORY_CLIENT_MGBEARD &emc>,
143
+
<&mc TEGRA234_MEMORY_CLIENT_MGBEAWR &emc>;
144
+
interconnect-names = "dma-mem", "write";
145
+
iommus = <&smmu_niso0 TEGRA234_SID_MGBE>;
146
+
power-domains = <&bpmp TEGRA234_POWER_DOMAIN_MGBEA>;
147
+
148
+
phy-handle = <&mgbe0_phy>;
149
+
phy-mode = "usxgmii";
150
+
151
+
mdio {
152
+
#address-cells = <1>;
153
+
#size-cells = <0>;
154
+
155
+
mgbe0_phy: phy@0 {
156
+
compatible = "ethernet-phy-ieee802.3-c45";
157
+
reg = <0x0>;
158
+
159
+
#phy-cells = <0>;
160
+
};
161
+
};
162
+
};