Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux

Merge branches 'ib-mfd-gpio-4.12', 'ib-mfd-iio-input-4.12', 'ib-mfd-input-4.12', 'ib-mfd-leds-4.12', 'ib-mfd-phy-4.12' and 'ib-mfd-pinctrl-samsung-4.12' into ibs-for-mfd-merged

+2300 -1767
Documentation/devicetree/bindings/iio/adc/mxs-lradc.txt Documentation/devicetree/bindings/mfd/mxs-lradc.txt
+20
Documentation/devicetree/bindings/input/cpcap-pwrbutton.txt
··· 1 + Motorola CPCAP on key 2 + 3 + This module is part of the CPCAP. For more details about the whole 4 + chip see Documentation/devicetree/bindings/mfd/motorola-cpcap.txt. 5 + 6 + This module provides a simple power button event via an Interrupt. 7 + 8 + Required properties: 9 + - compatible: should be one of the following 10 + - "motorola,cpcap-pwrbutton" 11 + - interrupts: irq specifier for CPCAP's ON IRQ 12 + 13 + Example: 14 + 15 + &cpcap { 16 + cpcap_pwrbutton: pwrbutton { 17 + compatible = "motorola,cpcap-pwrbutton"; 18 + interrupts = <23 IRQ_TYPE_NONE>; 19 + }; 20 + };
+13 -14
drivers/iio/adc/Kconfig
··· 229 229 To compile this driver as a module, choose M here: the module will be 230 230 called exynos_adc. 231 231 232 + config MXS_LRADC_ADC 233 + tristate "Freescale i.MX23/i.MX28 LRADC ADC" 234 + depends on MFD_MXS_LRADC 235 + select IIO_BUFFER 236 + select IIO_TRIGGERED_BUFFER 237 + help 238 + Say yes here to build support for the ADC functions of the 239 + i.MX23/i.MX28 LRADC. This includes general-purpose ADC readings, 240 + battery voltage measurement, and die temperature measurement. 241 + 242 + This driver can also be built as a module. If so, the module will be 243 + called mxs-lradc-adc. 244 + 232 245 config FSL_MX25_ADC 233 246 tristate "Freescale MX25 ADC driver" 234 247 depends on MFD_MX25_TSADC ··· 423 410 424 411 To compile this driver as a module, choose M here: the 425 412 module will be called meson_saradc. 426 - 427 - config MXS_LRADC 428 - tristate "Freescale i.MX23/i.MX28 LRADC" 429 - depends on (ARCH_MXS || COMPILE_TEST) && HAS_IOMEM 430 - depends on INPUT 431 - select STMP_DEVICE 432 - select IIO_BUFFER 433 - select IIO_TRIGGERED_BUFFER 434 - help 435 - Say yes here to build support for i.MX23/i.MX28 LRADC convertor 436 - built into these chips. 437 - 438 - To compile this driver as a module, choose M here: the 439 - module will be called mxs-lradc. 440 413 441 414 config NAU7802 442 415 tristate "Nuvoton NAU7802 ADC driver"
+1 -1
drivers/iio/adc/Makefile
··· 39 39 obj-$(CONFIG_MEDIATEK_MT6577_AUXADC) += mt6577_auxadc.o 40 40 obj-$(CONFIG_MEN_Z188_ADC) += men_z188_adc.o 41 41 obj-$(CONFIG_MESON_SARADC) += meson_saradc.o 42 - obj-$(CONFIG_MXS_LRADC) += mxs-lradc.o 42 + obj-$(CONFIG_MXS_LRADC_ADC) += mxs-lradc-adc.o 43 43 obj-$(CONFIG_NAU7802) += nau7802.o 44 44 obj-$(CONFIG_PALMAS_GPADC) += palmas_gpadc.o 45 45 obj-$(CONFIG_QCOM_SPMI_IADC) += qcom-spmi-iadc.o
+843
drivers/iio/adc/mxs-lradc-adc.c
··· 1 + /* 2 + * Freescale MXS LRADC ADC driver 3 + * 4 + * Copyright (c) 2012 DENX Software Engineering, GmbH. 5 + * Copyright (c) 2017 Ksenija Stanojevic <ksenija.stanojevic@gmail.com> 6 + * 7 + * Authors: 8 + * Marek Vasut <marex@denx.de> 9 + * Ksenija Stanojevic <ksenija.stanojevic@gmail.com> 10 + * 11 + * This program is free software; you can redistribute it and/or modify 12 + * it under the terms of the GNU General Public License as published by 13 + * the Free Software Foundation; either version 2 of the License, or 14 + * (at your option) any later version. 15 + * 16 + * This program is distributed in the hope that it will be useful, 17 + * but WITHOUT ANY WARRANTY; without even the implied warranty of 18 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 19 + * GNU General Public License for more details. 20 + */ 21 + 22 + #include <linux/completion.h> 23 + #include <linux/device.h> 24 + #include <linux/err.h> 25 + #include <linux/interrupt.h> 26 + #include <linux/mfd/core.h> 27 + #include <linux/mfd/mxs-lradc.h> 28 + #include <linux/module.h> 29 + #include <linux/of_irq.h> 30 + #include <linux/platform_device.h> 31 + #include <linux/sysfs.h> 32 + 33 + #include <linux/iio/buffer.h> 34 + #include <linux/iio/iio.h> 35 + #include <linux/iio/trigger.h> 36 + #include <linux/iio/trigger_consumer.h> 37 + #include <linux/iio/triggered_buffer.h> 38 + #include <linux/iio/sysfs.h> 39 + 40 + /* 41 + * Make this runtime configurable if necessary. Currently, if the buffered mode 42 + * is enabled, the LRADC takes LRADC_DELAY_TIMER_LOOP samples of data before 43 + * triggering IRQ. The sampling happens every (LRADC_DELAY_TIMER_PER / 2000) 44 + * seconds. The result is that the samples arrive every 500mS. 45 + */ 46 + #define LRADC_DELAY_TIMER_PER 200 47 + #define LRADC_DELAY_TIMER_LOOP 5 48 + 49 + #define VREF_MV_BASE 1850 50 + 51 + const char *mx23_lradc_adc_irq_names[] = { 52 + "mxs-lradc-channel0", 53 + "mxs-lradc-channel1", 54 + "mxs-lradc-channel2", 55 + "mxs-lradc-channel3", 56 + "mxs-lradc-channel4", 57 + "mxs-lradc-channel5", 58 + }; 59 + 60 + const char *mx28_lradc_adc_irq_names[] = { 61 + "mxs-lradc-thresh0", 62 + "mxs-lradc-thresh1", 63 + "mxs-lradc-channel0", 64 + "mxs-lradc-channel1", 65 + "mxs-lradc-channel2", 66 + "mxs-lradc-channel3", 67 + "mxs-lradc-channel4", 68 + "mxs-lradc-channel5", 69 + "mxs-lradc-button0", 70 + "mxs-lradc-button1", 71 + }; 72 + 73 + static const u32 mxs_lradc_adc_vref_mv[][LRADC_MAX_TOTAL_CHANS] = { 74 + [IMX23_LRADC] = { 75 + VREF_MV_BASE, /* CH0 */ 76 + VREF_MV_BASE, /* CH1 */ 77 + VREF_MV_BASE, /* CH2 */ 78 + VREF_MV_BASE, /* CH3 */ 79 + VREF_MV_BASE, /* CH4 */ 80 + VREF_MV_BASE, /* CH5 */ 81 + VREF_MV_BASE * 2, /* CH6 VDDIO */ 82 + VREF_MV_BASE * 4, /* CH7 VBATT */ 83 + VREF_MV_BASE, /* CH8 Temp sense 0 */ 84 + VREF_MV_BASE, /* CH9 Temp sense 1 */ 85 + VREF_MV_BASE, /* CH10 */ 86 + VREF_MV_BASE, /* CH11 */ 87 + VREF_MV_BASE, /* CH12 USB_DP */ 88 + VREF_MV_BASE, /* CH13 USB_DN */ 89 + VREF_MV_BASE, /* CH14 VBG */ 90 + VREF_MV_BASE * 4, /* CH15 VDD5V */ 91 + }, 92 + [IMX28_LRADC] = { 93 + VREF_MV_BASE, /* CH0 */ 94 + VREF_MV_BASE, /* CH1 */ 95 + VREF_MV_BASE, /* CH2 */ 96 + VREF_MV_BASE, /* CH3 */ 97 + VREF_MV_BASE, /* CH4 */ 98 + VREF_MV_BASE, /* CH5 */ 99 + VREF_MV_BASE, /* CH6 */ 100 + VREF_MV_BASE * 4, /* CH7 VBATT */ 101 + VREF_MV_BASE, /* CH8 Temp sense 0 */ 102 + VREF_MV_BASE, /* CH9 Temp sense 1 */ 103 + VREF_MV_BASE * 2, /* CH10 VDDIO */ 104 + VREF_MV_BASE, /* CH11 VTH */ 105 + VREF_MV_BASE * 2, /* CH12 VDDA */ 106 + VREF_MV_BASE, /* CH13 VDDD */ 107 + VREF_MV_BASE, /* CH14 VBG */ 108 + VREF_MV_BASE * 4, /* CH15 VDD5V */ 109 + }, 110 + }; 111 + 112 + enum mxs_lradc_divbytwo { 113 + MXS_LRADC_DIV_DISABLED = 0, 114 + MXS_LRADC_DIV_ENABLED, 115 + }; 116 + 117 + struct mxs_lradc_scale { 118 + unsigned int integer; 119 + unsigned int nano; 120 + }; 121 + 122 + struct mxs_lradc_adc { 123 + struct mxs_lradc *lradc; 124 + struct device *dev; 125 + 126 + void __iomem *base; 127 + u32 buffer[10]; 128 + struct iio_trigger *trig; 129 + struct completion completion; 130 + spinlock_t lock; 131 + 132 + const u32 *vref_mv; 133 + struct mxs_lradc_scale scale_avail[LRADC_MAX_TOTAL_CHANS][2]; 134 + unsigned long is_divided; 135 + }; 136 + 137 + 138 + /* Raw I/O operations */ 139 + static int mxs_lradc_adc_read_single(struct iio_dev *iio_dev, int chan, 140 + int *val) 141 + { 142 + struct mxs_lradc_adc *adc = iio_priv(iio_dev); 143 + struct mxs_lradc *lradc = adc->lradc; 144 + int ret; 145 + 146 + /* 147 + * See if there is no buffered operation in progress. If there is simply 148 + * bail out. This can be improved to support both buffered and raw IO at 149 + * the same time, yet the code becomes horribly complicated. Therefore I 150 + * applied KISS principle here. 151 + */ 152 + ret = iio_device_claim_direct_mode(iio_dev); 153 + if (ret) 154 + return ret; 155 + 156 + reinit_completion(&adc->completion); 157 + 158 + /* 159 + * No buffered operation in progress, map the channel and trigger it. 160 + * Virtual channel 0 is always used here as the others are always not 161 + * used if doing raw sampling. 162 + */ 163 + if (lradc->soc == IMX28_LRADC) 164 + writel(LRADC_CTRL1_LRADC_IRQ_EN(0), 165 + adc->base + LRADC_CTRL1 + STMP_OFFSET_REG_CLR); 166 + writel(0x1, adc->base + LRADC_CTRL0 + STMP_OFFSET_REG_CLR); 167 + 168 + /* Enable / disable the divider per requirement */ 169 + if (test_bit(chan, &adc->is_divided)) 170 + writel(1 << LRADC_CTRL2_DIVIDE_BY_TWO_OFFSET, 171 + adc->base + LRADC_CTRL2 + STMP_OFFSET_REG_SET); 172 + else 173 + writel(1 << LRADC_CTRL2_DIVIDE_BY_TWO_OFFSET, 174 + adc->base + LRADC_CTRL2 + STMP_OFFSET_REG_CLR); 175 + 176 + /* Clean the slot's previous content, then set new one. */ 177 + writel(LRADC_CTRL4_LRADCSELECT_MASK(0), 178 + adc->base + LRADC_CTRL4 + STMP_OFFSET_REG_CLR); 179 + writel(chan, adc->base + LRADC_CTRL4 + STMP_OFFSET_REG_SET); 180 + 181 + writel(0, adc->base + LRADC_CH(0)); 182 + 183 + /* Enable the IRQ and start sampling the channel. */ 184 + writel(LRADC_CTRL1_LRADC_IRQ_EN(0), 185 + adc->base + LRADC_CTRL1 + STMP_OFFSET_REG_SET); 186 + writel(BIT(0), adc->base + LRADC_CTRL0 + STMP_OFFSET_REG_SET); 187 + 188 + /* Wait for completion on the channel, 1 second max. */ 189 + ret = wait_for_completion_killable_timeout(&adc->completion, HZ); 190 + if (!ret) 191 + ret = -ETIMEDOUT; 192 + if (ret < 0) 193 + goto err; 194 + 195 + /* Read the data. */ 196 + *val = readl(adc->base + LRADC_CH(0)) & LRADC_CH_VALUE_MASK; 197 + ret = IIO_VAL_INT; 198 + 199 + err: 200 + writel(LRADC_CTRL1_LRADC_IRQ_EN(0), 201 + adc->base + LRADC_CTRL1 + STMP_OFFSET_REG_CLR); 202 + 203 + iio_device_release_direct_mode(iio_dev); 204 + 205 + return ret; 206 + } 207 + 208 + static int mxs_lradc_adc_read_temp(struct iio_dev *iio_dev, int *val) 209 + { 210 + int ret, min, max; 211 + 212 + ret = mxs_lradc_adc_read_single(iio_dev, 8, &min); 213 + if (ret != IIO_VAL_INT) 214 + return ret; 215 + 216 + ret = mxs_lradc_adc_read_single(iio_dev, 9, &max); 217 + if (ret != IIO_VAL_INT) 218 + return ret; 219 + 220 + *val = max - min; 221 + 222 + return IIO_VAL_INT; 223 + } 224 + 225 + static int mxs_lradc_adc_read_raw(struct iio_dev *iio_dev, 226 + const struct iio_chan_spec *chan, 227 + int *val, int *val2, long m) 228 + { 229 + struct mxs_lradc_adc *adc = iio_priv(iio_dev); 230 + 231 + switch (m) { 232 + case IIO_CHAN_INFO_RAW: 233 + if (chan->type == IIO_TEMP) 234 + return mxs_lradc_adc_read_temp(iio_dev, val); 235 + 236 + return mxs_lradc_adc_read_single(iio_dev, chan->channel, val); 237 + 238 + case IIO_CHAN_INFO_SCALE: 239 + if (chan->type == IIO_TEMP) { 240 + /* 241 + * From the datasheet, we have to multiply by 1.012 and 242 + * divide by 4 243 + */ 244 + *val = 0; 245 + *val2 = 253000; 246 + return IIO_VAL_INT_PLUS_MICRO; 247 + } 248 + 249 + *val = adc->vref_mv[chan->channel]; 250 + *val2 = chan->scan_type.realbits - 251 + test_bit(chan->channel, &adc->is_divided); 252 + return IIO_VAL_FRACTIONAL_LOG2; 253 + 254 + case IIO_CHAN_INFO_OFFSET: 255 + if (chan->type == IIO_TEMP) { 256 + /* 257 + * The calculated value from the ADC is in Kelvin, we 258 + * want Celsius for hwmon so the offset is -273.15 259 + * The offset is applied before scaling so it is 260 + * actually -213.15 * 4 / 1.012 = -1079.644268 261 + */ 262 + *val = -1079; 263 + *val2 = 644268; 264 + 265 + return IIO_VAL_INT_PLUS_MICRO; 266 + } 267 + 268 + return -EINVAL; 269 + 270 + default: 271 + break; 272 + } 273 + 274 + return -EINVAL; 275 + } 276 + 277 + static int mxs_lradc_adc_write_raw(struct iio_dev *iio_dev, 278 + const struct iio_chan_spec *chan, 279 + int val, int val2, long m) 280 + { 281 + struct mxs_lradc_adc *adc = iio_priv(iio_dev); 282 + struct mxs_lradc_scale *scale_avail = 283 + adc->scale_avail[chan->channel]; 284 + int ret; 285 + 286 + ret = iio_device_claim_direct_mode(iio_dev); 287 + if (ret) 288 + return ret; 289 + 290 + switch (m) { 291 + case IIO_CHAN_INFO_SCALE: 292 + ret = -EINVAL; 293 + if (val == scale_avail[MXS_LRADC_DIV_DISABLED].integer && 294 + val2 == scale_avail[MXS_LRADC_DIV_DISABLED].nano) { 295 + /* divider by two disabled */ 296 + clear_bit(chan->channel, &adc->is_divided); 297 + ret = 0; 298 + } else if (val == scale_avail[MXS_LRADC_DIV_ENABLED].integer && 299 + val2 == scale_avail[MXS_LRADC_DIV_ENABLED].nano) { 300 + /* divider by two enabled */ 301 + set_bit(chan->channel, &adc->is_divided); 302 + ret = 0; 303 + } 304 + 305 + break; 306 + default: 307 + ret = -EINVAL; 308 + break; 309 + } 310 + 311 + iio_device_release_direct_mode(iio_dev); 312 + 313 + return ret; 314 + } 315 + 316 + static int mxs_lradc_adc_write_raw_get_fmt(struct iio_dev *iio_dev, 317 + const struct iio_chan_spec *chan, 318 + long m) 319 + { 320 + return IIO_VAL_INT_PLUS_NANO; 321 + } 322 + 323 + static ssize_t mxs_lradc_adc_show_scale_avail(struct device *dev, 324 + struct device_attribute *attr, 325 + char *buf) 326 + { 327 + struct iio_dev *iio = dev_to_iio_dev(dev); 328 + struct mxs_lradc_adc *adc = iio_priv(iio); 329 + struct iio_dev_attr *iio_attr = to_iio_dev_attr(attr); 330 + int i, ch, len = 0; 331 + 332 + ch = iio_attr->address; 333 + for (i = 0; i < ARRAY_SIZE(adc->scale_avail[ch]); i++) 334 + len += sprintf(buf + len, "%u.%09u ", 335 + adc->scale_avail[ch][i].integer, 336 + adc->scale_avail[ch][i].nano); 337 + 338 + len += sprintf(buf + len, "\n"); 339 + 340 + return len; 341 + } 342 + 343 + #define SHOW_SCALE_AVAILABLE_ATTR(ch)\ 344 + IIO_DEVICE_ATTR(in_voltage##ch##_scale_available, 0444,\ 345 + mxs_lradc_adc_show_scale_avail, NULL, ch) 346 + 347 + SHOW_SCALE_AVAILABLE_ATTR(0); 348 + SHOW_SCALE_AVAILABLE_ATTR(1); 349 + SHOW_SCALE_AVAILABLE_ATTR(2); 350 + SHOW_SCALE_AVAILABLE_ATTR(3); 351 + SHOW_SCALE_AVAILABLE_ATTR(4); 352 + SHOW_SCALE_AVAILABLE_ATTR(5); 353 + SHOW_SCALE_AVAILABLE_ATTR(6); 354 + SHOW_SCALE_AVAILABLE_ATTR(7); 355 + SHOW_SCALE_AVAILABLE_ATTR(10); 356 + SHOW_SCALE_AVAILABLE_ATTR(11); 357 + SHOW_SCALE_AVAILABLE_ATTR(12); 358 + SHOW_SCALE_AVAILABLE_ATTR(13); 359 + SHOW_SCALE_AVAILABLE_ATTR(14); 360 + SHOW_SCALE_AVAILABLE_ATTR(15); 361 + 362 + static struct attribute *mxs_lradc_adc_attributes[] = { 363 + &iio_dev_attr_in_voltage0_scale_available.dev_attr.attr, 364 + &iio_dev_attr_in_voltage1_scale_available.dev_attr.attr, 365 + &iio_dev_attr_in_voltage2_scale_available.dev_attr.attr, 366 + &iio_dev_attr_in_voltage3_scale_available.dev_attr.attr, 367 + &iio_dev_attr_in_voltage4_scale_available.dev_attr.attr, 368 + &iio_dev_attr_in_voltage5_scale_available.dev_attr.attr, 369 + &iio_dev_attr_in_voltage6_scale_available.dev_attr.attr, 370 + &iio_dev_attr_in_voltage7_scale_available.dev_attr.attr, 371 + &iio_dev_attr_in_voltage10_scale_available.dev_attr.attr, 372 + &iio_dev_attr_in_voltage11_scale_available.dev_attr.attr, 373 + &iio_dev_attr_in_voltage12_scale_available.dev_attr.attr, 374 + &iio_dev_attr_in_voltage13_scale_available.dev_attr.attr, 375 + &iio_dev_attr_in_voltage14_scale_available.dev_attr.attr, 376 + &iio_dev_attr_in_voltage15_scale_available.dev_attr.attr, 377 + NULL 378 + }; 379 + 380 + static const struct attribute_group mxs_lradc_adc_attribute_group = { 381 + .attrs = mxs_lradc_adc_attributes, 382 + }; 383 + 384 + static const struct iio_info mxs_lradc_adc_iio_info = { 385 + .driver_module = THIS_MODULE, 386 + .read_raw = mxs_lradc_adc_read_raw, 387 + .write_raw = mxs_lradc_adc_write_raw, 388 + .write_raw_get_fmt = mxs_lradc_adc_write_raw_get_fmt, 389 + .attrs = &mxs_lradc_adc_attribute_group, 390 + }; 391 + 392 + /* IRQ Handling */ 393 + static irqreturn_t mxs_lradc_adc_handle_irq(int irq, void *data) 394 + { 395 + struct iio_dev *iio = data; 396 + struct mxs_lradc_adc *adc = iio_priv(iio); 397 + struct mxs_lradc *lradc = adc->lradc; 398 + unsigned long reg = readl(adc->base + LRADC_CTRL1); 399 + unsigned long flags; 400 + 401 + if (!(reg & mxs_lradc_irq_mask(lradc))) 402 + return IRQ_NONE; 403 + 404 + if (iio_buffer_enabled(iio)) { 405 + if (reg & lradc->buffer_vchans) { 406 + spin_lock_irqsave(&adc->lock, flags); 407 + iio_trigger_poll(iio->trig); 408 + spin_unlock_irqrestore(&adc->lock, flags); 409 + } 410 + } else if (reg & LRADC_CTRL1_LRADC_IRQ(0)) { 411 + complete(&adc->completion); 412 + } 413 + 414 + writel(reg & mxs_lradc_irq_mask(lradc), 415 + adc->base + LRADC_CTRL1 + STMP_OFFSET_REG_CLR); 416 + 417 + return IRQ_HANDLED; 418 + } 419 + 420 + 421 + /* Trigger handling */ 422 + static irqreturn_t mxs_lradc_adc_trigger_handler(int irq, void *p) 423 + { 424 + struct iio_poll_func *pf = p; 425 + struct iio_dev *iio = pf->indio_dev; 426 + struct mxs_lradc_adc *adc = iio_priv(iio); 427 + const u32 chan_value = LRADC_CH_ACCUMULATE | 428 + ((LRADC_DELAY_TIMER_LOOP - 1) << LRADC_CH_NUM_SAMPLES_OFFSET); 429 + unsigned int i, j = 0; 430 + 431 + for_each_set_bit(i, iio->active_scan_mask, LRADC_MAX_TOTAL_CHANS) { 432 + adc->buffer[j] = readl(adc->base + LRADC_CH(j)); 433 + writel(chan_value, adc->base + LRADC_CH(j)); 434 + adc->buffer[j] &= LRADC_CH_VALUE_MASK; 435 + adc->buffer[j] /= LRADC_DELAY_TIMER_LOOP; 436 + j++; 437 + } 438 + 439 + iio_push_to_buffers_with_timestamp(iio, adc->buffer, pf->timestamp); 440 + 441 + iio_trigger_notify_done(iio->trig); 442 + 443 + return IRQ_HANDLED; 444 + } 445 + 446 + static int mxs_lradc_adc_configure_trigger(struct iio_trigger *trig, bool state) 447 + { 448 + struct iio_dev *iio = iio_trigger_get_drvdata(trig); 449 + struct mxs_lradc_adc *adc = iio_priv(iio); 450 + const u32 st = state ? STMP_OFFSET_REG_SET : STMP_OFFSET_REG_CLR; 451 + 452 + writel(LRADC_DELAY_KICK, adc->base + (LRADC_DELAY(0) + st)); 453 + 454 + return 0; 455 + } 456 + 457 + static const struct iio_trigger_ops mxs_lradc_adc_trigger_ops = { 458 + .owner = THIS_MODULE, 459 + .set_trigger_state = &mxs_lradc_adc_configure_trigger, 460 + }; 461 + 462 + static int mxs_lradc_adc_trigger_init(struct iio_dev *iio) 463 + { 464 + int ret; 465 + struct iio_trigger *trig; 466 + struct mxs_lradc_adc *adc = iio_priv(iio); 467 + 468 + trig = devm_iio_trigger_alloc(&iio->dev, "%s-dev%i", iio->name, 469 + iio->id); 470 + 471 + trig->dev.parent = adc->dev; 472 + iio_trigger_set_drvdata(trig, iio); 473 + trig->ops = &mxs_lradc_adc_trigger_ops; 474 + 475 + ret = iio_trigger_register(trig); 476 + if (ret) 477 + return ret; 478 + 479 + adc->trig = trig; 480 + 481 + return 0; 482 + } 483 + 484 + static void mxs_lradc_adc_trigger_remove(struct iio_dev *iio) 485 + { 486 + struct mxs_lradc_adc *adc = iio_priv(iio); 487 + 488 + iio_trigger_unregister(adc->trig); 489 + } 490 + 491 + static int mxs_lradc_adc_buffer_preenable(struct iio_dev *iio) 492 + { 493 + struct mxs_lradc_adc *adc = iio_priv(iio); 494 + struct mxs_lradc *lradc = adc->lradc; 495 + int chan, ofs = 0; 496 + unsigned long enable = 0; 497 + u32 ctrl4_set = 0; 498 + u32 ctrl4_clr = 0; 499 + u32 ctrl1_irq = 0; 500 + const u32 chan_value = LRADC_CH_ACCUMULATE | 501 + ((LRADC_DELAY_TIMER_LOOP - 1) << LRADC_CH_NUM_SAMPLES_OFFSET); 502 + 503 + if (lradc->soc == IMX28_LRADC) 504 + writel(lradc->buffer_vchans << LRADC_CTRL1_LRADC_IRQ_EN_OFFSET, 505 + adc->base + LRADC_CTRL1 + STMP_OFFSET_REG_CLR); 506 + writel(lradc->buffer_vchans, 507 + adc->base + LRADC_CTRL0 + STMP_OFFSET_REG_CLR); 508 + 509 + for_each_set_bit(chan, iio->active_scan_mask, LRADC_MAX_TOTAL_CHANS) { 510 + ctrl4_set |= chan << LRADC_CTRL4_LRADCSELECT_OFFSET(ofs); 511 + ctrl4_clr |= LRADC_CTRL4_LRADCSELECT_MASK(ofs); 512 + ctrl1_irq |= LRADC_CTRL1_LRADC_IRQ_EN(ofs); 513 + writel(chan_value, adc->base + LRADC_CH(ofs)); 514 + bitmap_set(&enable, ofs, 1); 515 + ofs++; 516 + } 517 + 518 + writel(LRADC_DELAY_TRIGGER_LRADCS_MASK | LRADC_DELAY_KICK, 519 + adc->base + LRADC_DELAY(0) + STMP_OFFSET_REG_CLR); 520 + writel(ctrl4_clr, adc->base + LRADC_CTRL4 + STMP_OFFSET_REG_CLR); 521 + writel(ctrl4_set, adc->base + LRADC_CTRL4 + STMP_OFFSET_REG_SET); 522 + writel(ctrl1_irq, adc->base + LRADC_CTRL1 + STMP_OFFSET_REG_SET); 523 + writel(enable << LRADC_DELAY_TRIGGER_LRADCS_OFFSET, 524 + adc->base + LRADC_DELAY(0) + STMP_OFFSET_REG_SET); 525 + 526 + return 0; 527 + } 528 + 529 + static int mxs_lradc_adc_buffer_postdisable(struct iio_dev *iio) 530 + { 531 + struct mxs_lradc_adc *adc = iio_priv(iio); 532 + struct mxs_lradc *lradc = adc->lradc; 533 + 534 + writel(LRADC_DELAY_TRIGGER_LRADCS_MASK | LRADC_DELAY_KICK, 535 + adc->base + LRADC_DELAY(0) + STMP_OFFSET_REG_CLR); 536 + 537 + writel(lradc->buffer_vchans, 538 + adc->base + LRADC_CTRL0 + STMP_OFFSET_REG_CLR); 539 + if (lradc->soc == IMX28_LRADC) 540 + writel(lradc->buffer_vchans << LRADC_CTRL1_LRADC_IRQ_EN_OFFSET, 541 + adc->base + LRADC_CTRL1 + STMP_OFFSET_REG_CLR); 542 + 543 + return 0; 544 + } 545 + 546 + static bool mxs_lradc_adc_validate_scan_mask(struct iio_dev *iio, 547 + const unsigned long *mask) 548 + { 549 + struct mxs_lradc_adc *adc = iio_priv(iio); 550 + struct mxs_lradc *lradc = adc->lradc; 551 + const int map_chans = bitmap_weight(mask, LRADC_MAX_TOTAL_CHANS); 552 + int rsvd_chans = 0; 553 + unsigned long rsvd_mask = 0; 554 + 555 + if (lradc->use_touchbutton) 556 + rsvd_mask |= CHAN_MASK_TOUCHBUTTON; 557 + if (lradc->touchscreen_wire == MXS_LRADC_TOUCHSCREEN_4WIRE) 558 + rsvd_mask |= CHAN_MASK_TOUCHSCREEN_4WIRE; 559 + if (lradc->touchscreen_wire == MXS_LRADC_TOUCHSCREEN_5WIRE) 560 + rsvd_mask |= CHAN_MASK_TOUCHSCREEN_5WIRE; 561 + 562 + if (lradc->use_touchbutton) 563 + rsvd_chans++; 564 + if (lradc->touchscreen_wire) 565 + rsvd_chans += 2; 566 + 567 + /* Test for attempts to map channels with special mode of operation. */ 568 + if (bitmap_intersects(mask, &rsvd_mask, LRADC_MAX_TOTAL_CHANS)) 569 + return false; 570 + 571 + /* Test for attempts to map more channels then available slots. */ 572 + if (map_chans + rsvd_chans > LRADC_MAX_MAPPED_CHANS) 573 + return false; 574 + 575 + return true; 576 + } 577 + 578 + static const struct iio_buffer_setup_ops mxs_lradc_adc_buffer_ops = { 579 + .preenable = &mxs_lradc_adc_buffer_preenable, 580 + .postenable = &iio_triggered_buffer_postenable, 581 + .predisable = &iio_triggered_buffer_predisable, 582 + .postdisable = &mxs_lradc_adc_buffer_postdisable, 583 + .validate_scan_mask = &mxs_lradc_adc_validate_scan_mask, 584 + }; 585 + 586 + /* Driver initialization */ 587 + #define MXS_ADC_CHAN(idx, chan_type, name) { \ 588 + .type = (chan_type), \ 589 + .indexed = 1, \ 590 + .scan_index = (idx), \ 591 + .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ 592 + BIT(IIO_CHAN_INFO_SCALE), \ 593 + .channel = (idx), \ 594 + .address = (idx), \ 595 + .scan_type = { \ 596 + .sign = 'u', \ 597 + .realbits = LRADC_RESOLUTION, \ 598 + .storagebits = 32, \ 599 + }, \ 600 + .datasheet_name = (name), \ 601 + } 602 + 603 + static const struct iio_chan_spec mx23_lradc_chan_spec[] = { 604 + MXS_ADC_CHAN(0, IIO_VOLTAGE, "LRADC0"), 605 + MXS_ADC_CHAN(1, IIO_VOLTAGE, "LRADC1"), 606 + MXS_ADC_CHAN(2, IIO_VOLTAGE, "LRADC2"), 607 + MXS_ADC_CHAN(3, IIO_VOLTAGE, "LRADC3"), 608 + MXS_ADC_CHAN(4, IIO_VOLTAGE, "LRADC4"), 609 + MXS_ADC_CHAN(5, IIO_VOLTAGE, "LRADC5"), 610 + MXS_ADC_CHAN(6, IIO_VOLTAGE, "VDDIO"), 611 + MXS_ADC_CHAN(7, IIO_VOLTAGE, "VBATT"), 612 + /* Combined Temperature sensors */ 613 + { 614 + .type = IIO_TEMP, 615 + .indexed = 1, 616 + .scan_index = 8, 617 + .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | 618 + BIT(IIO_CHAN_INFO_OFFSET) | 619 + BIT(IIO_CHAN_INFO_SCALE), 620 + .channel = 8, 621 + .scan_type = {.sign = 'u', .realbits = 18, .storagebits = 32,}, 622 + .datasheet_name = "TEMP_DIE", 623 + }, 624 + /* Hidden channel to keep indexes */ 625 + { 626 + .type = IIO_TEMP, 627 + .indexed = 1, 628 + .scan_index = -1, 629 + .channel = 9, 630 + }, 631 + MXS_ADC_CHAN(10, IIO_VOLTAGE, NULL), 632 + MXS_ADC_CHAN(11, IIO_VOLTAGE, NULL), 633 + MXS_ADC_CHAN(12, IIO_VOLTAGE, "USB_DP"), 634 + MXS_ADC_CHAN(13, IIO_VOLTAGE, "USB_DN"), 635 + MXS_ADC_CHAN(14, IIO_VOLTAGE, "VBG"), 636 + MXS_ADC_CHAN(15, IIO_VOLTAGE, "VDD5V"), 637 + }; 638 + 639 + static const struct iio_chan_spec mx28_lradc_chan_spec[] = { 640 + MXS_ADC_CHAN(0, IIO_VOLTAGE, "LRADC0"), 641 + MXS_ADC_CHAN(1, IIO_VOLTAGE, "LRADC1"), 642 + MXS_ADC_CHAN(2, IIO_VOLTAGE, "LRADC2"), 643 + MXS_ADC_CHAN(3, IIO_VOLTAGE, "LRADC3"), 644 + MXS_ADC_CHAN(4, IIO_VOLTAGE, "LRADC4"), 645 + MXS_ADC_CHAN(5, IIO_VOLTAGE, "LRADC5"), 646 + MXS_ADC_CHAN(6, IIO_VOLTAGE, "LRADC6"), 647 + MXS_ADC_CHAN(7, IIO_VOLTAGE, "VBATT"), 648 + /* Combined Temperature sensors */ 649 + { 650 + .type = IIO_TEMP, 651 + .indexed = 1, 652 + .scan_index = 8, 653 + .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | 654 + BIT(IIO_CHAN_INFO_OFFSET) | 655 + BIT(IIO_CHAN_INFO_SCALE), 656 + .channel = 8, 657 + .scan_type = {.sign = 'u', .realbits = 18, .storagebits = 32,}, 658 + .datasheet_name = "TEMP_DIE", 659 + }, 660 + /* Hidden channel to keep indexes */ 661 + { 662 + .type = IIO_TEMP, 663 + .indexed = 1, 664 + .scan_index = -1, 665 + .channel = 9, 666 + }, 667 + MXS_ADC_CHAN(10, IIO_VOLTAGE, "VDDIO"), 668 + MXS_ADC_CHAN(11, IIO_VOLTAGE, "VTH"), 669 + MXS_ADC_CHAN(12, IIO_VOLTAGE, "VDDA"), 670 + MXS_ADC_CHAN(13, IIO_VOLTAGE, "VDDD"), 671 + MXS_ADC_CHAN(14, IIO_VOLTAGE, "VBG"), 672 + MXS_ADC_CHAN(15, IIO_VOLTAGE, "VDD5V"), 673 + }; 674 + 675 + static void mxs_lradc_adc_hw_init(struct mxs_lradc_adc *adc) 676 + { 677 + /* The ADC always uses DELAY CHANNEL 0. */ 678 + const u32 adc_cfg = 679 + (1 << (LRADC_DELAY_TRIGGER_DELAYS_OFFSET + 0)) | 680 + (LRADC_DELAY_TIMER_PER << LRADC_DELAY_DELAY_OFFSET); 681 + 682 + /* Configure DELAY CHANNEL 0 for generic ADC sampling. */ 683 + writel(adc_cfg, adc->base + LRADC_DELAY(0)); 684 + 685 + /* 686 + * Start internal temperature sensing by clearing bit 687 + * HW_LRADC_CTRL2_TEMPSENSE_PWD. This bit can be left cleared 688 + * after power up. 689 + */ 690 + writel(0, adc->base + LRADC_CTRL2); 691 + } 692 + 693 + static void mxs_lradc_adc_hw_stop(struct mxs_lradc_adc *adc) 694 + { 695 + writel(0, adc->base + LRADC_DELAY(0)); 696 + } 697 + 698 + static int mxs_lradc_adc_probe(struct platform_device *pdev) 699 + { 700 + struct device *dev = &pdev->dev; 701 + struct mxs_lradc *lradc = dev_get_drvdata(dev->parent); 702 + struct mxs_lradc_adc *adc; 703 + struct iio_dev *iio; 704 + struct resource *iores; 705 + int ret, irq, virq, i, s, n; 706 + u64 scale_uv; 707 + const char **irq_name; 708 + 709 + /* Allocate the IIO device. */ 710 + iio = devm_iio_device_alloc(dev, sizeof(*adc)); 711 + if (!iio) { 712 + dev_err(dev, "Failed to allocate IIO device\n"); 713 + return -ENOMEM; 714 + } 715 + 716 + adc = iio_priv(iio); 717 + adc->lradc = lradc; 718 + adc->dev = dev; 719 + 720 + iores = platform_get_resource(pdev, IORESOURCE_MEM, 0); 721 + adc->base = devm_ioremap(dev, iores->start, resource_size(iores)); 722 + if (IS_ERR(adc->base)) 723 + return PTR_ERR(adc->base); 724 + 725 + init_completion(&adc->completion); 726 + spin_lock_init(&adc->lock); 727 + 728 + platform_set_drvdata(pdev, iio); 729 + 730 + iio->name = pdev->name; 731 + iio->dev.parent = dev; 732 + iio->dev.of_node = dev->parent->of_node; 733 + iio->info = &mxs_lradc_adc_iio_info; 734 + iio->modes = INDIO_DIRECT_MODE; 735 + iio->masklength = LRADC_MAX_TOTAL_CHANS; 736 + 737 + if (lradc->soc == IMX23_LRADC) { 738 + iio->channels = mx23_lradc_chan_spec; 739 + iio->num_channels = ARRAY_SIZE(mx23_lradc_chan_spec); 740 + irq_name = mx23_lradc_adc_irq_names; 741 + n = ARRAY_SIZE(mx23_lradc_adc_irq_names); 742 + } else { 743 + iio->channels = mx28_lradc_chan_spec; 744 + iio->num_channels = ARRAY_SIZE(mx28_lradc_chan_spec); 745 + irq_name = mx28_lradc_adc_irq_names; 746 + n = ARRAY_SIZE(mx28_lradc_adc_irq_names); 747 + } 748 + 749 + ret = stmp_reset_block(adc->base); 750 + if (ret) 751 + return ret; 752 + 753 + for (i = 0; i < n; i++) { 754 + irq = platform_get_irq_byname(pdev, irq_name[i]); 755 + if (irq < 0) 756 + return irq; 757 + 758 + virq = irq_of_parse_and_map(dev->parent->of_node, irq); 759 + 760 + ret = devm_request_irq(dev, virq, mxs_lradc_adc_handle_irq, 761 + 0, irq_name[i], iio); 762 + if (ret) 763 + return ret; 764 + } 765 + 766 + ret = mxs_lradc_adc_trigger_init(iio); 767 + if (ret) 768 + goto err_trig; 769 + 770 + ret = iio_triggered_buffer_setup(iio, &iio_pollfunc_store_time, 771 + &mxs_lradc_adc_trigger_handler, 772 + &mxs_lradc_adc_buffer_ops); 773 + if (ret) 774 + return ret; 775 + 776 + adc->vref_mv = mxs_lradc_adc_vref_mv[lradc->soc]; 777 + 778 + /* Populate available ADC input ranges */ 779 + for (i = 0; i < LRADC_MAX_TOTAL_CHANS; i++) { 780 + for (s = 0; s < ARRAY_SIZE(adc->scale_avail[i]); s++) { 781 + /* 782 + * [s=0] = optional divider by two disabled (default) 783 + * [s=1] = optional divider by two enabled 784 + * 785 + * The scale is calculated by doing: 786 + * Vref >> (realbits - s) 787 + * which multiplies by two on the second component 788 + * of the array. 789 + */ 790 + scale_uv = ((u64)adc->vref_mv[i] * 100000000) >> 791 + (LRADC_RESOLUTION - s); 792 + adc->scale_avail[i][s].nano = 793 + do_div(scale_uv, 100000000) * 10; 794 + adc->scale_avail[i][s].integer = scale_uv; 795 + } 796 + } 797 + 798 + /* Configure the hardware. */ 799 + mxs_lradc_adc_hw_init(adc); 800 + 801 + /* Register IIO device. */ 802 + ret = iio_device_register(iio); 803 + if (ret) { 804 + dev_err(dev, "Failed to register IIO device\n"); 805 + goto err_dev; 806 + } 807 + 808 + return 0; 809 + 810 + err_dev: 811 + mxs_lradc_adc_hw_stop(adc); 812 + mxs_lradc_adc_trigger_remove(iio); 813 + err_trig: 814 + iio_triggered_buffer_cleanup(iio); 815 + return ret; 816 + } 817 + 818 + static int mxs_lradc_adc_remove(struct platform_device *pdev) 819 + { 820 + struct iio_dev *iio = platform_get_drvdata(pdev); 821 + struct mxs_lradc_adc *adc = iio_priv(iio); 822 + 823 + iio_device_unregister(iio); 824 + mxs_lradc_adc_hw_stop(adc); 825 + mxs_lradc_adc_trigger_remove(iio); 826 + iio_triggered_buffer_cleanup(iio); 827 + 828 + return 0; 829 + } 830 + 831 + static struct platform_driver mxs_lradc_adc_driver = { 832 + .driver = { 833 + .name = "mxs-lradc-adc", 834 + }, 835 + .probe = mxs_lradc_adc_probe, 836 + .remove = mxs_lradc_adc_remove, 837 + }; 838 + module_platform_driver(mxs_lradc_adc_driver); 839 + 840 + MODULE_AUTHOR("Marek Vasut <marex@denx.de>"); 841 + MODULE_DESCRIPTION("Freescale MXS LRADC driver general purpose ADC driver"); 842 + MODULE_LICENSE("GPL"); 843 + MODULE_ALIAS("platform:mxs-lradc-adc");
-1750
drivers/iio/adc/mxs-lradc.c
··· 1 - /* 2 - * Freescale MXS LRADC driver 3 - * 4 - * Copyright (c) 2012 DENX Software Engineering, GmbH. 5 - * Marek Vasut <marex@denx.de> 6 - * 7 - * This program is free software; you can redistribute it and/or modify 8 - * it under the terms of the GNU General Public License as published by 9 - * the Free Software Foundation; either version 2 of the License, or 10 - * (at your option) any later version. 11 - * 12 - * This program is distributed in the hope that it will be useful, 13 - * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 - * GNU General Public License for more details. 16 - */ 17 - 18 - #include <linux/bitops.h> 19 - #include <linux/clk.h> 20 - #include <linux/completion.h> 21 - #include <linux/device.h> 22 - #include <linux/err.h> 23 - #include <linux/input.h> 24 - #include <linux/interrupt.h> 25 - #include <linux/io.h> 26 - #include <linux/kernel.h> 27 - #include <linux/module.h> 28 - #include <linux/mutex.h> 29 - #include <linux/of.h> 30 - #include <linux/of_device.h> 31 - #include <linux/platform_device.h> 32 - #include <linux/slab.h> 33 - #include <linux/stmp_device.h> 34 - #include <linux/sysfs.h> 35 - 36 - #include <linux/iio/buffer.h> 37 - #include <linux/iio/iio.h> 38 - #include <linux/iio/trigger.h> 39 - #include <linux/iio/trigger_consumer.h> 40 - #include <linux/iio/triggered_buffer.h> 41 - #include <linux/iio/sysfs.h> 42 - 43 - #define DRIVER_NAME "mxs-lradc" 44 - 45 - #define LRADC_MAX_DELAY_CHANS 4 46 - #define LRADC_MAX_MAPPED_CHANS 8 47 - #define LRADC_MAX_TOTAL_CHANS 16 48 - 49 - #define LRADC_DELAY_TIMER_HZ 2000 50 - 51 - /* 52 - * Make this runtime configurable if necessary. Currently, if the buffered mode 53 - * is enabled, the LRADC takes LRADC_DELAY_TIMER_LOOP samples of data before 54 - * triggering IRQ. The sampling happens every (LRADC_DELAY_TIMER_PER / 2000) 55 - * seconds. The result is that the samples arrive every 500mS. 56 - */ 57 - #define LRADC_DELAY_TIMER_PER 200 58 - #define LRADC_DELAY_TIMER_LOOP 5 59 - 60 - /* 61 - * Once the pen touches the touchscreen, the touchscreen switches from 62 - * IRQ-driven mode to polling mode to prevent interrupt storm. The polling 63 - * is realized by worker thread, which is called every 20 or so milliseconds. 64 - * This gives the touchscreen enough fluency and does not strain the system 65 - * too much. 66 - */ 67 - #define LRADC_TS_SAMPLE_DELAY_MS 5 68 - 69 - /* 70 - * The LRADC reads the following amount of samples from each touchscreen 71 - * channel and the driver then computes average of these. 72 - */ 73 - #define LRADC_TS_SAMPLE_AMOUNT 4 74 - 75 - enum mxs_lradc_id { 76 - IMX23_LRADC, 77 - IMX28_LRADC, 78 - }; 79 - 80 - static const char * const mx23_lradc_irq_names[] = { 81 - "mxs-lradc-touchscreen", 82 - "mxs-lradc-channel0", 83 - "mxs-lradc-channel1", 84 - "mxs-lradc-channel2", 85 - "mxs-lradc-channel3", 86 - "mxs-lradc-channel4", 87 - "mxs-lradc-channel5", 88 - "mxs-lradc-channel6", 89 - "mxs-lradc-channel7", 90 - }; 91 - 92 - static const char * const mx28_lradc_irq_names[] = { 93 - "mxs-lradc-touchscreen", 94 - "mxs-lradc-thresh0", 95 - "mxs-lradc-thresh1", 96 - "mxs-lradc-channel0", 97 - "mxs-lradc-channel1", 98 - "mxs-lradc-channel2", 99 - "mxs-lradc-channel3", 100 - "mxs-lradc-channel4", 101 - "mxs-lradc-channel5", 102 - "mxs-lradc-channel6", 103 - "mxs-lradc-channel7", 104 - "mxs-lradc-button0", 105 - "mxs-lradc-button1", 106 - }; 107 - 108 - struct mxs_lradc_of_config { 109 - const int irq_count; 110 - const char * const *irq_name; 111 - const u32 *vref_mv; 112 - }; 113 - 114 - #define VREF_MV_BASE 1850 115 - 116 - static const u32 mx23_vref_mv[LRADC_MAX_TOTAL_CHANS] = { 117 - VREF_MV_BASE, /* CH0 */ 118 - VREF_MV_BASE, /* CH1 */ 119 - VREF_MV_BASE, /* CH2 */ 120 - VREF_MV_BASE, /* CH3 */ 121 - VREF_MV_BASE, /* CH4 */ 122 - VREF_MV_BASE, /* CH5 */ 123 - VREF_MV_BASE * 2, /* CH6 VDDIO */ 124 - VREF_MV_BASE * 4, /* CH7 VBATT */ 125 - VREF_MV_BASE, /* CH8 Temp sense 0 */ 126 - VREF_MV_BASE, /* CH9 Temp sense 1 */ 127 - VREF_MV_BASE, /* CH10 */ 128 - VREF_MV_BASE, /* CH11 */ 129 - VREF_MV_BASE, /* CH12 USB_DP */ 130 - VREF_MV_BASE, /* CH13 USB_DN */ 131 - VREF_MV_BASE, /* CH14 VBG */ 132 - VREF_MV_BASE * 4, /* CH15 VDD5V */ 133 - }; 134 - 135 - static const u32 mx28_vref_mv[LRADC_MAX_TOTAL_CHANS] = { 136 - VREF_MV_BASE, /* CH0 */ 137 - VREF_MV_BASE, /* CH1 */ 138 - VREF_MV_BASE, /* CH2 */ 139 - VREF_MV_BASE, /* CH3 */ 140 - VREF_MV_BASE, /* CH4 */ 141 - VREF_MV_BASE, /* CH5 */ 142 - VREF_MV_BASE, /* CH6 */ 143 - VREF_MV_BASE * 4, /* CH7 VBATT */ 144 - VREF_MV_BASE, /* CH8 Temp sense 0 */ 145 - VREF_MV_BASE, /* CH9 Temp sense 1 */ 146 - VREF_MV_BASE * 2, /* CH10 VDDIO */ 147 - VREF_MV_BASE, /* CH11 VTH */ 148 - VREF_MV_BASE * 2, /* CH12 VDDA */ 149 - VREF_MV_BASE, /* CH13 VDDD */ 150 - VREF_MV_BASE, /* CH14 VBG */ 151 - VREF_MV_BASE * 4, /* CH15 VDD5V */ 152 - }; 153 - 154 - static const struct mxs_lradc_of_config mxs_lradc_of_config[] = { 155 - [IMX23_LRADC] = { 156 - .irq_count = ARRAY_SIZE(mx23_lradc_irq_names), 157 - .irq_name = mx23_lradc_irq_names, 158 - .vref_mv = mx23_vref_mv, 159 - }, 160 - [IMX28_LRADC] = { 161 - .irq_count = ARRAY_SIZE(mx28_lradc_irq_names), 162 - .irq_name = mx28_lradc_irq_names, 163 - .vref_mv = mx28_vref_mv, 164 - }, 165 - }; 166 - 167 - enum mxs_lradc_ts { 168 - MXS_LRADC_TOUCHSCREEN_NONE = 0, 169 - MXS_LRADC_TOUCHSCREEN_4WIRE, 170 - MXS_LRADC_TOUCHSCREEN_5WIRE, 171 - }; 172 - 173 - /* 174 - * Touchscreen handling 175 - */ 176 - enum lradc_ts_plate { 177 - LRADC_TOUCH = 0, 178 - LRADC_SAMPLE_X, 179 - LRADC_SAMPLE_Y, 180 - LRADC_SAMPLE_PRESSURE, 181 - LRADC_SAMPLE_VALID, 182 - }; 183 - 184 - enum mxs_lradc_divbytwo { 185 - MXS_LRADC_DIV_DISABLED = 0, 186 - MXS_LRADC_DIV_ENABLED, 187 - }; 188 - 189 - struct mxs_lradc_scale { 190 - unsigned int integer; 191 - unsigned int nano; 192 - }; 193 - 194 - struct mxs_lradc { 195 - struct device *dev; 196 - void __iomem *base; 197 - int irq[13]; 198 - 199 - struct clk *clk; 200 - 201 - u32 *buffer; 202 - struct iio_trigger *trig; 203 - 204 - struct mutex lock; 205 - 206 - struct completion completion; 207 - 208 - const u32 *vref_mv; 209 - struct mxs_lradc_scale scale_avail[LRADC_MAX_TOTAL_CHANS][2]; 210 - unsigned long is_divided; 211 - 212 - /* 213 - * When the touchscreen is enabled, we give it two private virtual 214 - * channels: #6 and #7. This means that only 6 virtual channels (instead 215 - * of 8) will be available for buffered capture. 216 - */ 217 - #define TOUCHSCREEN_VCHANNEL1 7 218 - #define TOUCHSCREEN_VCHANNEL2 6 219 - #define BUFFER_VCHANS_LIMITED 0x3f 220 - #define BUFFER_VCHANS_ALL 0xff 221 - u8 buffer_vchans; 222 - 223 - /* 224 - * Furthermore, certain LRADC channels are shared between touchscreen 225 - * and/or touch-buttons and generic LRADC block. Therefore when using 226 - * either of these, these channels are not available for the regular 227 - * sampling. The shared channels are as follows: 228 - * 229 - * CH0 -- Touch button #0 230 - * CH1 -- Touch button #1 231 - * CH2 -- Touch screen XPUL 232 - * CH3 -- Touch screen YPLL 233 - * CH4 -- Touch screen XNUL 234 - * CH5 -- Touch screen YNLR 235 - * CH6 -- Touch screen WIPER (5-wire only) 236 - * 237 - * The bit fields below represents which parts of the LRADC block are 238 - * switched into special mode of operation. These channels can not 239 - * be sampled as regular LRADC channels. The driver will refuse any 240 - * attempt to sample these channels. 241 - */ 242 - #define CHAN_MASK_TOUCHBUTTON (BIT(1) | BIT(0)) 243 - #define CHAN_MASK_TOUCHSCREEN_4WIRE (0xf << 2) 244 - #define CHAN_MASK_TOUCHSCREEN_5WIRE (0x1f << 2) 245 - enum mxs_lradc_ts use_touchscreen; 246 - bool use_touchbutton; 247 - 248 - struct input_dev *ts_input; 249 - 250 - enum mxs_lradc_id soc; 251 - enum lradc_ts_plate cur_plate; /* state machine */ 252 - bool ts_valid; 253 - unsigned ts_x_pos; 254 - unsigned ts_y_pos; 255 - unsigned ts_pressure; 256 - 257 - /* handle touchscreen's physical behaviour */ 258 - /* samples per coordinate */ 259 - unsigned over_sample_cnt; 260 - /* time clocks between samples */ 261 - unsigned over_sample_delay; 262 - /* time in clocks to wait after the plates where switched */ 263 - unsigned settling_delay; 264 - }; 265 - 266 - #define LRADC_CTRL0 0x00 267 - # define LRADC_CTRL0_MX28_TOUCH_DETECT_ENABLE BIT(23) 268 - # define LRADC_CTRL0_MX28_TOUCH_SCREEN_TYPE BIT(22) 269 - # define LRADC_CTRL0_MX28_YNNSW /* YM */ BIT(21) 270 - # define LRADC_CTRL0_MX28_YPNSW /* YP */ BIT(20) 271 - # define LRADC_CTRL0_MX28_YPPSW /* YP */ BIT(19) 272 - # define LRADC_CTRL0_MX28_XNNSW /* XM */ BIT(18) 273 - # define LRADC_CTRL0_MX28_XNPSW /* XM */ BIT(17) 274 - # define LRADC_CTRL0_MX28_XPPSW /* XP */ BIT(16) 275 - 276 - # define LRADC_CTRL0_MX23_TOUCH_DETECT_ENABLE BIT(20) 277 - # define LRADC_CTRL0_MX23_YM BIT(19) 278 - # define LRADC_CTRL0_MX23_XM BIT(18) 279 - # define LRADC_CTRL0_MX23_YP BIT(17) 280 - # define LRADC_CTRL0_MX23_XP BIT(16) 281 - 282 - # define LRADC_CTRL0_MX28_PLATE_MASK \ 283 - (LRADC_CTRL0_MX28_TOUCH_DETECT_ENABLE | \ 284 - LRADC_CTRL0_MX28_YNNSW | LRADC_CTRL0_MX28_YPNSW | \ 285 - LRADC_CTRL0_MX28_YPPSW | LRADC_CTRL0_MX28_XNNSW | \ 286 - LRADC_CTRL0_MX28_XNPSW | LRADC_CTRL0_MX28_XPPSW) 287 - 288 - # define LRADC_CTRL0_MX23_PLATE_MASK \ 289 - (LRADC_CTRL0_MX23_TOUCH_DETECT_ENABLE | \ 290 - LRADC_CTRL0_MX23_YM | LRADC_CTRL0_MX23_XM | \ 291 - LRADC_CTRL0_MX23_YP | LRADC_CTRL0_MX23_XP) 292 - 293 - #define LRADC_CTRL1 0x10 294 - #define LRADC_CTRL1_TOUCH_DETECT_IRQ_EN BIT(24) 295 - #define LRADC_CTRL1_LRADC_IRQ_EN(n) (1 << ((n) + 16)) 296 - #define LRADC_CTRL1_MX28_LRADC_IRQ_EN_MASK (0x1fff << 16) 297 - #define LRADC_CTRL1_MX23_LRADC_IRQ_EN_MASK (0x01ff << 16) 298 - #define LRADC_CTRL1_LRADC_IRQ_EN_OFFSET 16 299 - #define LRADC_CTRL1_TOUCH_DETECT_IRQ BIT(8) 300 - #define LRADC_CTRL1_LRADC_IRQ(n) (1 << (n)) 301 - #define LRADC_CTRL1_MX28_LRADC_IRQ_MASK 0x1fff 302 - #define LRADC_CTRL1_MX23_LRADC_IRQ_MASK 0x01ff 303 - #define LRADC_CTRL1_LRADC_IRQ_OFFSET 0 304 - 305 - #define LRADC_CTRL2 0x20 306 - #define LRADC_CTRL2_DIVIDE_BY_TWO_OFFSET 24 307 - #define LRADC_CTRL2_TEMPSENSE_PWD BIT(15) 308 - 309 - #define LRADC_STATUS 0x40 310 - #define LRADC_STATUS_TOUCH_DETECT_RAW BIT(0) 311 - 312 - #define LRADC_CH(n) (0x50 + (0x10 * (n))) 313 - #define LRADC_CH_ACCUMULATE BIT(29) 314 - #define LRADC_CH_NUM_SAMPLES_MASK (0x1f << 24) 315 - #define LRADC_CH_NUM_SAMPLES_OFFSET 24 316 - #define LRADC_CH_NUM_SAMPLES(x) \ 317 - ((x) << LRADC_CH_NUM_SAMPLES_OFFSET) 318 - #define LRADC_CH_VALUE_MASK 0x3ffff 319 - #define LRADC_CH_VALUE_OFFSET 0 320 - 321 - #define LRADC_DELAY(n) (0xd0 + (0x10 * (n))) 322 - #define LRADC_DELAY_TRIGGER_LRADCS_MASK (0xffUL << 24) 323 - #define LRADC_DELAY_TRIGGER_LRADCS_OFFSET 24 324 - #define LRADC_DELAY_TRIGGER(x) \ 325 - (((x) << LRADC_DELAY_TRIGGER_LRADCS_OFFSET) & \ 326 - LRADC_DELAY_TRIGGER_LRADCS_MASK) 327 - #define LRADC_DELAY_KICK BIT(20) 328 - #define LRADC_DELAY_TRIGGER_DELAYS_MASK (0xf << 16) 329 - #define LRADC_DELAY_TRIGGER_DELAYS_OFFSET 16 330 - #define LRADC_DELAY_TRIGGER_DELAYS(x) \ 331 - (((x) << LRADC_DELAY_TRIGGER_DELAYS_OFFSET) & \ 332 - LRADC_DELAY_TRIGGER_DELAYS_MASK) 333 - #define LRADC_DELAY_LOOP_COUNT_MASK (0x1f << 11) 334 - #define LRADC_DELAY_LOOP_COUNT_OFFSET 11 335 - #define LRADC_DELAY_LOOP(x) \ 336 - (((x) << LRADC_DELAY_LOOP_COUNT_OFFSET) & \ 337 - LRADC_DELAY_LOOP_COUNT_MASK) 338 - #define LRADC_DELAY_DELAY_MASK 0x7ff 339 - #define LRADC_DELAY_DELAY_OFFSET 0 340 - #define LRADC_DELAY_DELAY(x) \ 341 - (((x) << LRADC_DELAY_DELAY_OFFSET) & \ 342 - LRADC_DELAY_DELAY_MASK) 343 - 344 - #define LRADC_CTRL4 0x140 345 - #define LRADC_CTRL4_LRADCSELECT_MASK(n) (0xf << ((n) * 4)) 346 - #define LRADC_CTRL4_LRADCSELECT_OFFSET(n) ((n) * 4) 347 - #define LRADC_CTRL4_LRADCSELECT(n, x) \ 348 - (((x) << LRADC_CTRL4_LRADCSELECT_OFFSET(n)) & \ 349 - LRADC_CTRL4_LRADCSELECT_MASK(n)) 350 - 351 - #define LRADC_RESOLUTION 12 352 - #define LRADC_SINGLE_SAMPLE_MASK ((1 << LRADC_RESOLUTION) - 1) 353 - 354 - static void mxs_lradc_reg_set(struct mxs_lradc *lradc, u32 val, u32 reg) 355 - { 356 - writel(val, lradc->base + reg + STMP_OFFSET_REG_SET); 357 - } 358 - 359 - static void mxs_lradc_reg_clear(struct mxs_lradc *lradc, u32 val, u32 reg) 360 - { 361 - writel(val, lradc->base + reg + STMP_OFFSET_REG_CLR); 362 - } 363 - 364 - static void mxs_lradc_reg_wrt(struct mxs_lradc *lradc, u32 val, u32 reg) 365 - { 366 - writel(val, lradc->base + reg); 367 - } 368 - 369 - static u32 mxs_lradc_plate_mask(struct mxs_lradc *lradc) 370 - { 371 - if (lradc->soc == IMX23_LRADC) 372 - return LRADC_CTRL0_MX23_PLATE_MASK; 373 - return LRADC_CTRL0_MX28_PLATE_MASK; 374 - } 375 - 376 - static u32 mxs_lradc_irq_mask(struct mxs_lradc *lradc) 377 - { 378 - if (lradc->soc == IMX23_LRADC) 379 - return LRADC_CTRL1_MX23_LRADC_IRQ_MASK; 380 - return LRADC_CTRL1_MX28_LRADC_IRQ_MASK; 381 - } 382 - 383 - static u32 mxs_lradc_touch_detect_bit(struct mxs_lradc *lradc) 384 - { 385 - if (lradc->soc == IMX23_LRADC) 386 - return LRADC_CTRL0_MX23_TOUCH_DETECT_ENABLE; 387 - return LRADC_CTRL0_MX28_TOUCH_DETECT_ENABLE; 388 - } 389 - 390 - static u32 mxs_lradc_drive_x_plate(struct mxs_lradc *lradc) 391 - { 392 - if (lradc->soc == IMX23_LRADC) 393 - return LRADC_CTRL0_MX23_XP | LRADC_CTRL0_MX23_XM; 394 - return LRADC_CTRL0_MX28_XPPSW | LRADC_CTRL0_MX28_XNNSW; 395 - } 396 - 397 - static u32 mxs_lradc_drive_y_plate(struct mxs_lradc *lradc) 398 - { 399 - if (lradc->soc == IMX23_LRADC) 400 - return LRADC_CTRL0_MX23_YP | LRADC_CTRL0_MX23_YM; 401 - return LRADC_CTRL0_MX28_YPPSW | LRADC_CTRL0_MX28_YNNSW; 402 - } 403 - 404 - static u32 mxs_lradc_drive_pressure(struct mxs_lradc *lradc) 405 - { 406 - if (lradc->soc == IMX23_LRADC) 407 - return LRADC_CTRL0_MX23_YP | LRADC_CTRL0_MX23_XM; 408 - return LRADC_CTRL0_MX28_YPPSW | LRADC_CTRL0_MX28_XNNSW; 409 - } 410 - 411 - static bool mxs_lradc_check_touch_event(struct mxs_lradc *lradc) 412 - { 413 - return !!(readl(lradc->base + LRADC_STATUS) & 414 - LRADC_STATUS_TOUCH_DETECT_RAW); 415 - } 416 - 417 - static void mxs_lradc_map_channel(struct mxs_lradc *lradc, unsigned vch, 418 - unsigned ch) 419 - { 420 - mxs_lradc_reg_clear(lradc, LRADC_CTRL4_LRADCSELECT_MASK(vch), 421 - LRADC_CTRL4); 422 - mxs_lradc_reg_set(lradc, LRADC_CTRL4_LRADCSELECT(vch, ch), LRADC_CTRL4); 423 - } 424 - 425 - static void mxs_lradc_setup_ts_channel(struct mxs_lradc *lradc, unsigned ch) 426 - { 427 - /* 428 - * prepare for oversampling conversion 429 - * 430 - * from the datasheet: 431 - * "The ACCUMULATE bit in the appropriate channel register 432 - * HW_LRADC_CHn must be set to 1 if NUM_SAMPLES is greater then 0; 433 - * otherwise, the IRQs will not fire." 434 - */ 435 - mxs_lradc_reg_wrt(lradc, LRADC_CH_ACCUMULATE | 436 - LRADC_CH_NUM_SAMPLES(lradc->over_sample_cnt - 1), 437 - LRADC_CH(ch)); 438 - 439 - /* 440 - * from the datasheet: 441 - * "Software must clear this register in preparation for a 442 - * multi-cycle accumulation. 443 - */ 444 - mxs_lradc_reg_clear(lradc, LRADC_CH_VALUE_MASK, LRADC_CH(ch)); 445 - 446 - /* 447 - * prepare the delay/loop unit according to the oversampling count 448 - * 449 - * from the datasheet: 450 - * "The DELAY fields in HW_LRADC_DELAY0, HW_LRADC_DELAY1, 451 - * HW_LRADC_DELAY2, and HW_LRADC_DELAY3 must be non-zero; otherwise, 452 - * the LRADC will not trigger the delay group." 453 - */ 454 - mxs_lradc_reg_wrt(lradc, LRADC_DELAY_TRIGGER(1 << ch) | 455 - LRADC_DELAY_TRIGGER_DELAYS(0) | 456 - LRADC_DELAY_LOOP(lradc->over_sample_cnt - 1) | 457 - LRADC_DELAY_DELAY(lradc->over_sample_delay - 1), 458 - LRADC_DELAY(3)); 459 - 460 - mxs_lradc_reg_clear(lradc, LRADC_CTRL1_LRADC_IRQ(ch), LRADC_CTRL1); 461 - 462 - /* 463 - * after changing the touchscreen plates setting 464 - * the signals need some initial time to settle. Start the 465 - * SoC's delay unit and start the conversion later 466 - * and automatically. 467 - */ 468 - mxs_lradc_reg_wrt( 469 - lradc, 470 - LRADC_DELAY_TRIGGER(0) | /* don't trigger ADC */ 471 - LRADC_DELAY_TRIGGER_DELAYS(BIT(3)) | /* trigger DELAY unit#3 */ 472 - LRADC_DELAY_KICK | 473 - LRADC_DELAY_DELAY(lradc->settling_delay), 474 - LRADC_DELAY(2)); 475 - } 476 - 477 - /* 478 - * Pressure detection is special: 479 - * We want to do both required measurements for the pressure detection in 480 - * one turn. Use the hardware features to chain both conversions and let the 481 - * hardware report one interrupt if both conversions are done 482 - */ 483 - static void mxs_lradc_setup_ts_pressure(struct mxs_lradc *lradc, unsigned ch1, 484 - unsigned ch2) 485 - { 486 - u32 reg; 487 - 488 - /* 489 - * prepare for oversampling conversion 490 - * 491 - * from the datasheet: 492 - * "The ACCUMULATE bit in the appropriate channel register 493 - * HW_LRADC_CHn must be set to 1 if NUM_SAMPLES is greater then 0; 494 - * otherwise, the IRQs will not fire." 495 - */ 496 - reg = LRADC_CH_ACCUMULATE | 497 - LRADC_CH_NUM_SAMPLES(lradc->over_sample_cnt - 1); 498 - mxs_lradc_reg_wrt(lradc, reg, LRADC_CH(ch1)); 499 - mxs_lradc_reg_wrt(lradc, reg, LRADC_CH(ch2)); 500 - 501 - /* 502 - * from the datasheet: 503 - * "Software must clear this register in preparation for a 504 - * multi-cycle accumulation. 505 - */ 506 - mxs_lradc_reg_clear(lradc, LRADC_CH_VALUE_MASK, LRADC_CH(ch1)); 507 - mxs_lradc_reg_clear(lradc, LRADC_CH_VALUE_MASK, LRADC_CH(ch2)); 508 - 509 - /* prepare the delay/loop unit according to the oversampling count */ 510 - mxs_lradc_reg_wrt( 511 - lradc, 512 - LRADC_DELAY_TRIGGER(1 << ch1) | 513 - LRADC_DELAY_TRIGGER(1 << ch2) | /* start both channels */ 514 - LRADC_DELAY_TRIGGER_DELAYS(0) | 515 - LRADC_DELAY_LOOP(lradc->over_sample_cnt - 1) | 516 - LRADC_DELAY_DELAY(lradc->over_sample_delay - 1), 517 - LRADC_DELAY(3)); 518 - 519 - mxs_lradc_reg_clear(lradc, LRADC_CTRL1_LRADC_IRQ(ch2), LRADC_CTRL1); 520 - 521 - /* 522 - * after changing the touchscreen plates setting 523 - * the signals need some initial time to settle. Start the 524 - * SoC's delay unit and start the conversion later 525 - * and automatically. 526 - */ 527 - mxs_lradc_reg_wrt( 528 - lradc, 529 - LRADC_DELAY_TRIGGER(0) | /* don't trigger ADC */ 530 - LRADC_DELAY_TRIGGER_DELAYS(BIT(3)) | /* trigger DELAY unit#3 */ 531 - LRADC_DELAY_KICK | 532 - LRADC_DELAY_DELAY(lradc->settling_delay), LRADC_DELAY(2)); 533 - } 534 - 535 - static unsigned mxs_lradc_read_raw_channel(struct mxs_lradc *lradc, 536 - unsigned channel) 537 - { 538 - u32 reg; 539 - unsigned num_samples, val; 540 - 541 - reg = readl(lradc->base + LRADC_CH(channel)); 542 - if (reg & LRADC_CH_ACCUMULATE) 543 - num_samples = lradc->over_sample_cnt; 544 - else 545 - num_samples = 1; 546 - 547 - val = (reg & LRADC_CH_VALUE_MASK) >> LRADC_CH_VALUE_OFFSET; 548 - return val / num_samples; 549 - } 550 - 551 - static unsigned mxs_lradc_read_ts_pressure(struct mxs_lradc *lradc, 552 - unsigned ch1, unsigned ch2) 553 - { 554 - u32 reg, mask; 555 - unsigned pressure, m1, m2; 556 - 557 - mask = LRADC_CTRL1_LRADC_IRQ(ch1) | LRADC_CTRL1_LRADC_IRQ(ch2); 558 - reg = readl(lradc->base + LRADC_CTRL1) & mask; 559 - 560 - while (reg != mask) { 561 - reg = readl(lradc->base + LRADC_CTRL1) & mask; 562 - dev_dbg(lradc->dev, "One channel is still busy: %X\n", reg); 563 - } 564 - 565 - m1 = mxs_lradc_read_raw_channel(lradc, ch1); 566 - m2 = mxs_lradc_read_raw_channel(lradc, ch2); 567 - 568 - if (m2 == 0) { 569 - dev_warn(lradc->dev, "Cannot calculate pressure\n"); 570 - return 1 << (LRADC_RESOLUTION - 1); 571 - } 572 - 573 - /* simply scale the value from 0 ... max ADC resolution */ 574 - pressure = m1; 575 - pressure *= (1 << LRADC_RESOLUTION); 576 - pressure /= m2; 577 - 578 - dev_dbg(lradc->dev, "Pressure = %u\n", pressure); 579 - return pressure; 580 - } 581 - 582 - #define TS_CH_XP 2 583 - #define TS_CH_YP 3 584 - #define TS_CH_XM 4 585 - #define TS_CH_YM 5 586 - 587 - /* 588 - * YP(open)--+-------------+ 589 - * | |--+ 590 - * | | | 591 - * YM(-)--+-------------+ | 592 - * +--------------+ 593 - * | | 594 - * XP(weak+) XM(open) 595 - * 596 - * "weak+" means 200k Ohm VDDIO 597 - * (-) means GND 598 - */ 599 - static void mxs_lradc_setup_touch_detection(struct mxs_lradc *lradc) 600 - { 601 - /* 602 - * In order to detect a touch event the 'touch detect enable' bit 603 - * enables: 604 - * - a weak pullup to the X+ connector 605 - * - a strong ground at the Y- connector 606 - */ 607 - mxs_lradc_reg_clear(lradc, mxs_lradc_plate_mask(lradc), LRADC_CTRL0); 608 - mxs_lradc_reg_set(lradc, mxs_lradc_touch_detect_bit(lradc), 609 - LRADC_CTRL0); 610 - } 611 - 612 - /* 613 - * YP(meas)--+-------------+ 614 - * | |--+ 615 - * | | | 616 - * YM(open)--+-------------+ | 617 - * +--------------+ 618 - * | | 619 - * XP(+) XM(-) 620 - * 621 - * (+) means here 1.85 V 622 - * (-) means here GND 623 - */ 624 - static void mxs_lradc_prepare_x_pos(struct mxs_lradc *lradc) 625 - { 626 - mxs_lradc_reg_clear(lradc, mxs_lradc_plate_mask(lradc), LRADC_CTRL0); 627 - mxs_lradc_reg_set(lradc, mxs_lradc_drive_x_plate(lradc), LRADC_CTRL0); 628 - 629 - lradc->cur_plate = LRADC_SAMPLE_X; 630 - mxs_lradc_map_channel(lradc, TOUCHSCREEN_VCHANNEL1, TS_CH_YP); 631 - mxs_lradc_setup_ts_channel(lradc, TOUCHSCREEN_VCHANNEL1); 632 - } 633 - 634 - /* 635 - * YP(+)--+-------------+ 636 - * | |--+ 637 - * | | | 638 - * YM(-)--+-------------+ | 639 - * +--------------+ 640 - * | | 641 - * XP(open) XM(meas) 642 - * 643 - * (+) means here 1.85 V 644 - * (-) means here GND 645 - */ 646 - static void mxs_lradc_prepare_y_pos(struct mxs_lradc *lradc) 647 - { 648 - mxs_lradc_reg_clear(lradc, mxs_lradc_plate_mask(lradc), LRADC_CTRL0); 649 - mxs_lradc_reg_set(lradc, mxs_lradc_drive_y_plate(lradc), LRADC_CTRL0); 650 - 651 - lradc->cur_plate = LRADC_SAMPLE_Y; 652 - mxs_lradc_map_channel(lradc, TOUCHSCREEN_VCHANNEL1, TS_CH_XM); 653 - mxs_lradc_setup_ts_channel(lradc, TOUCHSCREEN_VCHANNEL1); 654 - } 655 - 656 - /* 657 - * YP(+)--+-------------+ 658 - * | |--+ 659 - * | | | 660 - * YM(meas)--+-------------+ | 661 - * +--------------+ 662 - * | | 663 - * XP(meas) XM(-) 664 - * 665 - * (+) means here 1.85 V 666 - * (-) means here GND 667 - */ 668 - static void mxs_lradc_prepare_pressure(struct mxs_lradc *lradc) 669 - { 670 - mxs_lradc_reg_clear(lradc, mxs_lradc_plate_mask(lradc), LRADC_CTRL0); 671 - mxs_lradc_reg_set(lradc, mxs_lradc_drive_pressure(lradc), LRADC_CTRL0); 672 - 673 - lradc->cur_plate = LRADC_SAMPLE_PRESSURE; 674 - mxs_lradc_map_channel(lradc, TOUCHSCREEN_VCHANNEL1, TS_CH_YM); 675 - mxs_lradc_map_channel(lradc, TOUCHSCREEN_VCHANNEL2, TS_CH_XP); 676 - mxs_lradc_setup_ts_pressure(lradc, TOUCHSCREEN_VCHANNEL2, 677 - TOUCHSCREEN_VCHANNEL1); 678 - } 679 - 680 - static void mxs_lradc_enable_touch_detection(struct mxs_lradc *lradc) 681 - { 682 - /* Configure the touchscreen type */ 683 - if (lradc->soc == IMX28_LRADC) { 684 - mxs_lradc_reg_clear(lradc, LRADC_CTRL0_MX28_TOUCH_SCREEN_TYPE, 685 - LRADC_CTRL0); 686 - 687 - if (lradc->use_touchscreen == MXS_LRADC_TOUCHSCREEN_5WIRE) 688 - mxs_lradc_reg_set(lradc, 689 - LRADC_CTRL0_MX28_TOUCH_SCREEN_TYPE, 690 - LRADC_CTRL0); 691 - } 692 - 693 - mxs_lradc_setup_touch_detection(lradc); 694 - 695 - lradc->cur_plate = LRADC_TOUCH; 696 - mxs_lradc_reg_clear(lradc, LRADC_CTRL1_TOUCH_DETECT_IRQ | 697 - LRADC_CTRL1_TOUCH_DETECT_IRQ_EN, LRADC_CTRL1); 698 - mxs_lradc_reg_set(lradc, LRADC_CTRL1_TOUCH_DETECT_IRQ_EN, LRADC_CTRL1); 699 - } 700 - 701 - static void mxs_lradc_start_touch_event(struct mxs_lradc *lradc) 702 - { 703 - mxs_lradc_reg_clear(lradc, 704 - LRADC_CTRL1_TOUCH_DETECT_IRQ_EN, 705 - LRADC_CTRL1); 706 - mxs_lradc_reg_set(lradc, 707 - LRADC_CTRL1_LRADC_IRQ_EN(TOUCHSCREEN_VCHANNEL1), 708 - LRADC_CTRL1); 709 - /* 710 - * start with the Y-pos, because it uses nearly the same plate 711 - * settings like the touch detection 712 - */ 713 - mxs_lradc_prepare_y_pos(lradc); 714 - } 715 - 716 - static void mxs_lradc_report_ts_event(struct mxs_lradc *lradc) 717 - { 718 - input_report_abs(lradc->ts_input, ABS_X, lradc->ts_x_pos); 719 - input_report_abs(lradc->ts_input, ABS_Y, lradc->ts_y_pos); 720 - input_report_abs(lradc->ts_input, ABS_PRESSURE, lradc->ts_pressure); 721 - input_report_key(lradc->ts_input, BTN_TOUCH, 1); 722 - input_sync(lradc->ts_input); 723 - } 724 - 725 - static void mxs_lradc_complete_touch_event(struct mxs_lradc *lradc) 726 - { 727 - mxs_lradc_setup_touch_detection(lradc); 728 - lradc->cur_plate = LRADC_SAMPLE_VALID; 729 - /* 730 - * start a dummy conversion to burn time to settle the signals 731 - * note: we are not interested in the conversion's value 732 - */ 733 - mxs_lradc_reg_wrt(lradc, 0, LRADC_CH(TOUCHSCREEN_VCHANNEL1)); 734 - mxs_lradc_reg_clear(lradc, 735 - LRADC_CTRL1_LRADC_IRQ(TOUCHSCREEN_VCHANNEL1) | 736 - LRADC_CTRL1_LRADC_IRQ(TOUCHSCREEN_VCHANNEL2), 737 - LRADC_CTRL1); 738 - mxs_lradc_reg_wrt( 739 - lradc, 740 - LRADC_DELAY_TRIGGER(1 << TOUCHSCREEN_VCHANNEL1) | 741 - LRADC_DELAY_KICK | LRADC_DELAY_DELAY(10), /* waste 5 ms */ 742 - LRADC_DELAY(2)); 743 - } 744 - 745 - /* 746 - * in order to avoid false measurements, report only samples where 747 - * the surface is still touched after the position measurement 748 - */ 749 - static void mxs_lradc_finish_touch_event(struct mxs_lradc *lradc, bool valid) 750 - { 751 - /* if it is still touched, report the sample */ 752 - if (valid && mxs_lradc_check_touch_event(lradc)) { 753 - lradc->ts_valid = true; 754 - mxs_lradc_report_ts_event(lradc); 755 - } 756 - 757 - /* if it is even still touched, continue with the next measurement */ 758 - if (mxs_lradc_check_touch_event(lradc)) { 759 - mxs_lradc_prepare_y_pos(lradc); 760 - return; 761 - } 762 - 763 - if (lradc->ts_valid) { 764 - /* signal the release */ 765 - lradc->ts_valid = false; 766 - input_report_key(lradc->ts_input, BTN_TOUCH, 0); 767 - input_sync(lradc->ts_input); 768 - } 769 - 770 - /* if it is released, wait for the next touch via IRQ */ 771 - lradc->cur_plate = LRADC_TOUCH; 772 - mxs_lradc_reg_wrt(lradc, 0, LRADC_DELAY(2)); 773 - mxs_lradc_reg_wrt(lradc, 0, LRADC_DELAY(3)); 774 - mxs_lradc_reg_clear(lradc, 775 - LRADC_CTRL1_TOUCH_DETECT_IRQ | 776 - LRADC_CTRL1_LRADC_IRQ_EN(TOUCHSCREEN_VCHANNEL1) | 777 - LRADC_CTRL1_LRADC_IRQ(TOUCHSCREEN_VCHANNEL1), 778 - LRADC_CTRL1); 779 - mxs_lradc_reg_set(lradc, LRADC_CTRL1_TOUCH_DETECT_IRQ_EN, LRADC_CTRL1); 780 - } 781 - 782 - /* touchscreen's state machine */ 783 - static void mxs_lradc_handle_touch(struct mxs_lradc *lradc) 784 - { 785 - switch (lradc->cur_plate) { 786 - case LRADC_TOUCH: 787 - if (mxs_lradc_check_touch_event(lradc)) 788 - mxs_lradc_start_touch_event(lradc); 789 - mxs_lradc_reg_clear(lradc, LRADC_CTRL1_TOUCH_DETECT_IRQ, 790 - LRADC_CTRL1); 791 - return; 792 - 793 - case LRADC_SAMPLE_Y: 794 - lradc->ts_y_pos = 795 - mxs_lradc_read_raw_channel(lradc, 796 - TOUCHSCREEN_VCHANNEL1); 797 - mxs_lradc_prepare_x_pos(lradc); 798 - return; 799 - 800 - case LRADC_SAMPLE_X: 801 - lradc->ts_x_pos = 802 - mxs_lradc_read_raw_channel(lradc, 803 - TOUCHSCREEN_VCHANNEL1); 804 - mxs_lradc_prepare_pressure(lradc); 805 - return; 806 - 807 - case LRADC_SAMPLE_PRESSURE: 808 - lradc->ts_pressure = 809 - mxs_lradc_read_ts_pressure(lradc, 810 - TOUCHSCREEN_VCHANNEL2, 811 - TOUCHSCREEN_VCHANNEL1); 812 - mxs_lradc_complete_touch_event(lradc); 813 - return; 814 - 815 - case LRADC_SAMPLE_VALID: 816 - mxs_lradc_finish_touch_event(lradc, 1); 817 - break; 818 - } 819 - } 820 - 821 - /* 822 - * Raw I/O operations 823 - */ 824 - static int mxs_lradc_read_single(struct iio_dev *iio_dev, int chan, int *val) 825 - { 826 - struct mxs_lradc *lradc = iio_priv(iio_dev); 827 - int ret; 828 - 829 - /* 830 - * See if there is no buffered operation in progress. If there is, simply 831 - * bail out. This can be improved to support both buffered and raw IO at 832 - * the same time, yet the code becomes horribly complicated. Therefore I 833 - * applied KISS principle here. 834 - */ 835 - ret = mutex_trylock(&lradc->lock); 836 - if (!ret) 837 - return -EBUSY; 838 - 839 - reinit_completion(&lradc->completion); 840 - 841 - /* 842 - * No buffered operation in progress, map the channel and trigger it. 843 - * Virtual channel 0 is always used here as the others are always not 844 - * used if doing raw sampling. 845 - */ 846 - if (lradc->soc == IMX28_LRADC) 847 - mxs_lradc_reg_clear(lradc, LRADC_CTRL1_LRADC_IRQ_EN(0), 848 - LRADC_CTRL1); 849 - mxs_lradc_reg_clear(lradc, 0x1, LRADC_CTRL0); 850 - 851 - /* Enable / disable the divider per requirement */ 852 - if (test_bit(chan, &lradc->is_divided)) 853 - mxs_lradc_reg_set(lradc, 854 - 1 << LRADC_CTRL2_DIVIDE_BY_TWO_OFFSET, 855 - LRADC_CTRL2); 856 - else 857 - mxs_lradc_reg_clear(lradc, 858 - 1 << LRADC_CTRL2_DIVIDE_BY_TWO_OFFSET, 859 - LRADC_CTRL2); 860 - 861 - /* Clean the slot's previous content, then set new one. */ 862 - mxs_lradc_reg_clear(lradc, LRADC_CTRL4_LRADCSELECT_MASK(0), 863 - LRADC_CTRL4); 864 - mxs_lradc_reg_set(lradc, chan, LRADC_CTRL4); 865 - 866 - mxs_lradc_reg_wrt(lradc, 0, LRADC_CH(0)); 867 - 868 - /* Enable the IRQ and start sampling the channel. */ 869 - mxs_lradc_reg_set(lradc, LRADC_CTRL1_LRADC_IRQ_EN(0), LRADC_CTRL1); 870 - mxs_lradc_reg_set(lradc, BIT(0), LRADC_CTRL0); 871 - 872 - /* Wait for completion on the channel, 1 second max. */ 873 - ret = wait_for_completion_killable_timeout(&lradc->completion, HZ); 874 - if (!ret) 875 - ret = -ETIMEDOUT; 876 - if (ret < 0) 877 - goto err; 878 - 879 - /* Read the data. */ 880 - *val = readl(lradc->base + LRADC_CH(0)) & LRADC_CH_VALUE_MASK; 881 - ret = IIO_VAL_INT; 882 - 883 - err: 884 - mxs_lradc_reg_clear(lradc, LRADC_CTRL1_LRADC_IRQ_EN(0), LRADC_CTRL1); 885 - 886 - mutex_unlock(&lradc->lock); 887 - 888 - return ret; 889 - } 890 - 891 - static int mxs_lradc_read_temp(struct iio_dev *iio_dev, int *val) 892 - { 893 - int ret, min, max; 894 - 895 - ret = mxs_lradc_read_single(iio_dev, 8, &min); 896 - if (ret != IIO_VAL_INT) 897 - return ret; 898 - 899 - ret = mxs_lradc_read_single(iio_dev, 9, &max); 900 - if (ret != IIO_VAL_INT) 901 - return ret; 902 - 903 - *val = max - min; 904 - 905 - return IIO_VAL_INT; 906 - } 907 - 908 - static int mxs_lradc_read_raw(struct iio_dev *iio_dev, 909 - const struct iio_chan_spec *chan, 910 - int *val, int *val2, long m) 911 - { 912 - struct mxs_lradc *lradc = iio_priv(iio_dev); 913 - 914 - switch (m) { 915 - case IIO_CHAN_INFO_RAW: 916 - if (chan->type == IIO_TEMP) 917 - return mxs_lradc_read_temp(iio_dev, val); 918 - 919 - return mxs_lradc_read_single(iio_dev, chan->channel, val); 920 - 921 - case IIO_CHAN_INFO_SCALE: 922 - if (chan->type == IIO_TEMP) { 923 - /* 924 - * From the datasheet, we have to multiply by 1.012 and 925 - * divide by 4 926 - */ 927 - *val = 0; 928 - *val2 = 253000; 929 - return IIO_VAL_INT_PLUS_MICRO; 930 - } 931 - 932 - *val = lradc->vref_mv[chan->channel]; 933 - *val2 = chan->scan_type.realbits - 934 - test_bit(chan->channel, &lradc->is_divided); 935 - return IIO_VAL_FRACTIONAL_LOG2; 936 - 937 - case IIO_CHAN_INFO_OFFSET: 938 - if (chan->type == IIO_TEMP) { 939 - /* 940 - * The calculated value from the ADC is in Kelvin, we 941 - * want Celsius for hwmon so the offset is -273.15 942 - * The offset is applied before scaling so it is 943 - * actually -213.15 * 4 / 1.012 = -1079.644268 944 - */ 945 - *val = -1079; 946 - *val2 = 644268; 947 - 948 - return IIO_VAL_INT_PLUS_MICRO; 949 - } 950 - 951 - return -EINVAL; 952 - 953 - default: 954 - break; 955 - } 956 - 957 - return -EINVAL; 958 - } 959 - 960 - static int mxs_lradc_write_raw(struct iio_dev *iio_dev, 961 - const struct iio_chan_spec *chan, 962 - int val, int val2, long m) 963 - { 964 - struct mxs_lradc *lradc = iio_priv(iio_dev); 965 - struct mxs_lradc_scale *scale_avail = 966 - lradc->scale_avail[chan->channel]; 967 - int ret; 968 - 969 - ret = mutex_trylock(&lradc->lock); 970 - if (!ret) 971 - return -EBUSY; 972 - 973 - switch (m) { 974 - case IIO_CHAN_INFO_SCALE: 975 - ret = -EINVAL; 976 - if (val == scale_avail[MXS_LRADC_DIV_DISABLED].integer && 977 - val2 == scale_avail[MXS_LRADC_DIV_DISABLED].nano) { 978 - /* divider by two disabled */ 979 - clear_bit(chan->channel, &lradc->is_divided); 980 - ret = 0; 981 - } else if (val == scale_avail[MXS_LRADC_DIV_ENABLED].integer && 982 - val2 == scale_avail[MXS_LRADC_DIV_ENABLED].nano) { 983 - /* divider by two enabled */ 984 - set_bit(chan->channel, &lradc->is_divided); 985 - ret = 0; 986 - } 987 - 988 - break; 989 - default: 990 - ret = -EINVAL; 991 - break; 992 - } 993 - 994 - mutex_unlock(&lradc->lock); 995 - 996 - return ret; 997 - } 998 - 999 - static int mxs_lradc_write_raw_get_fmt(struct iio_dev *iio_dev, 1000 - const struct iio_chan_spec *chan, 1001 - long m) 1002 - { 1003 - return IIO_VAL_INT_PLUS_NANO; 1004 - } 1005 - 1006 - static ssize_t mxs_lradc_show_scale_available_ch(struct device *dev, 1007 - struct device_attribute *attr, 1008 - char *buf, 1009 - int ch) 1010 - { 1011 - struct iio_dev *iio = dev_to_iio_dev(dev); 1012 - struct mxs_lradc *lradc = iio_priv(iio); 1013 - int i, len = 0; 1014 - 1015 - for (i = 0; i < ARRAY_SIZE(lradc->scale_avail[ch]); i++) 1016 - len += sprintf(buf + len, "%u.%09u ", 1017 - lradc->scale_avail[ch][i].integer, 1018 - lradc->scale_avail[ch][i].nano); 1019 - 1020 - len += sprintf(buf + len, "\n"); 1021 - 1022 - return len; 1023 - } 1024 - 1025 - static ssize_t mxs_lradc_show_scale_available(struct device *dev, 1026 - struct device_attribute *attr, 1027 - char *buf) 1028 - { 1029 - struct iio_dev_attr *iio_attr = to_iio_dev_attr(attr); 1030 - 1031 - return mxs_lradc_show_scale_available_ch(dev, attr, buf, 1032 - iio_attr->address); 1033 - } 1034 - 1035 - #define SHOW_SCALE_AVAILABLE_ATTR(ch) \ 1036 - static IIO_DEVICE_ATTR(in_voltage##ch##_scale_available, S_IRUGO, \ 1037 - mxs_lradc_show_scale_available, NULL, ch) 1038 - 1039 - SHOW_SCALE_AVAILABLE_ATTR(0); 1040 - SHOW_SCALE_AVAILABLE_ATTR(1); 1041 - SHOW_SCALE_AVAILABLE_ATTR(2); 1042 - SHOW_SCALE_AVAILABLE_ATTR(3); 1043 - SHOW_SCALE_AVAILABLE_ATTR(4); 1044 - SHOW_SCALE_AVAILABLE_ATTR(5); 1045 - SHOW_SCALE_AVAILABLE_ATTR(6); 1046 - SHOW_SCALE_AVAILABLE_ATTR(7); 1047 - SHOW_SCALE_AVAILABLE_ATTR(10); 1048 - SHOW_SCALE_AVAILABLE_ATTR(11); 1049 - SHOW_SCALE_AVAILABLE_ATTR(12); 1050 - SHOW_SCALE_AVAILABLE_ATTR(13); 1051 - SHOW_SCALE_AVAILABLE_ATTR(14); 1052 - SHOW_SCALE_AVAILABLE_ATTR(15); 1053 - 1054 - static struct attribute *mxs_lradc_attributes[] = { 1055 - &iio_dev_attr_in_voltage0_scale_available.dev_attr.attr, 1056 - &iio_dev_attr_in_voltage1_scale_available.dev_attr.attr, 1057 - &iio_dev_attr_in_voltage2_scale_available.dev_attr.attr, 1058 - &iio_dev_attr_in_voltage3_scale_available.dev_attr.attr, 1059 - &iio_dev_attr_in_voltage4_scale_available.dev_attr.attr, 1060 - &iio_dev_attr_in_voltage5_scale_available.dev_attr.attr, 1061 - &iio_dev_attr_in_voltage6_scale_available.dev_attr.attr, 1062 - &iio_dev_attr_in_voltage7_scale_available.dev_attr.attr, 1063 - &iio_dev_attr_in_voltage10_scale_available.dev_attr.attr, 1064 - &iio_dev_attr_in_voltage11_scale_available.dev_attr.attr, 1065 - &iio_dev_attr_in_voltage12_scale_available.dev_attr.attr, 1066 - &iio_dev_attr_in_voltage13_scale_available.dev_attr.attr, 1067 - &iio_dev_attr_in_voltage14_scale_available.dev_attr.attr, 1068 - &iio_dev_attr_in_voltage15_scale_available.dev_attr.attr, 1069 - NULL 1070 - }; 1071 - 1072 - static const struct attribute_group mxs_lradc_attribute_group = { 1073 - .attrs = mxs_lradc_attributes, 1074 - }; 1075 - 1076 - static const struct iio_info mxs_lradc_iio_info = { 1077 - .driver_module = THIS_MODULE, 1078 - .read_raw = mxs_lradc_read_raw, 1079 - .write_raw = mxs_lradc_write_raw, 1080 - .write_raw_get_fmt = mxs_lradc_write_raw_get_fmt, 1081 - .attrs = &mxs_lradc_attribute_group, 1082 - }; 1083 - 1084 - static int mxs_lradc_ts_open(struct input_dev *dev) 1085 - { 1086 - struct mxs_lradc *lradc = input_get_drvdata(dev); 1087 - 1088 - /* Enable the touch-detect circuitry. */ 1089 - mxs_lradc_enable_touch_detection(lradc); 1090 - 1091 - return 0; 1092 - } 1093 - 1094 - static void mxs_lradc_disable_ts(struct mxs_lradc *lradc) 1095 - { 1096 - /* stop all interrupts from firing */ 1097 - mxs_lradc_reg_clear(lradc, LRADC_CTRL1_TOUCH_DETECT_IRQ_EN | 1098 - LRADC_CTRL1_LRADC_IRQ_EN(TOUCHSCREEN_VCHANNEL1) | 1099 - LRADC_CTRL1_LRADC_IRQ_EN(TOUCHSCREEN_VCHANNEL2), LRADC_CTRL1); 1100 - 1101 - /* Power-down touchscreen touch-detect circuitry. */ 1102 - mxs_lradc_reg_clear(lradc, mxs_lradc_plate_mask(lradc), LRADC_CTRL0); 1103 - } 1104 - 1105 - static void mxs_lradc_ts_close(struct input_dev *dev) 1106 - { 1107 - struct mxs_lradc *lradc = input_get_drvdata(dev); 1108 - 1109 - mxs_lradc_disable_ts(lradc); 1110 - } 1111 - 1112 - static int mxs_lradc_ts_register(struct mxs_lradc *lradc) 1113 - { 1114 - struct input_dev *input; 1115 - struct device *dev = lradc->dev; 1116 - 1117 - if (!lradc->use_touchscreen) 1118 - return 0; 1119 - 1120 - input = devm_input_allocate_device(dev); 1121 - if (!input) 1122 - return -ENOMEM; 1123 - 1124 - input->name = DRIVER_NAME; 1125 - input->id.bustype = BUS_HOST; 1126 - input->open = mxs_lradc_ts_open; 1127 - input->close = mxs_lradc_ts_close; 1128 - 1129 - __set_bit(EV_ABS, input->evbit); 1130 - __set_bit(EV_KEY, input->evbit); 1131 - __set_bit(BTN_TOUCH, input->keybit); 1132 - __set_bit(INPUT_PROP_DIRECT, input->propbit); 1133 - input_set_abs_params(input, ABS_X, 0, LRADC_SINGLE_SAMPLE_MASK, 0, 0); 1134 - input_set_abs_params(input, ABS_Y, 0, LRADC_SINGLE_SAMPLE_MASK, 0, 0); 1135 - input_set_abs_params(input, ABS_PRESSURE, 0, LRADC_SINGLE_SAMPLE_MASK, 1136 - 0, 0); 1137 - 1138 - lradc->ts_input = input; 1139 - input_set_drvdata(input, lradc); 1140 - 1141 - return input_register_device(input); 1142 - } 1143 - 1144 - /* 1145 - * IRQ Handling 1146 - */ 1147 - static irqreturn_t mxs_lradc_handle_irq(int irq, void *data) 1148 - { 1149 - struct iio_dev *iio = data; 1150 - struct mxs_lradc *lradc = iio_priv(iio); 1151 - unsigned long reg = readl(lradc->base + LRADC_CTRL1); 1152 - u32 clr_irq = mxs_lradc_irq_mask(lradc); 1153 - const u32 ts_irq_mask = 1154 - LRADC_CTRL1_TOUCH_DETECT_IRQ | 1155 - LRADC_CTRL1_LRADC_IRQ(TOUCHSCREEN_VCHANNEL1) | 1156 - LRADC_CTRL1_LRADC_IRQ(TOUCHSCREEN_VCHANNEL2); 1157 - 1158 - if (!(reg & mxs_lradc_irq_mask(lradc))) 1159 - return IRQ_NONE; 1160 - 1161 - if (lradc->use_touchscreen && (reg & ts_irq_mask)) { 1162 - mxs_lradc_handle_touch(lradc); 1163 - 1164 - /* Make sure we don't clear the next conversion's interrupt. */ 1165 - clr_irq &= ~(LRADC_CTRL1_LRADC_IRQ(TOUCHSCREEN_VCHANNEL1) | 1166 - LRADC_CTRL1_LRADC_IRQ(TOUCHSCREEN_VCHANNEL2)); 1167 - } 1168 - 1169 - if (iio_buffer_enabled(iio)) { 1170 - if (reg & lradc->buffer_vchans) 1171 - iio_trigger_poll(iio->trig); 1172 - } else if (reg & LRADC_CTRL1_LRADC_IRQ(0)) { 1173 - complete(&lradc->completion); 1174 - } 1175 - 1176 - mxs_lradc_reg_clear(lradc, reg & clr_irq, LRADC_CTRL1); 1177 - 1178 - return IRQ_HANDLED; 1179 - } 1180 - 1181 - /* 1182 - * Trigger handling 1183 - */ 1184 - static irqreturn_t mxs_lradc_trigger_handler(int irq, void *p) 1185 - { 1186 - struct iio_poll_func *pf = p; 1187 - struct iio_dev *iio = pf->indio_dev; 1188 - struct mxs_lradc *lradc = iio_priv(iio); 1189 - const u32 chan_value = LRADC_CH_ACCUMULATE | 1190 - ((LRADC_DELAY_TIMER_LOOP - 1) << LRADC_CH_NUM_SAMPLES_OFFSET); 1191 - unsigned int i, j = 0; 1192 - 1193 - for_each_set_bit(i, iio->active_scan_mask, LRADC_MAX_TOTAL_CHANS) { 1194 - lradc->buffer[j] = readl(lradc->base + LRADC_CH(j)); 1195 - mxs_lradc_reg_wrt(lradc, chan_value, LRADC_CH(j)); 1196 - lradc->buffer[j] &= LRADC_CH_VALUE_MASK; 1197 - lradc->buffer[j] /= LRADC_DELAY_TIMER_LOOP; 1198 - j++; 1199 - } 1200 - 1201 - iio_push_to_buffers_with_timestamp(iio, lradc->buffer, pf->timestamp); 1202 - 1203 - iio_trigger_notify_done(iio->trig); 1204 - 1205 - return IRQ_HANDLED; 1206 - } 1207 - 1208 - static int mxs_lradc_configure_trigger(struct iio_trigger *trig, bool state) 1209 - { 1210 - struct iio_dev *iio = iio_trigger_get_drvdata(trig); 1211 - struct mxs_lradc *lradc = iio_priv(iio); 1212 - const u32 st = state ? STMP_OFFSET_REG_SET : STMP_OFFSET_REG_CLR; 1213 - 1214 - mxs_lradc_reg_wrt(lradc, LRADC_DELAY_KICK, LRADC_DELAY(0) + st); 1215 - 1216 - return 0; 1217 - } 1218 - 1219 - static const struct iio_trigger_ops mxs_lradc_trigger_ops = { 1220 - .owner = THIS_MODULE, 1221 - .set_trigger_state = &mxs_lradc_configure_trigger, 1222 - }; 1223 - 1224 - static int mxs_lradc_trigger_init(struct iio_dev *iio) 1225 - { 1226 - int ret; 1227 - struct iio_trigger *trig; 1228 - struct mxs_lradc *lradc = iio_priv(iio); 1229 - 1230 - trig = iio_trigger_alloc("%s-dev%i", iio->name, iio->id); 1231 - if (!trig) 1232 - return -ENOMEM; 1233 - 1234 - trig->dev.parent = lradc->dev; 1235 - iio_trigger_set_drvdata(trig, iio); 1236 - trig->ops = &mxs_lradc_trigger_ops; 1237 - 1238 - ret = iio_trigger_register(trig); 1239 - if (ret) { 1240 - iio_trigger_free(trig); 1241 - return ret; 1242 - } 1243 - 1244 - lradc->trig = trig; 1245 - 1246 - return 0; 1247 - } 1248 - 1249 - static void mxs_lradc_trigger_remove(struct iio_dev *iio) 1250 - { 1251 - struct mxs_lradc *lradc = iio_priv(iio); 1252 - 1253 - iio_trigger_unregister(lradc->trig); 1254 - iio_trigger_free(lradc->trig); 1255 - } 1256 - 1257 - static int mxs_lradc_buffer_preenable(struct iio_dev *iio) 1258 - { 1259 - struct mxs_lradc *lradc = iio_priv(iio); 1260 - int ret = 0, chan, ofs = 0; 1261 - unsigned long enable = 0; 1262 - u32 ctrl4_set = 0; 1263 - u32 ctrl4_clr = 0; 1264 - u32 ctrl1_irq = 0; 1265 - const u32 chan_value = LRADC_CH_ACCUMULATE | 1266 - ((LRADC_DELAY_TIMER_LOOP - 1) << LRADC_CH_NUM_SAMPLES_OFFSET); 1267 - const int len = bitmap_weight(iio->active_scan_mask, 1268 - LRADC_MAX_TOTAL_CHANS); 1269 - 1270 - if (!len) 1271 - return -EINVAL; 1272 - 1273 - /* 1274 - * Lock the driver so raw access can not be done during buffered 1275 - * operation. This simplifies the code a lot. 1276 - */ 1277 - ret = mutex_trylock(&lradc->lock); 1278 - if (!ret) 1279 - return -EBUSY; 1280 - 1281 - lradc->buffer = kmalloc_array(len, sizeof(*lradc->buffer), GFP_KERNEL); 1282 - if (!lradc->buffer) { 1283 - ret = -ENOMEM; 1284 - goto err_mem; 1285 - } 1286 - 1287 - if (lradc->soc == IMX28_LRADC) 1288 - mxs_lradc_reg_clear( 1289 - lradc, 1290 - lradc->buffer_vchans << LRADC_CTRL1_LRADC_IRQ_EN_OFFSET, 1291 - LRADC_CTRL1); 1292 - mxs_lradc_reg_clear(lradc, lradc->buffer_vchans, LRADC_CTRL0); 1293 - 1294 - for_each_set_bit(chan, iio->active_scan_mask, LRADC_MAX_TOTAL_CHANS) { 1295 - ctrl4_set |= chan << LRADC_CTRL4_LRADCSELECT_OFFSET(ofs); 1296 - ctrl4_clr |= LRADC_CTRL4_LRADCSELECT_MASK(ofs); 1297 - ctrl1_irq |= LRADC_CTRL1_LRADC_IRQ_EN(ofs); 1298 - mxs_lradc_reg_wrt(lradc, chan_value, LRADC_CH(ofs)); 1299 - bitmap_set(&enable, ofs, 1); 1300 - ofs++; 1301 - } 1302 - 1303 - mxs_lradc_reg_clear(lradc, LRADC_DELAY_TRIGGER_LRADCS_MASK | 1304 - LRADC_DELAY_KICK, LRADC_DELAY(0)); 1305 - mxs_lradc_reg_clear(lradc, ctrl4_clr, LRADC_CTRL4); 1306 - mxs_lradc_reg_set(lradc, ctrl4_set, LRADC_CTRL4); 1307 - mxs_lradc_reg_set(lradc, ctrl1_irq, LRADC_CTRL1); 1308 - mxs_lradc_reg_set(lradc, enable << LRADC_DELAY_TRIGGER_LRADCS_OFFSET, 1309 - LRADC_DELAY(0)); 1310 - 1311 - return 0; 1312 - 1313 - err_mem: 1314 - mutex_unlock(&lradc->lock); 1315 - return ret; 1316 - } 1317 - 1318 - static int mxs_lradc_buffer_postdisable(struct iio_dev *iio) 1319 - { 1320 - struct mxs_lradc *lradc = iio_priv(iio); 1321 - 1322 - mxs_lradc_reg_clear(lradc, LRADC_DELAY_TRIGGER_LRADCS_MASK | 1323 - LRADC_DELAY_KICK, LRADC_DELAY(0)); 1324 - 1325 - mxs_lradc_reg_clear(lradc, lradc->buffer_vchans, LRADC_CTRL0); 1326 - if (lradc->soc == IMX28_LRADC) 1327 - mxs_lradc_reg_clear( 1328 - lradc, 1329 - lradc->buffer_vchans << LRADC_CTRL1_LRADC_IRQ_EN_OFFSET, 1330 - LRADC_CTRL1); 1331 - 1332 - kfree(lradc->buffer); 1333 - mutex_unlock(&lradc->lock); 1334 - 1335 - return 0; 1336 - } 1337 - 1338 - static bool mxs_lradc_validate_scan_mask(struct iio_dev *iio, 1339 - const unsigned long *mask) 1340 - { 1341 - struct mxs_lradc *lradc = iio_priv(iio); 1342 - const int map_chans = bitmap_weight(mask, LRADC_MAX_TOTAL_CHANS); 1343 - int rsvd_chans = 0; 1344 - unsigned long rsvd_mask = 0; 1345 - 1346 - if (lradc->use_touchbutton) 1347 - rsvd_mask |= CHAN_MASK_TOUCHBUTTON; 1348 - if (lradc->use_touchscreen == MXS_LRADC_TOUCHSCREEN_4WIRE) 1349 - rsvd_mask |= CHAN_MASK_TOUCHSCREEN_4WIRE; 1350 - if (lradc->use_touchscreen == MXS_LRADC_TOUCHSCREEN_5WIRE) 1351 - rsvd_mask |= CHAN_MASK_TOUCHSCREEN_5WIRE; 1352 - 1353 - if (lradc->use_touchbutton) 1354 - rsvd_chans++; 1355 - if (lradc->use_touchscreen) 1356 - rsvd_chans += 2; 1357 - 1358 - /* Test for attempts to map channels with special mode of operation. */ 1359 - if (bitmap_intersects(mask, &rsvd_mask, LRADC_MAX_TOTAL_CHANS)) 1360 - return false; 1361 - 1362 - /* Test for attempts to map more channels then available slots. */ 1363 - if (map_chans + rsvd_chans > LRADC_MAX_MAPPED_CHANS) 1364 - return false; 1365 - 1366 - return true; 1367 - } 1368 - 1369 - static const struct iio_buffer_setup_ops mxs_lradc_buffer_ops = { 1370 - .preenable = &mxs_lradc_buffer_preenable, 1371 - .postenable = &iio_triggered_buffer_postenable, 1372 - .predisable = &iio_triggered_buffer_predisable, 1373 - .postdisable = &mxs_lradc_buffer_postdisable, 1374 - .validate_scan_mask = &mxs_lradc_validate_scan_mask, 1375 - }; 1376 - 1377 - /* 1378 - * Driver initialization 1379 - */ 1380 - 1381 - #define MXS_ADC_CHAN(idx, chan_type, name) { \ 1382 - .type = (chan_type), \ 1383 - .indexed = 1, \ 1384 - .scan_index = (idx), \ 1385 - .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ 1386 - BIT(IIO_CHAN_INFO_SCALE), \ 1387 - .channel = (idx), \ 1388 - .address = (idx), \ 1389 - .scan_type = { \ 1390 - .sign = 'u', \ 1391 - .realbits = LRADC_RESOLUTION, \ 1392 - .storagebits = 32, \ 1393 - }, \ 1394 - .datasheet_name = (name), \ 1395 - } 1396 - 1397 - static const struct iio_chan_spec mx23_lradc_chan_spec[] = { 1398 - MXS_ADC_CHAN(0, IIO_VOLTAGE, "LRADC0"), 1399 - MXS_ADC_CHAN(1, IIO_VOLTAGE, "LRADC1"), 1400 - MXS_ADC_CHAN(2, IIO_VOLTAGE, "LRADC2"), 1401 - MXS_ADC_CHAN(3, IIO_VOLTAGE, "LRADC3"), 1402 - MXS_ADC_CHAN(4, IIO_VOLTAGE, "LRADC4"), 1403 - MXS_ADC_CHAN(5, IIO_VOLTAGE, "LRADC5"), 1404 - MXS_ADC_CHAN(6, IIO_VOLTAGE, "VDDIO"), 1405 - MXS_ADC_CHAN(7, IIO_VOLTAGE, "VBATT"), 1406 - /* Combined Temperature sensors */ 1407 - { 1408 - .type = IIO_TEMP, 1409 - .indexed = 1, 1410 - .scan_index = 8, 1411 - .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | 1412 - BIT(IIO_CHAN_INFO_OFFSET) | 1413 - BIT(IIO_CHAN_INFO_SCALE), 1414 - .channel = 8, 1415 - .scan_type = {.sign = 'u', .realbits = 18, .storagebits = 32,}, 1416 - .datasheet_name = "TEMP_DIE", 1417 - }, 1418 - /* Hidden channel to keep indexes */ 1419 - { 1420 - .type = IIO_TEMP, 1421 - .indexed = 1, 1422 - .scan_index = -1, 1423 - .channel = 9, 1424 - }, 1425 - MXS_ADC_CHAN(10, IIO_VOLTAGE, NULL), 1426 - MXS_ADC_CHAN(11, IIO_VOLTAGE, NULL), 1427 - MXS_ADC_CHAN(12, IIO_VOLTAGE, "USB_DP"), 1428 - MXS_ADC_CHAN(13, IIO_VOLTAGE, "USB_DN"), 1429 - MXS_ADC_CHAN(14, IIO_VOLTAGE, "VBG"), 1430 - MXS_ADC_CHAN(15, IIO_VOLTAGE, "VDD5V"), 1431 - }; 1432 - 1433 - static const struct iio_chan_spec mx28_lradc_chan_spec[] = { 1434 - MXS_ADC_CHAN(0, IIO_VOLTAGE, "LRADC0"), 1435 - MXS_ADC_CHAN(1, IIO_VOLTAGE, "LRADC1"), 1436 - MXS_ADC_CHAN(2, IIO_VOLTAGE, "LRADC2"), 1437 - MXS_ADC_CHAN(3, IIO_VOLTAGE, "LRADC3"), 1438 - MXS_ADC_CHAN(4, IIO_VOLTAGE, "LRADC4"), 1439 - MXS_ADC_CHAN(5, IIO_VOLTAGE, "LRADC5"), 1440 - MXS_ADC_CHAN(6, IIO_VOLTAGE, "LRADC6"), 1441 - MXS_ADC_CHAN(7, IIO_VOLTAGE, "VBATT"), 1442 - /* Combined Temperature sensors */ 1443 - { 1444 - .type = IIO_TEMP, 1445 - .indexed = 1, 1446 - .scan_index = 8, 1447 - .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | 1448 - BIT(IIO_CHAN_INFO_OFFSET) | 1449 - BIT(IIO_CHAN_INFO_SCALE), 1450 - .channel = 8, 1451 - .scan_type = {.sign = 'u', .realbits = 18, .storagebits = 32,}, 1452 - .datasheet_name = "TEMP_DIE", 1453 - }, 1454 - /* Hidden channel to keep indexes */ 1455 - { 1456 - .type = IIO_TEMP, 1457 - .indexed = 1, 1458 - .scan_index = -1, 1459 - .channel = 9, 1460 - }, 1461 - MXS_ADC_CHAN(10, IIO_VOLTAGE, "VDDIO"), 1462 - MXS_ADC_CHAN(11, IIO_VOLTAGE, "VTH"), 1463 - MXS_ADC_CHAN(12, IIO_VOLTAGE, "VDDA"), 1464 - MXS_ADC_CHAN(13, IIO_VOLTAGE, "VDDD"), 1465 - MXS_ADC_CHAN(14, IIO_VOLTAGE, "VBG"), 1466 - MXS_ADC_CHAN(15, IIO_VOLTAGE, "VDD5V"), 1467 - }; 1468 - 1469 - static void mxs_lradc_hw_init(struct mxs_lradc *lradc) 1470 - { 1471 - /* The ADC always uses DELAY CHANNEL 0. */ 1472 - const u32 adc_cfg = 1473 - (1 << (LRADC_DELAY_TRIGGER_DELAYS_OFFSET + 0)) | 1474 - (LRADC_DELAY_TIMER_PER << LRADC_DELAY_DELAY_OFFSET); 1475 - 1476 - /* Configure DELAY CHANNEL 0 for generic ADC sampling. */ 1477 - mxs_lradc_reg_wrt(lradc, adc_cfg, LRADC_DELAY(0)); 1478 - 1479 - /* Disable remaining DELAY CHANNELs */ 1480 - mxs_lradc_reg_wrt(lradc, 0, LRADC_DELAY(1)); 1481 - mxs_lradc_reg_wrt(lradc, 0, LRADC_DELAY(2)); 1482 - mxs_lradc_reg_wrt(lradc, 0, LRADC_DELAY(3)); 1483 - 1484 - /* Start internal temperature sensing. */ 1485 - mxs_lradc_reg_wrt(lradc, 0, LRADC_CTRL2); 1486 - } 1487 - 1488 - static void mxs_lradc_hw_stop(struct mxs_lradc *lradc) 1489 - { 1490 - int i; 1491 - 1492 - mxs_lradc_reg_clear(lradc, 1493 - lradc->buffer_vchans << LRADC_CTRL1_LRADC_IRQ_EN_OFFSET, 1494 - LRADC_CTRL1); 1495 - 1496 - for (i = 0; i < LRADC_MAX_DELAY_CHANS; i++) 1497 - mxs_lradc_reg_wrt(lradc, 0, LRADC_DELAY(i)); 1498 - } 1499 - 1500 - static const struct of_device_id mxs_lradc_dt_ids[] = { 1501 - { .compatible = "fsl,imx23-lradc", .data = (void *)IMX23_LRADC, }, 1502 - { .compatible = "fsl,imx28-lradc", .data = (void *)IMX28_LRADC, }, 1503 - { /* sentinel */ } 1504 - }; 1505 - MODULE_DEVICE_TABLE(of, mxs_lradc_dt_ids); 1506 - 1507 - static int mxs_lradc_probe_touchscreen(struct mxs_lradc *lradc, 1508 - struct device_node *lradc_node) 1509 - { 1510 - int ret; 1511 - u32 ts_wires = 0, adapt; 1512 - 1513 - ret = of_property_read_u32(lradc_node, "fsl,lradc-touchscreen-wires", 1514 - &ts_wires); 1515 - if (ret) 1516 - return -ENODEV; /* touchscreen feature disabled */ 1517 - 1518 - switch (ts_wires) { 1519 - case 4: 1520 - lradc->use_touchscreen = MXS_LRADC_TOUCHSCREEN_4WIRE; 1521 - break; 1522 - case 5: 1523 - if (lradc->soc == IMX28_LRADC) { 1524 - lradc->use_touchscreen = MXS_LRADC_TOUCHSCREEN_5WIRE; 1525 - break; 1526 - } 1527 - /* fall through an error message for i.MX23 */ 1528 - default: 1529 - dev_err(lradc->dev, 1530 - "Unsupported number of touchscreen wires (%d)\n", 1531 - ts_wires); 1532 - return -EINVAL; 1533 - } 1534 - 1535 - if (of_property_read_u32(lradc_node, "fsl,ave-ctrl", &adapt)) { 1536 - lradc->over_sample_cnt = 4; 1537 - } else { 1538 - if (adapt < 1 || adapt > 32) { 1539 - dev_err(lradc->dev, "Invalid sample count (%u)\n", 1540 - adapt); 1541 - return -EINVAL; 1542 - } 1543 - lradc->over_sample_cnt = adapt; 1544 - } 1545 - 1546 - if (of_property_read_u32(lradc_node, "fsl,ave-delay", &adapt)) { 1547 - lradc->over_sample_delay = 2; 1548 - } else { 1549 - if (adapt < 2 || adapt > LRADC_DELAY_DELAY_MASK + 1) { 1550 - dev_err(lradc->dev, "Invalid sample delay (%u)\n", 1551 - adapt); 1552 - return -EINVAL; 1553 - } 1554 - lradc->over_sample_delay = adapt; 1555 - } 1556 - 1557 - if (of_property_read_u32(lradc_node, "fsl,settling", &adapt)) { 1558 - lradc->settling_delay = 10; 1559 - } else { 1560 - if (adapt < 1 || adapt > LRADC_DELAY_DELAY_MASK) { 1561 - dev_err(lradc->dev, "Invalid settling delay (%u)\n", 1562 - adapt); 1563 - return -EINVAL; 1564 - } 1565 - lradc->settling_delay = adapt; 1566 - } 1567 - 1568 - return 0; 1569 - } 1570 - 1571 - static int mxs_lradc_probe(struct platform_device *pdev) 1572 - { 1573 - const struct of_device_id *of_id = 1574 - of_match_device(mxs_lradc_dt_ids, &pdev->dev); 1575 - const struct mxs_lradc_of_config *of_cfg = 1576 - &mxs_lradc_of_config[(enum mxs_lradc_id)of_id->data]; 1577 - struct device *dev = &pdev->dev; 1578 - struct device_node *node = dev->of_node; 1579 - struct mxs_lradc *lradc; 1580 - struct iio_dev *iio; 1581 - struct resource *iores; 1582 - int ret = 0, touch_ret; 1583 - int i, s; 1584 - u64 scale_uv; 1585 - 1586 - /* Allocate the IIO device. */ 1587 - iio = devm_iio_device_alloc(dev, sizeof(*lradc)); 1588 - if (!iio) { 1589 - dev_err(dev, "Failed to allocate IIO device\n"); 1590 - return -ENOMEM; 1591 - } 1592 - 1593 - lradc = iio_priv(iio); 1594 - lradc->soc = (enum mxs_lradc_id)of_id->data; 1595 - 1596 - /* Grab the memory area */ 1597 - iores = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1598 - lradc->dev = &pdev->dev; 1599 - lradc->base = devm_ioremap_resource(dev, iores); 1600 - if (IS_ERR(lradc->base)) 1601 - return PTR_ERR(lradc->base); 1602 - 1603 - lradc->clk = devm_clk_get(&pdev->dev, NULL); 1604 - if (IS_ERR(lradc->clk)) { 1605 - dev_err(dev, "Failed to get the delay unit clock\n"); 1606 - return PTR_ERR(lradc->clk); 1607 - } 1608 - ret = clk_prepare_enable(lradc->clk); 1609 - if (ret != 0) { 1610 - dev_err(dev, "Failed to enable the delay unit clock\n"); 1611 - return ret; 1612 - } 1613 - 1614 - touch_ret = mxs_lradc_probe_touchscreen(lradc, node); 1615 - 1616 - if (touch_ret == 0) 1617 - lradc->buffer_vchans = BUFFER_VCHANS_LIMITED; 1618 - else 1619 - lradc->buffer_vchans = BUFFER_VCHANS_ALL; 1620 - 1621 - /* Grab all IRQ sources */ 1622 - for (i = 0; i < of_cfg->irq_count; i++) { 1623 - lradc->irq[i] = platform_get_irq(pdev, i); 1624 - if (lradc->irq[i] < 0) { 1625 - ret = lradc->irq[i]; 1626 - goto err_clk; 1627 - } 1628 - 1629 - ret = devm_request_irq(dev, lradc->irq[i], 1630 - mxs_lradc_handle_irq, 0, 1631 - of_cfg->irq_name[i], iio); 1632 - if (ret) 1633 - goto err_clk; 1634 - } 1635 - 1636 - lradc->vref_mv = of_cfg->vref_mv; 1637 - 1638 - platform_set_drvdata(pdev, iio); 1639 - 1640 - init_completion(&lradc->completion); 1641 - mutex_init(&lradc->lock); 1642 - 1643 - iio->name = pdev->name; 1644 - iio->dev.parent = &pdev->dev; 1645 - iio->info = &mxs_lradc_iio_info; 1646 - iio->modes = INDIO_DIRECT_MODE; 1647 - iio->masklength = LRADC_MAX_TOTAL_CHANS; 1648 - 1649 - if (lradc->soc == IMX23_LRADC) { 1650 - iio->channels = mx23_lradc_chan_spec; 1651 - iio->num_channels = ARRAY_SIZE(mx23_lradc_chan_spec); 1652 - } else { 1653 - iio->channels = mx28_lradc_chan_spec; 1654 - iio->num_channels = ARRAY_SIZE(mx28_lradc_chan_spec); 1655 - } 1656 - 1657 - ret = iio_triggered_buffer_setup(iio, &iio_pollfunc_store_time, 1658 - &mxs_lradc_trigger_handler, 1659 - &mxs_lradc_buffer_ops); 1660 - if (ret) 1661 - goto err_clk; 1662 - 1663 - ret = mxs_lradc_trigger_init(iio); 1664 - if (ret) 1665 - goto err_trig; 1666 - 1667 - /* Populate available ADC input ranges */ 1668 - for (i = 0; i < LRADC_MAX_TOTAL_CHANS; i++) { 1669 - for (s = 0; s < ARRAY_SIZE(lradc->scale_avail[i]); s++) { 1670 - /* 1671 - * [s=0] = optional divider by two disabled (default) 1672 - * [s=1] = optional divider by two enabled 1673 - * 1674 - * The scale is calculated by doing: 1675 - * Vref >> (realbits - s) 1676 - * which multiplies by two on the second component 1677 - * of the array. 1678 - */ 1679 - scale_uv = ((u64)lradc->vref_mv[i] * 100000000) >> 1680 - (LRADC_RESOLUTION - s); 1681 - lradc->scale_avail[i][s].nano = 1682 - do_div(scale_uv, 100000000) * 10; 1683 - lradc->scale_avail[i][s].integer = scale_uv; 1684 - } 1685 - } 1686 - 1687 - ret = stmp_reset_block(lradc->base); 1688 - if (ret) 1689 - goto err_dev; 1690 - 1691 - /* Configure the hardware. */ 1692 - mxs_lradc_hw_init(lradc); 1693 - 1694 - /* Register the touchscreen input device. */ 1695 - if (touch_ret == 0) { 1696 - ret = mxs_lradc_ts_register(lradc); 1697 - if (ret) 1698 - goto err_ts_register; 1699 - } 1700 - 1701 - /* Register IIO device. */ 1702 - ret = iio_device_register(iio); 1703 - if (ret) { 1704 - dev_err(dev, "Failed to register IIO device\n"); 1705 - return ret; 1706 - } 1707 - 1708 - return 0; 1709 - 1710 - err_ts_register: 1711 - mxs_lradc_hw_stop(lradc); 1712 - err_dev: 1713 - mxs_lradc_trigger_remove(iio); 1714 - err_trig: 1715 - iio_triggered_buffer_cleanup(iio); 1716 - err_clk: 1717 - clk_disable_unprepare(lradc->clk); 1718 - return ret; 1719 - } 1720 - 1721 - static int mxs_lradc_remove(struct platform_device *pdev) 1722 - { 1723 - struct iio_dev *iio = platform_get_drvdata(pdev); 1724 - struct mxs_lradc *lradc = iio_priv(iio); 1725 - 1726 - iio_device_unregister(iio); 1727 - mxs_lradc_hw_stop(lradc); 1728 - mxs_lradc_trigger_remove(iio); 1729 - iio_triggered_buffer_cleanup(iio); 1730 - 1731 - clk_disable_unprepare(lradc->clk); 1732 - 1733 - return 0; 1734 - } 1735 - 1736 - static struct platform_driver mxs_lradc_driver = { 1737 - .driver = { 1738 - .name = DRIVER_NAME, 1739 - .of_match_table = mxs_lradc_dt_ids, 1740 - }, 1741 - .probe = mxs_lradc_probe, 1742 - .remove = mxs_lradc_remove, 1743 - }; 1744 - 1745 - module_platform_driver(mxs_lradc_driver); 1746 - 1747 - MODULE_AUTHOR("Marek Vasut <marex@denx.de>"); 1748 - MODULE_DESCRIPTION("Freescale MXS LRADC driver"); 1749 - MODULE_LICENSE("GPL v2"); 1750 - MODULE_ALIAS("platform:" DRIVER_NAME);
+10
drivers/input/misc/Kconfig
··· 316 316 To compile this driver as a module, choose M here: the 317 317 module will be called cobalt_btns. 318 318 319 + config INPUT_CPCAP_PWRBUTTON 320 + tristate "CPCAP OnKey" 321 + depends on MFD_CPCAP 322 + help 323 + Say Y here if you want to enable power key reporting via the 324 + Motorola CPCAP chip. 325 + 326 + To compile this driver as a module, choose M here. The module will 327 + be called cpcap-pwrbutton. 328 + 319 329 config INPUT_WISTRON_BTNS 320 330 tristate "x86 Wistron laptop button interface" 321 331 depends on X86_32
+1
drivers/input/misc/Makefile
··· 24 24 obj-$(CONFIG_INPUT_CMA3000) += cma3000_d0x.o 25 25 obj-$(CONFIG_INPUT_CMA3000_I2C) += cma3000_d0x_i2c.o 26 26 obj-$(CONFIG_INPUT_COBALT_BTNS) += cobalt_btns.o 27 + obj-$(CONFIG_INPUT_CPCAP_PWRBUTTON) += cpcap-pwrbutton.o 27 28 obj-$(CONFIG_INPUT_DA9052_ONKEY) += da9052_onkey.o 28 29 obj-$(CONFIG_INPUT_DA9055_ONKEY) += da9055_onkey.o 29 30 obj-$(CONFIG_INPUT_DA9063_ONKEY) += da9063_onkey.o
+117
drivers/input/misc/cpcap-pwrbutton.c
··· 1 + /** 2 + * CPCAP Power Button Input Driver 3 + * 4 + * Copyright (C) 2017 Sebastian Reichel <sre@kernel.org> 5 + * 6 + * This file is subject to the terms and conditions of the GNU General 7 + * Public License. See the file "COPYING" in the main directory of this 8 + * archive for more details. 9 + * 10 + * This program is distributed in the hope that it will be useful, 11 + * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 + * GNU General Public License for more details. 14 + */ 15 + 16 + #include <linux/module.h> 17 + #include <linux/init.h> 18 + #include <linux/kernel.h> 19 + #include <linux/errno.h> 20 + #include <linux/input.h> 21 + #include <linux/interrupt.h> 22 + #include <linux/regmap.h> 23 + #include <linux/of.h> 24 + #include <linux/platform_device.h> 25 + #include <linux/mfd/motorola-cpcap.h> 26 + 27 + #define CPCAP_IRQ_ON 23 28 + #define CPCAP_IRQ_ON_BITMASK (1 << (CPCAP_IRQ_ON % 16)) 29 + 30 + struct cpcap_power_button { 31 + struct regmap *regmap; 32 + struct input_dev *idev; 33 + struct device *dev; 34 + }; 35 + 36 + static irqreturn_t powerbutton_irq(int irq, void *_button) 37 + { 38 + struct cpcap_power_button *button = _button; 39 + int val; 40 + 41 + val = cpcap_sense_virq(button->regmap, irq); 42 + if (val < 0) { 43 + dev_err(button->dev, "irq read failed: %d", val); 44 + return IRQ_HANDLED; 45 + } 46 + 47 + pm_wakeup_event(button->dev, 0); 48 + input_report_key(button->idev, KEY_POWER, val); 49 + input_sync(button->idev); 50 + 51 + return IRQ_HANDLED; 52 + } 53 + 54 + static int cpcap_power_button_probe(struct platform_device *pdev) 55 + { 56 + struct cpcap_power_button *button; 57 + int irq = platform_get_irq(pdev, 0); 58 + int err; 59 + 60 + button = devm_kmalloc(&pdev->dev, sizeof(*button), GFP_KERNEL); 61 + if (!button) 62 + return -ENOMEM; 63 + 64 + button->idev = devm_input_allocate_device(&pdev->dev); 65 + if (!button->idev) 66 + return -ENOMEM; 67 + 68 + button->regmap = dev_get_regmap(pdev->dev.parent, NULL); 69 + if (!button->regmap) 70 + return -ENODEV; 71 + 72 + button->dev = &pdev->dev; 73 + 74 + button->idev->name = "cpcap-pwrbutton"; 75 + button->idev->phys = "cpcap-pwrbutton/input0"; 76 + button->idev->dev.parent = button->dev; 77 + input_set_capability(button->idev, EV_KEY, KEY_POWER); 78 + 79 + err = devm_request_threaded_irq(&pdev->dev, irq, NULL, 80 + powerbutton_irq, IRQF_ONESHOT, "cpcap_pwrbutton", button); 81 + if (err < 0) { 82 + dev_err(&pdev->dev, "IRQ request failed: %d\n", err); 83 + return err; 84 + } 85 + 86 + err = input_register_device(button->idev); 87 + if (err) { 88 + dev_err(&pdev->dev, "Input register failed: %d\n", err); 89 + return err; 90 + } 91 + 92 + device_init_wakeup(&pdev->dev, true); 93 + 94 + return 0; 95 + } 96 + 97 + #ifdef CONFIG_OF 98 + static const struct of_device_id cpcap_pwrbutton_dt_match_table[] = { 99 + { .compatible = "motorola,cpcap-pwrbutton" }, 100 + {}, 101 + }; 102 + MODULE_DEVICE_TABLE(of, cpcap_pwrbutton_dt_match_table); 103 + #endif 104 + 105 + static struct platform_driver cpcap_power_button_driver = { 106 + .probe = cpcap_power_button_probe, 107 + .driver = { 108 + .name = "cpcap-pwrbutton", 109 + .of_match_table = of_match_ptr(cpcap_pwrbutton_dt_match_table), 110 + }, 111 + }; 112 + module_platform_driver(cpcap_power_button_driver); 113 + 114 + MODULE_ALIAS("platform:cpcap-pwrbutton"); 115 + MODULE_DESCRIPTION("CPCAP Power Button"); 116 + MODULE_LICENSE("GPL"); 117 + MODULE_AUTHOR("Sebastian Reichel <sre@kernel.org>");
+10
drivers/input/touchscreen/Kconfig
··· 829 829 To compile this driver as a module, choose M here: the 830 830 module will be called usbtouchscreen. 831 831 832 + config TOUCHSCREEN_MXS_LRADC 833 + tristate "Freescale i.MX23/i.MX28 LRADC touchscreen" 834 + depends on MFD_MXS_LRADC 835 + help 836 + Say Y here if you have a touchscreen connected to the low-resolution 837 + analog-to-digital converter (LRADC) on an i.MX23 or i.MX28 processor. 838 + 839 + To compile this driver as a module, choose M here: the module will be 840 + called mxs-lradc-ts. 841 + 832 842 config TOUCHSCREEN_MX25 833 843 tristate "Freescale i.MX25 touchscreen input driver" 834 844 depends on MFD_MX25_TSADC
+1
drivers/input/touchscreen/Makefile
··· 45 45 obj-$(CONFIG_TOUCHSCREEN_IPROC) += bcm_iproc_tsc.o 46 46 obj-$(CONFIG_TOUCHSCREEN_LPC32XX) += lpc32xx_ts.o 47 47 obj-$(CONFIG_TOUCHSCREEN_MAX11801) += max11801_ts.o 48 + obj-$(CONFIG_TOUCHSCREEN_MXS_LRADC) += mxs-lradc-ts.o 48 49 obj-$(CONFIG_TOUCHSCREEN_MX25) += fsl-imx25-tcq.o 49 50 obj-$(CONFIG_TOUCHSCREEN_MC13783) += mc13783_ts.o 50 51 obj-$(CONFIG_TOUCHSCREEN_MCS5000) += mcs5000_ts.o
+714
drivers/input/touchscreen/mxs-lradc-ts.c
··· 1 + /* 2 + * Freescale MXS LRADC touchscreen driver 3 + * 4 + * Copyright (c) 2012 DENX Software Engineering, GmbH. 5 + * Copyright (c) 2017 Ksenija Stanojevic <ksenija.stanojevic@gmail.com> 6 + * 7 + * Authors: 8 + * Marek Vasut <marex@denx.de> 9 + * Ksenija Stanojevic <ksenija.stanojevic@gmail.com> 10 + * 11 + * This program is free software; you can redistribute it and/or modify 12 + * it under the terms of the GNU General Public License as published by 13 + * the Free Software Foundation; either version 2 of the License, or 14 + * (at your option) any later version. 15 + * 16 + * This program is distributed in the hope that it will be useful, 17 + * but WITHOUT ANY WARRANTY; without even the implied warranty of 18 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 19 + * GNU General Public License for more details. 20 + */ 21 + 22 + #include <linux/device.h> 23 + #include <linux/err.h> 24 + #include <linux/input.h> 25 + #include <linux/interrupt.h> 26 + #include <linux/module.h> 27 + #include <linux/mfd/core.h> 28 + #include <linux/mfd/mxs-lradc.h> 29 + #include <linux/of.h> 30 + #include <linux/of_irq.h> 31 + #include <linux/platform_device.h> 32 + 33 + const char *mxs_lradc_ts_irq_names[] = { 34 + "mxs-lradc-touchscreen", 35 + "mxs-lradc-channel6", 36 + "mxs-lradc-channel7", 37 + }; 38 + 39 + /* 40 + * Touchscreen handling 41 + */ 42 + enum mxs_lradc_ts_plate { 43 + LRADC_TOUCH = 0, 44 + LRADC_SAMPLE_X, 45 + LRADC_SAMPLE_Y, 46 + LRADC_SAMPLE_PRESSURE, 47 + LRADC_SAMPLE_VALID, 48 + }; 49 + 50 + struct mxs_lradc_ts { 51 + struct mxs_lradc *lradc; 52 + struct device *dev; 53 + 54 + void __iomem *base; 55 + /* 56 + * When the touchscreen is enabled, we give it two private virtual 57 + * channels: #6 and #7. This means that only 6 virtual channels (instead 58 + * of 8) will be available for buffered capture. 59 + */ 60 + #define TOUCHSCREEN_VCHANNEL1 7 61 + #define TOUCHSCREEN_VCHANNEL2 6 62 + 63 + struct input_dev *ts_input; 64 + 65 + enum mxs_lradc_ts_plate cur_plate; /* state machine */ 66 + bool ts_valid; 67 + unsigned int ts_x_pos; 68 + unsigned int ts_y_pos; 69 + unsigned int ts_pressure; 70 + 71 + /* handle touchscreen's physical behaviour */ 72 + /* samples per coordinate */ 73 + unsigned int over_sample_cnt; 74 + /* time clocks between samples */ 75 + unsigned int over_sample_delay; 76 + /* time in clocks to wait after the plates where switched */ 77 + unsigned int settling_delay; 78 + spinlock_t lock; 79 + }; 80 + 81 + struct state_info { 82 + u32 mask; 83 + u32 bit; 84 + u32 x_plate; 85 + u32 y_plate; 86 + u32 pressure; 87 + }; 88 + 89 + static struct state_info info[] = { 90 + {LRADC_CTRL0_MX23_PLATE_MASK, LRADC_CTRL0_MX23_TOUCH_DETECT_ENABLE, 91 + LRADC_CTRL0_MX23_XP | LRADC_CTRL0_MX23_XM, 92 + LRADC_CTRL0_MX23_YP | LRADC_CTRL0_MX23_YM, 93 + LRADC_CTRL0_MX23_YP | LRADC_CTRL0_MX23_XM}, 94 + {LRADC_CTRL0_MX28_PLATE_MASK, LRADC_CTRL0_MX28_TOUCH_DETECT_ENABLE, 95 + LRADC_CTRL0_MX28_XPPSW | LRADC_CTRL0_MX28_XNNSW, 96 + LRADC_CTRL0_MX28_YPPSW | LRADC_CTRL0_MX28_YNNSW, 97 + LRADC_CTRL0_MX28_YPPSW | LRADC_CTRL0_MX28_XNNSW} 98 + }; 99 + 100 + static bool mxs_lradc_check_touch_event(struct mxs_lradc_ts *ts) 101 + { 102 + return !!(readl(ts->base + LRADC_STATUS) & 103 + LRADC_STATUS_TOUCH_DETECT_RAW); 104 + } 105 + 106 + static void mxs_lradc_map_ts_channel(struct mxs_lradc_ts *ts, unsigned int vch, 107 + unsigned int ch) 108 + { 109 + writel(LRADC_CTRL4_LRADCSELECT_MASK(vch), 110 + ts->base + LRADC_CTRL4 + STMP_OFFSET_REG_CLR); 111 + writel(LRADC_CTRL4_LRADCSELECT(vch, ch), 112 + ts->base + LRADC_CTRL4 + STMP_OFFSET_REG_SET); 113 + } 114 + 115 + static void mxs_lradc_setup_ts_channel(struct mxs_lradc_ts *ts, unsigned int ch) 116 + { 117 + /* 118 + * prepare for oversampling conversion 119 + * 120 + * from the datasheet: 121 + * "The ACCUMULATE bit in the appropriate channel register 122 + * HW_LRADC_CHn must be set to 1 if NUM_SAMPLES is greater then 0; 123 + * otherwise, the IRQs will not fire." 124 + */ 125 + writel(LRADC_CH_ACCUMULATE | 126 + LRADC_CH_NUM_SAMPLES(ts->over_sample_cnt - 1), 127 + ts->base + LRADC_CH(ch)); 128 + 129 + /* from the datasheet: 130 + * "Software must clear this register in preparation for a 131 + * multi-cycle accumulation. 132 + */ 133 + writel(LRADC_CH_VALUE_MASK, 134 + ts->base + LRADC_CH(ch) + STMP_OFFSET_REG_CLR); 135 + 136 + /* 137 + * prepare the delay/loop unit according to the oversampling count 138 + * 139 + * from the datasheet: 140 + * "The DELAY fields in HW_LRADC_DELAY0, HW_LRADC_DELAY1, 141 + * HW_LRADC_DELAY2, and HW_LRADC_DELAY3 must be non-zero; otherwise, 142 + * the LRADC will not trigger the delay group." 143 + */ 144 + writel(LRADC_DELAY_TRIGGER(1 << ch) | LRADC_DELAY_TRIGGER_DELAYS(0) | 145 + LRADC_DELAY_LOOP(ts->over_sample_cnt - 1) | 146 + LRADC_DELAY_DELAY(ts->over_sample_delay - 1), 147 + ts->base + LRADC_DELAY(3)); 148 + 149 + writel(LRADC_CTRL1_LRADC_IRQ(ch), 150 + ts->base + LRADC_CTRL1 + STMP_OFFSET_REG_CLR); 151 + 152 + /* 153 + * after changing the touchscreen plates setting 154 + * the signals need some initial time to settle. Start the 155 + * SoC's delay unit and start the conversion later 156 + * and automatically. 157 + */ 158 + writel(LRADC_DELAY_TRIGGER(0) | LRADC_DELAY_TRIGGER_DELAYS(BIT(3)) | 159 + LRADC_DELAY_KICK | LRADC_DELAY_DELAY(ts->settling_delay), 160 + ts->base + LRADC_DELAY(2)); 161 + } 162 + 163 + /* 164 + * Pressure detection is special: 165 + * We want to do both required measurements for the pressure detection in 166 + * one turn. Use the hardware features to chain both conversions and let the 167 + * hardware report one interrupt if both conversions are done 168 + */ 169 + static void mxs_lradc_setup_ts_pressure(struct mxs_lradc_ts *ts, 170 + unsigned int ch1, unsigned int ch2) 171 + { 172 + u32 reg; 173 + 174 + /* 175 + * prepare for oversampling conversion 176 + * 177 + * from the datasheet: 178 + * "The ACCUMULATE bit in the appropriate channel register 179 + * HW_LRADC_CHn must be set to 1 if NUM_SAMPLES is greater then 0; 180 + * otherwise, the IRQs will not fire." 181 + */ 182 + reg = LRADC_CH_ACCUMULATE | 183 + LRADC_CH_NUM_SAMPLES(ts->over_sample_cnt - 1); 184 + writel(reg, ts->base + LRADC_CH(ch1)); 185 + writel(reg, ts->base + LRADC_CH(ch2)); 186 + 187 + /* from the datasheet: 188 + * "Software must clear this register in preparation for a 189 + * multi-cycle accumulation. 190 + */ 191 + writel(LRADC_CH_VALUE_MASK, 192 + ts->base + LRADC_CH(ch1) + STMP_OFFSET_REG_CLR); 193 + writel(LRADC_CH_VALUE_MASK, 194 + ts->base + LRADC_CH(ch2) + STMP_OFFSET_REG_CLR); 195 + 196 + /* prepare the delay/loop unit according to the oversampling count */ 197 + writel(LRADC_DELAY_TRIGGER(1 << ch1) | LRADC_DELAY_TRIGGER(1 << ch2) | 198 + LRADC_DELAY_TRIGGER_DELAYS(0) | 199 + LRADC_DELAY_LOOP(ts->over_sample_cnt - 1) | 200 + LRADC_DELAY_DELAY(ts->over_sample_delay - 1), 201 + ts->base + LRADC_DELAY(3)); 202 + 203 + writel(LRADC_CTRL1_LRADC_IRQ(ch2), 204 + ts->base + LRADC_CTRL1 + STMP_OFFSET_REG_CLR); 205 + 206 + /* 207 + * after changing the touchscreen plates setting 208 + * the signals need some initial time to settle. Start the 209 + * SoC's delay unit and start the conversion later 210 + * and automatically. 211 + */ 212 + writel(LRADC_DELAY_TRIGGER(0) | LRADC_DELAY_TRIGGER_DELAYS(BIT(3)) | 213 + LRADC_DELAY_KICK | LRADC_DELAY_DELAY(ts->settling_delay), 214 + ts->base + LRADC_DELAY(2)); 215 + } 216 + 217 + static unsigned int mxs_lradc_ts_read_raw_channel(struct mxs_lradc_ts *ts, 218 + unsigned int channel) 219 + { 220 + u32 reg; 221 + unsigned int num_samples, val; 222 + 223 + reg = readl(ts->base + LRADC_CH(channel)); 224 + if (reg & LRADC_CH_ACCUMULATE) 225 + num_samples = ts->over_sample_cnt; 226 + else 227 + num_samples = 1; 228 + 229 + val = (reg & LRADC_CH_VALUE_MASK) >> LRADC_CH_VALUE_OFFSET; 230 + return val / num_samples; 231 + } 232 + 233 + static unsigned int mxs_lradc_read_ts_pressure(struct mxs_lradc_ts *ts, 234 + unsigned int ch1, unsigned int ch2) 235 + { 236 + u32 reg, mask; 237 + unsigned int pressure, m1, m2; 238 + 239 + mask = LRADC_CTRL1_LRADC_IRQ(ch1) | LRADC_CTRL1_LRADC_IRQ(ch2); 240 + reg = readl(ts->base + LRADC_CTRL1) & mask; 241 + 242 + while (reg != mask) { 243 + reg = readl(ts->base + LRADC_CTRL1) & mask; 244 + dev_dbg(ts->dev, "One channel is still busy: %X\n", reg); 245 + } 246 + 247 + m1 = mxs_lradc_ts_read_raw_channel(ts, ch1); 248 + m2 = mxs_lradc_ts_read_raw_channel(ts, ch2); 249 + 250 + if (m2 == 0) { 251 + dev_warn(ts->dev, "Cannot calculate pressure\n"); 252 + return 1 << (LRADC_RESOLUTION - 1); 253 + } 254 + 255 + /* simply scale the value from 0 ... max ADC resolution */ 256 + pressure = m1; 257 + pressure *= (1 << LRADC_RESOLUTION); 258 + pressure /= m2; 259 + 260 + dev_dbg(ts->dev, "Pressure = %u\n", pressure); 261 + return pressure; 262 + } 263 + 264 + #define TS_CH_XP 2 265 + #define TS_CH_YP 3 266 + #define TS_CH_XM 4 267 + #define TS_CH_YM 5 268 + 269 + /* 270 + * YP(open)--+-------------+ 271 + * | |--+ 272 + * | | | 273 + * YM(-)--+-------------+ | 274 + * +--------------+ 275 + * | | 276 + * XP(weak+) XM(open) 277 + * 278 + * "weak+" means 200k Ohm VDDIO 279 + * (-) means GND 280 + */ 281 + static void mxs_lradc_setup_touch_detection(struct mxs_lradc_ts *ts) 282 + { 283 + struct mxs_lradc *lradc = ts->lradc; 284 + 285 + /* 286 + * In order to detect a touch event the 'touch detect enable' bit 287 + * enables: 288 + * - a weak pullup to the X+ connector 289 + * - a strong ground at the Y- connector 290 + */ 291 + writel(info[lradc->soc].mask, 292 + ts->base + LRADC_CTRL0 + STMP_OFFSET_REG_CLR); 293 + writel(info[lradc->soc].bit, 294 + ts->base + LRADC_CTRL0 + STMP_OFFSET_REG_SET); 295 + } 296 + 297 + /* 298 + * YP(meas)--+-------------+ 299 + * | |--+ 300 + * | | | 301 + * YM(open)--+-------------+ | 302 + * +--------------+ 303 + * | | 304 + * XP(+) XM(-) 305 + * 306 + * (+) means here 1.85 V 307 + * (-) means here GND 308 + */ 309 + static void mxs_lradc_prepare_x_pos(struct mxs_lradc_ts *ts) 310 + { 311 + struct mxs_lradc *lradc = ts->lradc; 312 + 313 + writel(info[lradc->soc].mask, 314 + ts->base + LRADC_CTRL0 + STMP_OFFSET_REG_CLR); 315 + writel(info[lradc->soc].x_plate, 316 + ts->base + LRADC_CTRL0 + STMP_OFFSET_REG_SET); 317 + 318 + ts->cur_plate = LRADC_SAMPLE_X; 319 + mxs_lradc_map_ts_channel(ts, TOUCHSCREEN_VCHANNEL1, TS_CH_YP); 320 + mxs_lradc_setup_ts_channel(ts, TOUCHSCREEN_VCHANNEL1); 321 + } 322 + 323 + /* 324 + * YP(+)--+-------------+ 325 + * | |--+ 326 + * | | | 327 + * YM(-)--+-------------+ | 328 + * +--------------+ 329 + * | | 330 + * XP(open) XM(meas) 331 + * 332 + * (+) means here 1.85 V 333 + * (-) means here GND 334 + */ 335 + static void mxs_lradc_prepare_y_pos(struct mxs_lradc_ts *ts) 336 + { 337 + struct mxs_lradc *lradc = ts->lradc; 338 + 339 + writel(info[lradc->soc].mask, 340 + ts->base + LRADC_CTRL0 + STMP_OFFSET_REG_CLR); 341 + writel(info[lradc->soc].y_plate, 342 + ts->base + LRADC_CTRL0 + STMP_OFFSET_REG_SET); 343 + 344 + ts->cur_plate = LRADC_SAMPLE_Y; 345 + mxs_lradc_map_ts_channel(ts, TOUCHSCREEN_VCHANNEL1, TS_CH_XM); 346 + mxs_lradc_setup_ts_channel(ts, TOUCHSCREEN_VCHANNEL1); 347 + } 348 + 349 + /* 350 + * YP(+)--+-------------+ 351 + * | |--+ 352 + * | | | 353 + * YM(meas)--+-------------+ | 354 + * +--------------+ 355 + * | | 356 + * XP(meas) XM(-) 357 + * 358 + * (+) means here 1.85 V 359 + * (-) means here GND 360 + */ 361 + static void mxs_lradc_prepare_pressure(struct mxs_lradc_ts *ts) 362 + { 363 + struct mxs_lradc *lradc = ts->lradc; 364 + 365 + writel(info[lradc->soc].mask, 366 + ts->base + LRADC_CTRL0 + STMP_OFFSET_REG_CLR); 367 + writel(info[lradc->soc].pressure, 368 + ts->base + LRADC_CTRL0 + STMP_OFFSET_REG_SET); 369 + 370 + ts->cur_plate = LRADC_SAMPLE_PRESSURE; 371 + mxs_lradc_map_ts_channel(ts, TOUCHSCREEN_VCHANNEL1, TS_CH_YM); 372 + mxs_lradc_map_ts_channel(ts, TOUCHSCREEN_VCHANNEL2, TS_CH_XP); 373 + mxs_lradc_setup_ts_pressure(ts, TOUCHSCREEN_VCHANNEL2, 374 + TOUCHSCREEN_VCHANNEL1); 375 + } 376 + 377 + static void mxs_lradc_enable_touch_detection(struct mxs_lradc_ts *ts) 378 + { 379 + mxs_lradc_setup_touch_detection(ts); 380 + 381 + ts->cur_plate = LRADC_TOUCH; 382 + writel(LRADC_CTRL1_TOUCH_DETECT_IRQ | LRADC_CTRL1_TOUCH_DETECT_IRQ_EN, 383 + ts->base + LRADC_CTRL1 + STMP_OFFSET_REG_CLR); 384 + writel(LRADC_CTRL1_TOUCH_DETECT_IRQ_EN, 385 + ts->base + LRADC_CTRL1 + STMP_OFFSET_REG_SET); 386 + } 387 + 388 + static void mxs_lradc_start_touch_event(struct mxs_lradc_ts *ts) 389 + { 390 + writel(LRADC_CTRL1_TOUCH_DETECT_IRQ_EN, 391 + ts->base + LRADC_CTRL1 + STMP_OFFSET_REG_CLR); 392 + writel(LRADC_CTRL1_LRADC_IRQ_EN(TOUCHSCREEN_VCHANNEL1), 393 + ts->base + LRADC_CTRL1 + STMP_OFFSET_REG_SET); 394 + /* 395 + * start with the Y-pos, because it uses nearly the same plate 396 + * settings like the touch detection 397 + */ 398 + mxs_lradc_prepare_y_pos(ts); 399 + } 400 + 401 + static void mxs_lradc_report_ts_event(struct mxs_lradc_ts *ts) 402 + { 403 + input_report_abs(ts->ts_input, ABS_X, ts->ts_x_pos); 404 + input_report_abs(ts->ts_input, ABS_Y, ts->ts_y_pos); 405 + input_report_abs(ts->ts_input, ABS_PRESSURE, ts->ts_pressure); 406 + input_report_key(ts->ts_input, BTN_TOUCH, 1); 407 + input_sync(ts->ts_input); 408 + } 409 + 410 + static void mxs_lradc_complete_touch_event(struct mxs_lradc_ts *ts) 411 + { 412 + mxs_lradc_setup_touch_detection(ts); 413 + ts->cur_plate = LRADC_SAMPLE_VALID; 414 + /* 415 + * start a dummy conversion to burn time to settle the signals 416 + * note: we are not interested in the conversion's value 417 + */ 418 + writel(0, ts->base + LRADC_CH(TOUCHSCREEN_VCHANNEL1)); 419 + writel(LRADC_CTRL1_LRADC_IRQ(TOUCHSCREEN_VCHANNEL1) | 420 + LRADC_CTRL1_LRADC_IRQ(TOUCHSCREEN_VCHANNEL2), 421 + ts->base + LRADC_CTRL1 + STMP_OFFSET_REG_CLR); 422 + writel(LRADC_DELAY_TRIGGER(1 << TOUCHSCREEN_VCHANNEL1) | 423 + LRADC_DELAY_KICK | LRADC_DELAY_DELAY(10), 424 + ts->base + LRADC_DELAY(2)); 425 + } 426 + 427 + /* 428 + * in order to avoid false measurements, report only samples where 429 + * the surface is still touched after the position measurement 430 + */ 431 + static void mxs_lradc_finish_touch_event(struct mxs_lradc_ts *ts, bool valid) 432 + { 433 + /* if it is still touched, report the sample */ 434 + if (valid && mxs_lradc_check_touch_event(ts)) { 435 + ts->ts_valid = true; 436 + mxs_lradc_report_ts_event(ts); 437 + } 438 + 439 + /* if it is even still touched, continue with the next measurement */ 440 + if (mxs_lradc_check_touch_event(ts)) { 441 + mxs_lradc_prepare_y_pos(ts); 442 + return; 443 + } 444 + 445 + if (ts->ts_valid) { 446 + /* signal the release */ 447 + ts->ts_valid = false; 448 + input_report_key(ts->ts_input, BTN_TOUCH, 0); 449 + input_sync(ts->ts_input); 450 + } 451 + 452 + /* if it is released, wait for the next touch via IRQ */ 453 + ts->cur_plate = LRADC_TOUCH; 454 + writel(0, ts->base + LRADC_DELAY(2)); 455 + writel(0, ts->base + LRADC_DELAY(3)); 456 + writel(LRADC_CTRL1_TOUCH_DETECT_IRQ | 457 + LRADC_CTRL1_LRADC_IRQ_EN(TOUCHSCREEN_VCHANNEL1) | 458 + LRADC_CTRL1_LRADC_IRQ(TOUCHSCREEN_VCHANNEL1), 459 + ts->base + LRADC_CTRL1 + STMP_OFFSET_REG_CLR); 460 + writel(LRADC_CTRL1_TOUCH_DETECT_IRQ_EN, 461 + ts->base + LRADC_CTRL1 + STMP_OFFSET_REG_SET); 462 + } 463 + 464 + /* touchscreen's state machine */ 465 + static void mxs_lradc_handle_touch(struct mxs_lradc_ts *ts) 466 + { 467 + switch (ts->cur_plate) { 468 + case LRADC_TOUCH: 469 + if (mxs_lradc_check_touch_event(ts)) 470 + mxs_lradc_start_touch_event(ts); 471 + writel(LRADC_CTRL1_TOUCH_DETECT_IRQ, 472 + ts->base + LRADC_CTRL1 + STMP_OFFSET_REG_CLR); 473 + return; 474 + 475 + case LRADC_SAMPLE_Y: 476 + ts->ts_y_pos = 477 + mxs_lradc_ts_read_raw_channel(ts, TOUCHSCREEN_VCHANNEL1); 478 + mxs_lradc_prepare_x_pos(ts); 479 + return; 480 + 481 + case LRADC_SAMPLE_X: 482 + ts->ts_x_pos = 483 + mxs_lradc_ts_read_raw_channel(ts, TOUCHSCREEN_VCHANNEL1); 484 + mxs_lradc_prepare_pressure(ts); 485 + return; 486 + 487 + case LRADC_SAMPLE_PRESSURE: 488 + ts->ts_pressure = 489 + mxs_lradc_read_ts_pressure(ts, 490 + TOUCHSCREEN_VCHANNEL2, 491 + TOUCHSCREEN_VCHANNEL1); 492 + mxs_lradc_complete_touch_event(ts); 493 + return; 494 + 495 + case LRADC_SAMPLE_VALID: 496 + mxs_lradc_finish_touch_event(ts, 1); 497 + break; 498 + } 499 + } 500 + 501 + /* IRQ Handling */ 502 + static irqreturn_t mxs_lradc_ts_handle_irq(int irq, void *data) 503 + { 504 + struct mxs_lradc_ts *ts = data; 505 + struct mxs_lradc *lradc = ts->lradc; 506 + unsigned long reg = readl(ts->base + LRADC_CTRL1); 507 + u32 clr_irq = mxs_lradc_irq_mask(lradc); 508 + const u32 ts_irq_mask = 509 + LRADC_CTRL1_TOUCH_DETECT_IRQ | 510 + LRADC_CTRL1_LRADC_IRQ(TOUCHSCREEN_VCHANNEL1) | 511 + LRADC_CTRL1_LRADC_IRQ(TOUCHSCREEN_VCHANNEL2); 512 + unsigned long flags; 513 + 514 + if (!(reg & mxs_lradc_irq_mask(lradc))) 515 + return IRQ_NONE; 516 + 517 + if (reg & ts_irq_mask) { 518 + spin_lock_irqsave(&ts->lock, flags); 519 + mxs_lradc_handle_touch(ts); 520 + spin_unlock_irqrestore(&ts->lock, flags); 521 + /* Make sure we don't clear the next conversion's interrupt. */ 522 + clr_irq &= ~(LRADC_CTRL1_LRADC_IRQ(TOUCHSCREEN_VCHANNEL1) | 523 + LRADC_CTRL1_LRADC_IRQ(TOUCHSCREEN_VCHANNEL2)); 524 + writel(reg & clr_irq, 525 + ts->base + LRADC_CTRL1 + STMP_OFFSET_REG_CLR); 526 + } 527 + 528 + return IRQ_HANDLED; 529 + } 530 + 531 + static int mxs_lradc_ts_open(struct input_dev *dev) 532 + { 533 + struct mxs_lradc_ts *ts = input_get_drvdata(dev); 534 + 535 + /* Enable the touch-detect circuitry. */ 536 + mxs_lradc_enable_touch_detection(ts); 537 + 538 + return 0; 539 + } 540 + 541 + static void mxs_lradc_ts_stop(struct mxs_lradc_ts *ts) 542 + { 543 + int i; 544 + struct mxs_lradc *lradc = ts->lradc; 545 + 546 + /* stop all interrupts from firing */ 547 + writel(LRADC_CTRL1_TOUCH_DETECT_IRQ_EN | 548 + LRADC_CTRL1_LRADC_IRQ_EN(TOUCHSCREEN_VCHANNEL1) | 549 + LRADC_CTRL1_LRADC_IRQ_EN(TOUCHSCREEN_VCHANNEL2), 550 + ts->base + LRADC_CTRL1 + STMP_OFFSET_REG_CLR); 551 + 552 + /* Power-down touchscreen touch-detect circuitry. */ 553 + writel(info[lradc->soc].mask, 554 + ts->base + LRADC_CTRL0 + STMP_OFFSET_REG_CLR); 555 + 556 + writel(lradc->buffer_vchans << LRADC_CTRL1_LRADC_IRQ_EN_OFFSET, 557 + ts->base + LRADC_CTRL1 + STMP_OFFSET_REG_CLR); 558 + 559 + for (i = 1; i < LRADC_MAX_DELAY_CHANS; i++) 560 + writel(0, ts->base + LRADC_DELAY(i)); 561 + } 562 + 563 + static void mxs_lradc_ts_close(struct input_dev *dev) 564 + { 565 + struct mxs_lradc_ts *ts = input_get_drvdata(dev); 566 + 567 + mxs_lradc_ts_stop(ts); 568 + } 569 + 570 + static void mxs_lradc_ts_hw_init(struct mxs_lradc_ts *ts) 571 + { 572 + struct mxs_lradc *lradc = ts->lradc; 573 + 574 + /* Configure the touchscreen type */ 575 + if (lradc->soc == IMX28_LRADC) { 576 + writel(LRADC_CTRL0_MX28_TOUCH_SCREEN_TYPE, 577 + ts->base + LRADC_CTRL0 + STMP_OFFSET_REG_CLR); 578 + 579 + if (lradc->touchscreen_wire == MXS_LRADC_TOUCHSCREEN_5WIRE) 580 + writel(LRADC_CTRL0_MX28_TOUCH_SCREEN_TYPE, 581 + ts->base + LRADC_CTRL0 + STMP_OFFSET_REG_SET); 582 + } 583 + } 584 + 585 + static int mxs_lradc_ts_register(struct mxs_lradc_ts *ts) 586 + { 587 + struct input_dev *input = ts->ts_input; 588 + struct device *dev = ts->dev; 589 + 590 + input = devm_input_allocate_device(dev); 591 + if (!input) 592 + return -ENOMEM; 593 + 594 + input->name = "mxs-lradc-ts"; 595 + input->id.bustype = BUS_HOST; 596 + input->open = mxs_lradc_ts_open; 597 + input->close = mxs_lradc_ts_close; 598 + 599 + __set_bit(INPUT_PROP_DIRECT, input->propbit); 600 + input_set_capability(input, EV_KEY, BTN_TOUCH); 601 + input_set_abs_params(input, ABS_X, 0, LRADC_SINGLE_SAMPLE_MASK, 0, 0); 602 + input_set_abs_params(input, ABS_Y, 0, LRADC_SINGLE_SAMPLE_MASK, 0, 0); 603 + input_set_abs_params(input, ABS_PRESSURE, 0, LRADC_SINGLE_SAMPLE_MASK, 604 + 0, 0); 605 + 606 + ts->ts_input = input; 607 + input_set_drvdata(input, ts); 608 + 609 + return input_register_device(input); 610 + } 611 + 612 + static int mxs_lradc_ts_probe(struct platform_device *pdev) 613 + { 614 + struct device *dev = &pdev->dev; 615 + struct device_node *node = dev->parent->of_node; 616 + struct mxs_lradc *lradc = dev_get_drvdata(dev->parent); 617 + struct mxs_lradc_ts *ts; 618 + struct resource *iores; 619 + int ret, irq, virq, i; 620 + u32 ts_wires = 0, adapt; 621 + 622 + ts = devm_kzalloc(dev, sizeof(*ts), GFP_KERNEL); 623 + if (!ts) 624 + return -ENOMEM; 625 + 626 + platform_set_drvdata(pdev, ts); 627 + 628 + ts->lradc = lradc; 629 + ts->dev = dev; 630 + spin_lock_init(&ts->lock); 631 + 632 + iores = platform_get_resource(pdev, IORESOURCE_MEM, 0); 633 + ts->base = devm_ioremap(dev, iores->start, resource_size(iores)); 634 + if (IS_ERR(ts->base)) 635 + return PTR_ERR(ts->base); 636 + 637 + ret = of_property_read_u32(node, "fsl,lradc-touchscreen-wires", 638 + &ts_wires); 639 + if (ret) 640 + return ret; 641 + 642 + if (of_property_read_u32(node, "fsl,ave-ctrl", &adapt)) { 643 + ts->over_sample_cnt = 4; 644 + } else { 645 + if (adapt >= 1 || adapt <= 32) { 646 + ts->over_sample_cnt = adapt; 647 + } else { 648 + dev_err(ts->dev, "Invalid sample count (%u)\n", 649 + adapt); 650 + return -EINVAL; 651 + } 652 + } 653 + 654 + if (of_property_read_u32(node, "fsl,ave-delay", &adapt)) { 655 + ts->over_sample_delay = 2; 656 + } else { 657 + if (adapt >= 2 || adapt <= LRADC_DELAY_DELAY_MASK + 1) { 658 + ts->over_sample_delay = adapt; 659 + } else { 660 + dev_err(ts->dev, "Invalid sample delay (%u)\n", 661 + adapt); 662 + return -EINVAL; 663 + } 664 + } 665 + 666 + if (of_property_read_u32(node, "fsl,settling", &adapt)) { 667 + ts->settling_delay = 10; 668 + } else { 669 + if (adapt >= 1 || adapt <= LRADC_DELAY_DELAY_MASK) { 670 + ts->settling_delay = adapt; 671 + } else { 672 + dev_err(ts->dev, "Invalid settling delay (%u)\n", 673 + adapt); 674 + return -EINVAL; 675 + } 676 + } 677 + 678 + ret = stmp_reset_block(ts->base); 679 + if (ret) 680 + return ret; 681 + 682 + mxs_lradc_ts_hw_init(ts); 683 + 684 + for (i = 0; i < 3; i++) { 685 + irq = platform_get_irq_byname(pdev, mxs_lradc_ts_irq_names[i]); 686 + if (irq < 0) 687 + return irq; 688 + 689 + virq = irq_of_parse_and_map(node, irq); 690 + 691 + mxs_lradc_ts_stop(ts); 692 + 693 + ret = devm_request_irq(dev, virq, 694 + mxs_lradc_ts_handle_irq, 695 + 0, mxs_lradc_ts_irq_names[i], ts); 696 + if (ret) 697 + return ret; 698 + } 699 + 700 + return mxs_lradc_ts_register(ts); 701 + } 702 + 703 + static struct platform_driver mxs_lradc_ts_driver = { 704 + .driver = { 705 + .name = "mxs-lradc-ts", 706 + }, 707 + .probe = mxs_lradc_ts_probe, 708 + }; 709 + module_platform_driver(mxs_lradc_ts_driver); 710 + 711 + MODULE_AUTHOR("Marek Vasut <marex@denx.de>"); 712 + MODULE_DESCRIPTION("Freescale MXS LRADC touchscreen driver"); 713 + MODULE_LICENSE("GPL"); 714 + MODULE_ALIAS("platform:mxs-lradc-ts");
+17
drivers/mfd/Kconfig
··· 344 344 help 345 345 Select this if your MC13xxx is connected via an I2C bus. 346 346 347 + config MFD_MXS_LRADC 348 + tristate "Freescale i.MX23/i.MX28 LRADC" 349 + depends on ARCH_MXS || COMPILE_TEST 350 + select MFD_CORE 351 + select STMP_DEVICE 352 + help 353 + Say yes here to build support for the Low Resolution 354 + Analog-to-Digital Converter (LRADC) found on the i.MX23 and i.MX28 355 + processors. This driver provides common support for accessing the 356 + device, additional drivers must be enabled in order to use the 357 + functionality of the device: 358 + mxs-lradc-adc for ADC readings 359 + mxs-lradc-ts for touchscreen support 360 + 361 + This driver can also be built as a module. If so, the module will be 362 + called mxs-lradc. 363 + 347 364 config MFD_MX25_TSADC 348 365 tristate "Freescale i.MX25 integrated Touchscreen and ADC unit" 349 366 select REGMAP_MMIO
+1
drivers/mfd/Makefile
··· 215 215 obj-$(CONFIG_MFD_SUN4I_GPADC) += sun4i-gpadc.o 216 216 217 217 obj-$(CONFIG_MFD_STM32_TIMERS) += stm32-timers.o 218 + obj-$(CONFIG_MFD_MXS_LRADC) += mxs-lradc.o
+2 -2
drivers/mfd/exynos-lpass.c
··· 18 18 #include <linux/io.h> 19 19 #include <linux/module.h> 20 20 #include <linux/mfd/syscon.h> 21 - #include <linux/mfd/syscon/exynos5-pmu.h> 22 21 #include <linux/of.h> 23 22 #include <linux/of_platform.h> 24 23 #include <linux/platform_device.h> 25 24 #include <linux/regmap.h> 25 + #include <linux/soc/samsung/exynos-regs-pmu.h> 26 26 #include <linux/types.h> 27 27 28 28 /* LPASS Top register definitions */ ··· 83 83 84 84 /* Activate related PADs from retention state */ 85 85 regmap_write(lpass->pmu, EXYNOS5433_PAD_RETENTION_AUD_OPTION, 86 - EXYNOS5433_PAD_INITIATE_WAKEUP_FROM_LOWPWR); 86 + EXYNOS_WAKEUP_FROM_LOWPWR); 87 87 88 88 exynos_lpass_core_sw_reset(lpass, LPASS_I2S_SW_RESET); 89 89 exynos_lpass_core_sw_reset(lpass, LPASS_DMA_SW_RESET);
+28
drivers/mfd/motorola-cpcap.c
··· 23 23 24 24 #define CPCAP_NR_IRQ_REG_BANKS 6 25 25 #define CPCAP_NR_IRQ_CHIPS 3 26 + #define CPCAP_REGISTER_SIZE 4 27 + #define CPCAP_REGISTER_BITS 16 26 28 27 29 struct cpcap_ddata { 28 30 struct spi_device *spi; ··· 33 31 const struct regmap_config *regmap_conf; 34 32 struct regmap *regmap; 35 33 }; 34 + 35 + static int cpcap_sense_irq(struct regmap *regmap, int irq) 36 + { 37 + int regnum = irq / CPCAP_REGISTER_BITS; 38 + int mask = BIT(irq % CPCAP_REGISTER_BITS); 39 + int reg = CPCAP_REG_INTS1 + (regnum * CPCAP_REGISTER_SIZE); 40 + int err, val; 41 + 42 + if (reg < CPCAP_REG_INTS1 || reg > CPCAP_REG_INTS4) 43 + return -EINVAL; 44 + 45 + err = regmap_read(regmap, reg, &val); 46 + if (err) 47 + return err; 48 + 49 + return !!(val & mask); 50 + } 51 + 52 + int cpcap_sense_virq(struct regmap *regmap, int virq) 53 + { 54 + struct regmap_irq_chip_data *d = irq_get_chip_data(virq); 55 + int irq_base = regmap_irq_chip_get_base(d); 56 + 57 + return cpcap_sense_irq(regmap, virq - irq_base); 58 + } 59 + EXPORT_SYMBOL_GPL(cpcap_sense_virq); 36 60 37 61 static int cpcap_check_revision(struct cpcap_ddata *cpcap) 38 62 {
+267
drivers/mfd/mxs-lradc.c
··· 1 + /* 2 + * Freescale MXS Low Resolution Analog-to-Digital Converter driver 3 + * 4 + * Copyright (c) 2012 DENX Software Engineering, GmbH. 5 + * Copyright (c) 2017 Ksenija Stanojevic <ksenija.stanojevic@gmail.com> 6 + * 7 + * Authors: 8 + * Marek Vasut <marex@denx.de> 9 + * Ksenija Stanojevic <ksenija.stanojevic@gmail.com> 10 + * 11 + * This program is free software; you can redistribute it and/or modify 12 + * it under the terms of the GNU General Public License as published by 13 + * the Free Software Foundation; either version 2 of the License, or 14 + * (at your option) any later version. 15 + * 16 + * This program is distributed in the hope that it will be useful, 17 + * but WITHOUT ANY WARRANTY; without even the implied warranty of 18 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 19 + * GNU General Public License for more details. 20 + */ 21 + 22 + #include <linux/clk.h> 23 + #include <linux/device.h> 24 + #include <linux/mfd/core.h> 25 + #include <linux/mfd/mxs-lradc.h> 26 + #include <linux/module.h> 27 + #include <linux/of.h> 28 + #include <linux/of_device.h> 29 + #include <linux/platform_device.h> 30 + #include <linux/slab.h> 31 + 32 + #define ADC_CELL 0 33 + #define TSC_CELL 1 34 + #define RES_MEM 0 35 + 36 + enum mx23_lradc_irqs { 37 + MX23_LRADC_TS_IRQ = 0, 38 + MX23_LRADC_CH0_IRQ, 39 + MX23_LRADC_CH1_IRQ, 40 + MX23_LRADC_CH2_IRQ, 41 + MX23_LRADC_CH3_IRQ, 42 + MX23_LRADC_CH4_IRQ, 43 + MX23_LRADC_CH5_IRQ, 44 + MX23_LRADC_CH6_IRQ, 45 + MX23_LRADC_CH7_IRQ, 46 + }; 47 + 48 + enum mx28_lradc_irqs { 49 + MX28_LRADC_TS_IRQ = 0, 50 + MX28_LRADC_TRESH0_IRQ, 51 + MX28_LRADC_TRESH1_IRQ, 52 + MX28_LRADC_CH0_IRQ, 53 + MX28_LRADC_CH1_IRQ, 54 + MX28_LRADC_CH2_IRQ, 55 + MX28_LRADC_CH3_IRQ, 56 + MX28_LRADC_CH4_IRQ, 57 + MX28_LRADC_CH5_IRQ, 58 + MX28_LRADC_CH6_IRQ, 59 + MX28_LRADC_CH7_IRQ, 60 + MX28_LRADC_BUTTON0_IRQ, 61 + MX28_LRADC_BUTTON1_IRQ, 62 + }; 63 + 64 + static struct resource mx23_adc_resources[] = { 65 + DEFINE_RES_MEM(0x0, 0x0), 66 + DEFINE_RES_IRQ_NAMED(MX23_LRADC_CH0_IRQ, "mxs-lradc-channel0"), 67 + DEFINE_RES_IRQ_NAMED(MX23_LRADC_CH1_IRQ, "mxs-lradc-channel1"), 68 + DEFINE_RES_IRQ_NAMED(MX23_LRADC_CH2_IRQ, "mxs-lradc-channel2"), 69 + DEFINE_RES_IRQ_NAMED(MX23_LRADC_CH3_IRQ, "mxs-lradc-channel3"), 70 + DEFINE_RES_IRQ_NAMED(MX23_LRADC_CH4_IRQ, "mxs-lradc-channel4"), 71 + DEFINE_RES_IRQ_NAMED(MX23_LRADC_CH5_IRQ, "mxs-lradc-channel5"), 72 + }; 73 + 74 + static struct resource mx23_touchscreen_resources[] = { 75 + DEFINE_RES_MEM(0x0, 0x0), 76 + DEFINE_RES_IRQ_NAMED(MX23_LRADC_TS_IRQ, "mxs-lradc-touchscreen"), 77 + DEFINE_RES_IRQ_NAMED(MX23_LRADC_CH6_IRQ, "mxs-lradc-channel6"), 78 + DEFINE_RES_IRQ_NAMED(MX23_LRADC_CH7_IRQ, "mxs-lradc-channel7"), 79 + }; 80 + 81 + static struct resource mx28_adc_resources[] = { 82 + DEFINE_RES_MEM(0x0, 0x0), 83 + DEFINE_RES_IRQ_NAMED(MX28_LRADC_TRESH0_IRQ, "mxs-lradc-thresh0"), 84 + DEFINE_RES_IRQ_NAMED(MX28_LRADC_TRESH1_IRQ, "mxs-lradc-thresh1"), 85 + DEFINE_RES_IRQ_NAMED(MX28_LRADC_CH0_IRQ, "mxs-lradc-channel0"), 86 + DEFINE_RES_IRQ_NAMED(MX28_LRADC_CH1_IRQ, "mxs-lradc-channel1"), 87 + DEFINE_RES_IRQ_NAMED(MX28_LRADC_CH2_IRQ, "mxs-lradc-channel2"), 88 + DEFINE_RES_IRQ_NAMED(MX28_LRADC_CH3_IRQ, "mxs-lradc-channel3"), 89 + DEFINE_RES_IRQ_NAMED(MX28_LRADC_CH4_IRQ, "mxs-lradc-channel4"), 90 + DEFINE_RES_IRQ_NAMED(MX28_LRADC_CH5_IRQ, "mxs-lradc-channel5"), 91 + DEFINE_RES_IRQ_NAMED(MX28_LRADC_BUTTON0_IRQ, "mxs-lradc-button0"), 92 + DEFINE_RES_IRQ_NAMED(MX28_LRADC_BUTTON1_IRQ, "mxs-lradc-button1"), 93 + }; 94 + 95 + static struct resource mx28_touchscreen_resources[] = { 96 + DEFINE_RES_MEM(0x0, 0x0), 97 + DEFINE_RES_IRQ_NAMED(MX28_LRADC_TS_IRQ, "mxs-lradc-touchscreen"), 98 + DEFINE_RES_IRQ_NAMED(MX28_LRADC_CH6_IRQ, "mxs-lradc-channel6"), 99 + DEFINE_RES_IRQ_NAMED(MX28_LRADC_CH7_IRQ, "mxs-lradc-channel7"), 100 + }; 101 + 102 + static struct mfd_cell mx23_cells[] = { 103 + { 104 + .name = "mxs-lradc-adc", 105 + .resources = mx23_adc_resources, 106 + .num_resources = ARRAY_SIZE(mx23_adc_resources), 107 + }, 108 + { 109 + .name = "mxs-lradc-ts", 110 + .resources = mx23_touchscreen_resources, 111 + .num_resources = ARRAY_SIZE(mx23_touchscreen_resources), 112 + }, 113 + }; 114 + 115 + static struct mfd_cell mx28_cells[] = { 116 + { 117 + .name = "mxs-lradc-adc", 118 + .resources = mx28_adc_resources, 119 + .num_resources = ARRAY_SIZE(mx28_adc_resources), 120 + }, 121 + { 122 + .name = "mxs-lradc-ts", 123 + .resources = mx28_touchscreen_resources, 124 + .num_resources = ARRAY_SIZE(mx28_touchscreen_resources), 125 + } 126 + }; 127 + 128 + static const struct of_device_id mxs_lradc_dt_ids[] = { 129 + { .compatible = "fsl,imx23-lradc", .data = (void *)IMX23_LRADC, }, 130 + { .compatible = "fsl,imx28-lradc", .data = (void *)IMX28_LRADC, }, 131 + { /* sentinel */ } 132 + }; 133 + MODULE_DEVICE_TABLE(of, mxs_lradc_dt_ids); 134 + 135 + static int mxs_lradc_probe(struct platform_device *pdev) 136 + { 137 + const struct of_device_id *of_id; 138 + struct device *dev = &pdev->dev; 139 + struct device_node *node = dev->of_node; 140 + struct mxs_lradc *lradc; 141 + struct mfd_cell *cells = NULL; 142 + struct resource *res; 143 + int ret = 0; 144 + u32 ts_wires = 0; 145 + 146 + lradc = devm_kzalloc(&pdev->dev, sizeof(*lradc), GFP_KERNEL); 147 + if (!lradc) 148 + return -ENOMEM; 149 + 150 + of_id = of_match_device(mxs_lradc_dt_ids, &pdev->dev); 151 + if (!of_id) 152 + return -EINVAL; 153 + 154 + lradc->soc = (enum mxs_lradc_id)of_id->data; 155 + 156 + lradc->clk = devm_clk_get(&pdev->dev, NULL); 157 + if (IS_ERR(lradc->clk)) { 158 + dev_err(dev, "Failed to get the delay unit clock\n"); 159 + return PTR_ERR(lradc->clk); 160 + } 161 + 162 + ret = clk_prepare_enable(lradc->clk); 163 + if (ret) { 164 + dev_err(dev, "Failed to enable the delay unit clock\n"); 165 + return ret; 166 + } 167 + 168 + ret = of_property_read_u32(node, "fsl,lradc-touchscreen-wires", 169 + &ts_wires); 170 + 171 + if (!ret) { 172 + lradc->buffer_vchans = BUFFER_VCHANS_LIMITED; 173 + 174 + switch (ts_wires) { 175 + case 4: 176 + lradc->touchscreen_wire = MXS_LRADC_TOUCHSCREEN_4WIRE; 177 + break; 178 + case 5: 179 + if (lradc->soc == IMX28_LRADC) { 180 + lradc->touchscreen_wire = 181 + MXS_LRADC_TOUCHSCREEN_5WIRE; 182 + break; 183 + } 184 + /* fall through to an error message for i.MX23 */ 185 + default: 186 + dev_err(&pdev->dev, 187 + "Unsupported number of touchscreen wires (%d)\n" 188 + , ts_wires); 189 + ret = -EINVAL; 190 + goto err_clk; 191 + } 192 + } else { 193 + lradc->buffer_vchans = BUFFER_VCHANS_ALL; 194 + } 195 + 196 + platform_set_drvdata(pdev, lradc); 197 + 198 + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 199 + if (!res) 200 + return -ENOMEM; 201 + 202 + switch (lradc->soc) { 203 + case IMX23_LRADC: 204 + mx23_adc_resources[RES_MEM] = *res; 205 + mx23_touchscreen_resources[RES_MEM] = *res; 206 + cells = mx23_cells; 207 + break; 208 + case IMX28_LRADC: 209 + mx28_adc_resources[RES_MEM] = *res; 210 + mx28_touchscreen_resources[RES_MEM] = *res; 211 + cells = mx28_cells; 212 + break; 213 + default: 214 + dev_err(dev, "Unsupported SoC\n"); 215 + ret = -ENODEV; 216 + goto err_clk; 217 + } 218 + 219 + ret = devm_mfd_add_devices(&pdev->dev, PLATFORM_DEVID_NONE, 220 + &cells[ADC_CELL], 1, NULL, 0, NULL); 221 + if (ret) { 222 + dev_err(&pdev->dev, "Failed to add the ADC subdevice\n"); 223 + goto err_clk; 224 + } 225 + 226 + if (!lradc->touchscreen_wire) 227 + return 0; 228 + 229 + ret = devm_mfd_add_devices(&pdev->dev, PLATFORM_DEVID_NONE, 230 + &cells[TSC_CELL], 1, NULL, 0, NULL); 231 + if (ret) { 232 + dev_err(&pdev->dev, 233 + "Failed to add the touchscreen subdevice\n"); 234 + goto err_clk; 235 + } 236 + 237 + return 0; 238 + 239 + err_clk: 240 + clk_disable_unprepare(lradc->clk); 241 + 242 + return ret; 243 + } 244 + 245 + static int mxs_lradc_remove(struct platform_device *pdev) 246 + { 247 + struct mxs_lradc *lradc = platform_get_drvdata(pdev); 248 + 249 + clk_disable_unprepare(lradc->clk); 250 + 251 + return 0; 252 + } 253 + 254 + static struct platform_driver mxs_lradc_driver = { 255 + .driver = { 256 + .name = "mxs-lradc", 257 + .of_match_table = mxs_lradc_dt_ids, 258 + }, 259 + .probe = mxs_lradc_probe, 260 + .remove = mxs_lradc_remove, 261 + }; 262 + module_platform_driver(mxs_lradc_driver); 263 + 264 + MODULE_AUTHOR("Ksenija Stanojevic <ksenija.stanojevic@gmail.com>"); 265 + MODULE_DESCRIPTION("Freescale i.MX23/i.MX28 LRADC driver"); 266 + MODULE_LICENSE("GPL"); 267 + MODULE_ALIAS("platform:mxs-lradc");
+63
drivers/pinctrl/samsung/pinctrl-exynos.c
··· 777 777 { 778 778 struct samsung_retention_ctrl *ctrl; 779 779 struct regmap *pmu_regs; 780 + int i; 780 781 781 782 ctrl = devm_kzalloc(drvdata->dev, sizeof(*ctrl), GFP_KERNEL); 782 783 if (!ctrl) ··· 794 793 ctrl->refcnt = data->refcnt; 795 794 ctrl->enable = exynos_retention_enable; 796 795 ctrl->disable = exynos_retention_disable; 796 + 797 + /* Ensure that retention is disabled on driver init */ 798 + for (i = 0; i < ctrl->nr_regs; i++) 799 + regmap_write(pmu_regs, ctrl->regs[i], ctrl->value); 797 800 798 801 return ctrl; 799 802 } ··· 1551 1546 EXYNOS_PIN_BANK_EINTG(3, 0x000, "gpj1", 0x00), 1552 1547 }; 1553 1548 1549 + /* PMU pin retention groups registers for Exynos5433 (without audio & fsys) */ 1550 + static const u32 exynos5433_retention_regs[] = { 1551 + EXYNOS5433_PAD_RETENTION_TOP_OPTION, 1552 + EXYNOS5433_PAD_RETENTION_UART_OPTION, 1553 + EXYNOS5433_PAD_RETENTION_EBIA_OPTION, 1554 + EXYNOS5433_PAD_RETENTION_EBIB_OPTION, 1555 + EXYNOS5433_PAD_RETENTION_SPI_OPTION, 1556 + EXYNOS5433_PAD_RETENTION_MIF_OPTION, 1557 + EXYNOS5433_PAD_RETENTION_USBXTI_OPTION, 1558 + EXYNOS5433_PAD_RETENTION_BOOTLDO_OPTION, 1559 + EXYNOS5433_PAD_RETENTION_UFS_OPTION, 1560 + EXYNOS5433_PAD_RETENTION_FSYSGENIO_OPTION, 1561 + }; 1562 + 1563 + static const struct samsung_retention_data exynos5433_retention_data __initconst = { 1564 + .regs = exynos5433_retention_regs, 1565 + .nr_regs = ARRAY_SIZE(exynos5433_retention_regs), 1566 + .value = EXYNOS_WAKEUP_FROM_LOWPWR, 1567 + .refcnt = &exynos_shared_retention_refcnt, 1568 + .init = exynos_retention_init, 1569 + }; 1570 + 1571 + /* PMU retention control for audio pins can be tied to audio pin bank */ 1572 + static const u32 exynos5433_audio_retention_regs[] = { 1573 + EXYNOS5433_PAD_RETENTION_AUD_OPTION, 1574 + }; 1575 + 1576 + static const struct samsung_retention_data exynos5433_audio_retention_data __initconst = { 1577 + .regs = exynos5433_audio_retention_regs, 1578 + .nr_regs = ARRAY_SIZE(exynos5433_audio_retention_regs), 1579 + .value = EXYNOS_WAKEUP_FROM_LOWPWR, 1580 + .init = exynos_retention_init, 1581 + }; 1582 + 1583 + /* PMU retention control for mmc pins can be tied to fsys pin bank */ 1584 + static const u32 exynos5433_fsys_retention_regs[] = { 1585 + EXYNOS5433_PAD_RETENTION_MMC0_OPTION, 1586 + EXYNOS5433_PAD_RETENTION_MMC1_OPTION, 1587 + EXYNOS5433_PAD_RETENTION_MMC2_OPTION, 1588 + }; 1589 + 1590 + static const struct samsung_retention_data exynos5433_fsys_retention_data __initconst = { 1591 + .regs = exynos5433_fsys_retention_regs, 1592 + .nr_regs = ARRAY_SIZE(exynos5433_fsys_retention_regs), 1593 + .value = EXYNOS_WAKEUP_FROM_LOWPWR, 1594 + .init = exynos_retention_init, 1595 + }; 1596 + 1554 1597 /* 1555 1598 * Samsung pinctrl driver data for Exynos5433 SoC. Exynos5433 SoC includes 1556 1599 * ten gpio/pin-mux/pinconfig controllers. ··· 1612 1559 .suspend = exynos_pinctrl_suspend, 1613 1560 .resume = exynos_pinctrl_resume, 1614 1561 .nr_ext_resources = 1, 1562 + .retention_data = &exynos5433_retention_data, 1615 1563 }, { 1616 1564 /* pin-controller instance 1 data */ 1617 1565 .pin_banks = exynos5433_pin_banks1, ··· 1620 1566 .eint_gpio_init = exynos_eint_gpio_init, 1621 1567 .suspend = exynos_pinctrl_suspend, 1622 1568 .resume = exynos_pinctrl_resume, 1569 + .retention_data = &exynos5433_audio_retention_data, 1623 1570 }, { 1624 1571 /* pin-controller instance 2 data */ 1625 1572 .pin_banks = exynos5433_pin_banks2, ··· 1628 1573 .eint_gpio_init = exynos_eint_gpio_init, 1629 1574 .suspend = exynos_pinctrl_suspend, 1630 1575 .resume = exynos_pinctrl_resume, 1576 + .retention_data = &exynos5433_retention_data, 1631 1577 }, { 1632 1578 /* pin-controller instance 3 data */ 1633 1579 .pin_banks = exynos5433_pin_banks3, ··· 1636 1580 .eint_gpio_init = exynos_eint_gpio_init, 1637 1581 .suspend = exynos_pinctrl_suspend, 1638 1582 .resume = exynos_pinctrl_resume, 1583 + .retention_data = &exynos5433_retention_data, 1639 1584 }, { 1640 1585 /* pin-controller instance 4 data */ 1641 1586 .pin_banks = exynos5433_pin_banks4, ··· 1644 1587 .eint_gpio_init = exynos_eint_gpio_init, 1645 1588 .suspend = exynos_pinctrl_suspend, 1646 1589 .resume = exynos_pinctrl_resume, 1590 + .retention_data = &exynos5433_retention_data, 1647 1591 }, { 1648 1592 /* pin-controller instance 5 data */ 1649 1593 .pin_banks = exynos5433_pin_banks5, ··· 1652 1594 .eint_gpio_init = exynos_eint_gpio_init, 1653 1595 .suspend = exynos_pinctrl_suspend, 1654 1596 .resume = exynos_pinctrl_resume, 1597 + .retention_data = &exynos5433_fsys_retention_data, 1655 1598 }, { 1656 1599 /* pin-controller instance 6 data */ 1657 1600 .pin_banks = exynos5433_pin_banks6, ··· 1660 1601 .eint_gpio_init = exynos_eint_gpio_init, 1661 1602 .suspend = exynos_pinctrl_suspend, 1662 1603 .resume = exynos_pinctrl_resume, 1604 + .retention_data = &exynos5433_retention_data, 1663 1605 }, { 1664 1606 /* pin-controller instance 7 data */ 1665 1607 .pin_banks = exynos5433_pin_banks7, ··· 1668 1608 .eint_gpio_init = exynos_eint_gpio_init, 1669 1609 .suspend = exynos_pinctrl_suspend, 1670 1610 .resume = exynos_pinctrl_resume, 1611 + .retention_data = &exynos5433_retention_data, 1671 1612 }, { 1672 1613 /* pin-controller instance 8 data */ 1673 1614 .pin_banks = exynos5433_pin_banks8, ··· 1676 1615 .eint_gpio_init = exynos_eint_gpio_init, 1677 1616 .suspend = exynos_pinctrl_suspend, 1678 1617 .resume = exynos_pinctrl_resume, 1618 + .retention_data = &exynos5433_retention_data, 1679 1619 }, { 1680 1620 /* pin-controller instance 9 data */ 1681 1621 .pin_banks = exynos5433_pin_banks9, ··· 1684 1622 .eint_gpio_init = exynos_eint_gpio_init, 1685 1623 .suspend = exynos_pinctrl_suspend, 1686 1624 .resume = exynos_pinctrl_resume, 1625 + .retention_data = &exynos5433_retention_data, 1687 1626 }, 1688 1627 }; 1689 1628
+5
include/linux/mfd/motorola-cpcap.h
··· 14 14 * published by the Free Software Foundation. 15 15 */ 16 16 17 + #include <linux/device.h> 18 + #include <linux/regmap.h> 19 + 17 20 #define CPCAP_VENDOR_ST 0 18 21 #define CPCAP_VENDOR_TI 1 19 22 ··· 293 290 294 291 return 0; 295 292 } 293 + 294 + extern int cpcap_sense_virq(struct regmap *regmap, int virq);
+187
include/linux/mfd/mxs-lradc.h
··· 1 + /* 2 + * Freescale MXS Low Resolution Analog-to-Digital Converter driver 3 + * 4 + * Copyright (c) 2012 DENX Software Engineering, GmbH. 5 + * Copyright (c) 2016 Ksenija Stanojevic <ksenija.stanojevic@gmail.com> 6 + * 7 + * Author: Marek Vasut <marex@denx.de> 8 + * 9 + * This program is free software; you can redistribute it and/or modify 10 + * it under the terms of the GNU General Public License as published by 11 + * the Free Software Foundation; either version 2 of the License, or 12 + * (at your option) any later version. 13 + * 14 + * This program is distributed in the hope that it will be useful, 15 + * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 + * GNU General Public License for more details. 18 + */ 19 + 20 + #ifndef __MFD_MXS_LRADC_H 21 + #define __MFD_MXS_LRADC_H 22 + 23 + #include <linux/bitops.h> 24 + #include <linux/io.h> 25 + #include <linux/stmp_device.h> 26 + 27 + #define LRADC_MAX_DELAY_CHANS 4 28 + #define LRADC_MAX_MAPPED_CHANS 8 29 + #define LRADC_MAX_TOTAL_CHANS 16 30 + 31 + #define LRADC_DELAY_TIMER_HZ 2000 32 + 33 + #define LRADC_CTRL0 0x00 34 + # define LRADC_CTRL0_MX28_TOUCH_DETECT_ENABLE BIT(23) 35 + # define LRADC_CTRL0_MX28_TOUCH_SCREEN_TYPE BIT(22) 36 + # define LRADC_CTRL0_MX28_YNNSW /* YM */ BIT(21) 37 + # define LRADC_CTRL0_MX28_YPNSW /* YP */ BIT(20) 38 + # define LRADC_CTRL0_MX28_YPPSW /* YP */ BIT(19) 39 + # define LRADC_CTRL0_MX28_XNNSW /* XM */ BIT(18) 40 + # define LRADC_CTRL0_MX28_XNPSW /* XM */ BIT(17) 41 + # define LRADC_CTRL0_MX28_XPPSW /* XP */ BIT(16) 42 + 43 + # define LRADC_CTRL0_MX23_TOUCH_DETECT_ENABLE BIT(20) 44 + # define LRADC_CTRL0_MX23_YM BIT(19) 45 + # define LRADC_CTRL0_MX23_XM BIT(18) 46 + # define LRADC_CTRL0_MX23_YP BIT(17) 47 + # define LRADC_CTRL0_MX23_XP BIT(16) 48 + 49 + # define LRADC_CTRL0_MX28_PLATE_MASK \ 50 + (LRADC_CTRL0_MX28_TOUCH_DETECT_ENABLE | \ 51 + LRADC_CTRL0_MX28_YNNSW | LRADC_CTRL0_MX28_YPNSW | \ 52 + LRADC_CTRL0_MX28_YPPSW | LRADC_CTRL0_MX28_XNNSW | \ 53 + LRADC_CTRL0_MX28_XNPSW | LRADC_CTRL0_MX28_XPPSW) 54 + 55 + # define LRADC_CTRL0_MX23_PLATE_MASK \ 56 + (LRADC_CTRL0_MX23_TOUCH_DETECT_ENABLE | \ 57 + LRADC_CTRL0_MX23_YM | LRADC_CTRL0_MX23_XM | \ 58 + LRADC_CTRL0_MX23_YP | LRADC_CTRL0_MX23_XP) 59 + 60 + #define LRADC_CTRL1 0x10 61 + #define LRADC_CTRL1_TOUCH_DETECT_IRQ_EN BIT(24) 62 + #define LRADC_CTRL1_LRADC_IRQ_EN(n) (1 << ((n) + 16)) 63 + #define LRADC_CTRL1_MX28_LRADC_IRQ_EN_MASK (0x1fff << 16) 64 + #define LRADC_CTRL1_MX23_LRADC_IRQ_EN_MASK (0x01ff << 16) 65 + #define LRADC_CTRL1_LRADC_IRQ_EN_OFFSET 16 66 + #define LRADC_CTRL1_TOUCH_DETECT_IRQ BIT(8) 67 + #define LRADC_CTRL1_LRADC_IRQ(n) BIT(n) 68 + #define LRADC_CTRL1_MX28_LRADC_IRQ_MASK 0x1fff 69 + #define LRADC_CTRL1_MX23_LRADC_IRQ_MASK 0x01ff 70 + #define LRADC_CTRL1_LRADC_IRQ_OFFSET 0 71 + 72 + #define LRADC_CTRL2 0x20 73 + #define LRADC_CTRL2_DIVIDE_BY_TWO_OFFSET 24 74 + #define LRADC_CTRL2_TEMPSENSE_PWD BIT(15) 75 + 76 + #define LRADC_STATUS 0x40 77 + #define LRADC_STATUS_TOUCH_DETECT_RAW BIT(0) 78 + 79 + #define LRADC_CH(n) (0x50 + (0x10 * (n))) 80 + #define LRADC_CH_ACCUMULATE BIT(29) 81 + #define LRADC_CH_NUM_SAMPLES_MASK (0x1f << 24) 82 + #define LRADC_CH_NUM_SAMPLES_OFFSET 24 83 + #define LRADC_CH_NUM_SAMPLES(x) \ 84 + ((x) << LRADC_CH_NUM_SAMPLES_OFFSET) 85 + #define LRADC_CH_VALUE_MASK 0x3ffff 86 + #define LRADC_CH_VALUE_OFFSET 0 87 + 88 + #define LRADC_DELAY(n) (0xd0 + (0x10 * (n))) 89 + #define LRADC_DELAY_TRIGGER_LRADCS_MASK (0xffUL << 24) 90 + #define LRADC_DELAY_TRIGGER_LRADCS_OFFSET 24 91 + #define LRADC_DELAY_TRIGGER(x) \ 92 + (((x) << LRADC_DELAY_TRIGGER_LRADCS_OFFSET) & \ 93 + LRADC_DELAY_TRIGGER_LRADCS_MASK) 94 + #define LRADC_DELAY_KICK BIT(20) 95 + #define LRADC_DELAY_TRIGGER_DELAYS_MASK (0xf << 16) 96 + #define LRADC_DELAY_TRIGGER_DELAYS_OFFSET 16 97 + #define LRADC_DELAY_TRIGGER_DELAYS(x) \ 98 + (((x) << LRADC_DELAY_TRIGGER_DELAYS_OFFSET) & \ 99 + LRADC_DELAY_TRIGGER_DELAYS_MASK) 100 + #define LRADC_DELAY_LOOP_COUNT_MASK (0x1f << 11) 101 + #define LRADC_DELAY_LOOP_COUNT_OFFSET 11 102 + #define LRADC_DELAY_LOOP(x) \ 103 + (((x) << LRADC_DELAY_LOOP_COUNT_OFFSET) & \ 104 + LRADC_DELAY_LOOP_COUNT_MASK) 105 + #define LRADC_DELAY_DELAY_MASK 0x7ff 106 + #define LRADC_DELAY_DELAY_OFFSET 0 107 + #define LRADC_DELAY_DELAY(x) \ 108 + (((x) << LRADC_DELAY_DELAY_OFFSET) & \ 109 + LRADC_DELAY_DELAY_MASK) 110 + 111 + #define LRADC_CTRL4 0x140 112 + #define LRADC_CTRL4_LRADCSELECT_MASK(n) (0xf << ((n) * 4)) 113 + #define LRADC_CTRL4_LRADCSELECT_OFFSET(n) ((n) * 4) 114 + #define LRADC_CTRL4_LRADCSELECT(n, x) \ 115 + (((x) << LRADC_CTRL4_LRADCSELECT_OFFSET(n)) & \ 116 + LRADC_CTRL4_LRADCSELECT_MASK(n)) 117 + 118 + #define LRADC_RESOLUTION 12 119 + #define LRADC_SINGLE_SAMPLE_MASK ((1 << LRADC_RESOLUTION) - 1) 120 + 121 + #define BUFFER_VCHANS_LIMITED 0x3f 122 + #define BUFFER_VCHANS_ALL 0xff 123 + 124 + /* 125 + * Certain LRADC channels are shared between touchscreen 126 + * and/or touch-buttons and generic LRADC block. Therefore when using 127 + * either of these, these channels are not available for the regular 128 + * sampling. The shared channels are as follows: 129 + * 130 + * CH0 -- Touch button #0 131 + * CH1 -- Touch button #1 132 + * CH2 -- Touch screen XPUL 133 + * CH3 -- Touch screen YPLL 134 + * CH4 -- Touch screen XNUL 135 + * CH5 -- Touch screen YNLR 136 + * CH6 -- Touch screen WIPER (5-wire only) 137 + * 138 + * The bit fields below represents which parts of the LRADC block are 139 + * switched into special mode of operation. These channels can not 140 + * be sampled as regular LRADC channels. The driver will refuse any 141 + * attempt to sample these channels. 142 + */ 143 + #define CHAN_MASK_TOUCHBUTTON (BIT(1) | BIT(0)) 144 + #define CHAN_MASK_TOUCHSCREEN_4WIRE (0xf << 2) 145 + #define CHAN_MASK_TOUCHSCREEN_5WIRE (0x1f << 2) 146 + 147 + enum mxs_lradc_id { 148 + IMX23_LRADC, 149 + IMX28_LRADC, 150 + }; 151 + 152 + enum mxs_lradc_ts_wires { 153 + MXS_LRADC_TOUCHSCREEN_NONE = 0, 154 + MXS_LRADC_TOUCHSCREEN_4WIRE, 155 + MXS_LRADC_TOUCHSCREEN_5WIRE, 156 + }; 157 + 158 + /** 159 + * struct mxs_lradc 160 + * @soc: soc type (IMX23 or IMX28) 161 + * @clk: 2 kHz clock for delay units 162 + * @buffer_vchans: channels that can be used during buffered capture 163 + * @touchscreen_wire: touchscreen type (4-wire or 5-wire) 164 + * @use_touchbutton: button state (on or off) 165 + */ 166 + struct mxs_lradc { 167 + enum mxs_lradc_id soc; 168 + struct clk *clk; 169 + u8 buffer_vchans; 170 + 171 + enum mxs_lradc_ts_wires touchscreen_wire; 172 + bool use_touchbutton; 173 + }; 174 + 175 + static inline u32 mxs_lradc_irq_mask(struct mxs_lradc *lradc) 176 + { 177 + switch (lradc->soc) { 178 + case IMX23_LRADC: 179 + return LRADC_CTRL1_MX23_LRADC_IRQ_MASK; 180 + case IMX28_LRADC: 181 + return LRADC_CTRL1_MX28_LRADC_IRQ_MASK; 182 + default: 183 + return 0; 184 + } 185 + } 186 + 187 + #endif /* __MXS_LRADC_H */