Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux

drm/vc4: Make sure to emit a tile coordinates between two MSAA loads.

The HW only executes a load once the tile coordinates packet happens,
and only tracks one at a time, so by emitting our two MSAA loads back
to back we would end up with an undefined color or Z buffer.

Fixes dEQP-EGL.functional.render.multi_context.gles2.rgb888_window

Signed-off-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com>
Cc: Maxime Ripard <maxime.ripard@bootlin.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190206232550.12012-1-eric@anholt.net

+11 -12
+11 -12
drivers/gpu/drm/vc4/vc4_render_cl.c
··· 148 148 } 149 149 150 150 if (setup->zs_read) { 151 + if (setup->color_read) { 152 + /* Exec previous load. */ 153 + vc4_tile_coordinates(setup, x, y); 154 + vc4_store_before_load(setup); 155 + } 156 + 151 157 if (args->zs_read.flags & 152 158 VC4_SUBMIT_RCL_SURFACE_READ_IS_FULL_RES) { 153 159 rcl_u8(setup, VC4_PACKET_LOAD_FULL_RES_TILE_BUFFER); ··· 162 156 &args->zs_read, x, y) | 163 157 VC4_LOADSTORE_FULL_RES_DISABLE_COLOR); 164 158 } else { 165 - if (setup->color_read) { 166 - /* Exec previous load. */ 167 - vc4_tile_coordinates(setup, x, y); 168 - vc4_store_before_load(setup); 169 - } 170 - 171 159 rcl_u8(setup, VC4_PACKET_LOAD_TILE_BUFFER_GENERAL); 172 160 rcl_u16(setup, args->zs_read.bits); 173 161 rcl_u32(setup, setup->zs_read->paddr + ··· 291 291 } 292 292 } 293 293 if (setup->zs_read) { 294 + if (setup->color_read) { 295 + loop_body_size += VC4_PACKET_TILE_COORDINATES_SIZE; 296 + loop_body_size += VC4_PACKET_STORE_TILE_BUFFER_GENERAL_SIZE; 297 + } 298 + 294 299 if (args->zs_read.flags & 295 300 VC4_SUBMIT_RCL_SURFACE_READ_IS_FULL_RES) { 296 301 loop_body_size += VC4_PACKET_LOAD_FULL_RES_TILE_BUFFER_SIZE; 297 302 } else { 298 - if (setup->color_read && 299 - !(args->color_read.flags & 300 - VC4_SUBMIT_RCL_SURFACE_READ_IS_FULL_RES)) { 301 - loop_body_size += VC4_PACKET_TILE_COORDINATES_SIZE; 302 - loop_body_size += VC4_PACKET_STORE_TILE_BUFFER_GENERAL_SIZE; 303 - } 304 303 loop_body_size += VC4_PACKET_LOAD_TILE_BUFFER_GENERAL_SIZE; 305 304 } 306 305 }