tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
clk: rockchip: Add clock and reset driver for RK3506
Add the clock and reset tree definitions for the new
RK3506 SoC.
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Link: https://patch.msgid.link/20251121075350.2564860-3-zhangqing@rock-chips.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
authored by
Elaine Zhang
and committed by
Heiko Stuebner
18191dd7
84898f8e
+1116
+7
drivers/clk/rockchip/Kconfig
+7
drivers/clk/rockchip/Kconfig
···
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help
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Build the driver for RK3399 Clock Driver.
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config CLK_RK3506
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bool "Rockchip RK3506 clock controller support"
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depends on ARM || COMPILE_TEST
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default y
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help
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Build the driver for RK3506 Clock Driver.
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+
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config CLK_RK3528
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bool "Rockchip RK3528 clock controller support"
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depends on ARM64 || COMPILE_TEST
+1
drivers/clk/rockchip/Makefile
+1
drivers/clk/rockchip/Makefile
···
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obj-$(CONFIG_CLK_RK3328) += clk-rk3328.o
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obj-$(CONFIG_CLK_RK3368) += clk-rk3368.o
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obj-$(CONFIG_CLK_RK3399) += clk-rk3399.o
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obj-$(CONFIG_CLK_RK3506) += clk-rk3506.o rst-rk3506.o
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obj-$(CONFIG_CLK_RK3528) += clk-rk3528.o rst-rk3528.o
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obj-$(CONFIG_CLK_RK3562) += clk-rk3562.o rst-rk3562.o
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obj-$(CONFIG_CLK_RK3568) += clk-rk3568.o
+869
drivers/clk/rockchip/clk-rk3506.c
+869
drivers/clk/rockchip/clk-rk3506.c
···
1
+
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 2023-2025 Rockchip Electronics Co., Ltd.
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* Author: Finley Xiao <finley.xiao@rock-chips.com>
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*/
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+
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#include <linux/clk-provider.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/of_address.h>
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#include <linux/platform_device.h>
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#include <linux/syscore_ops.h>
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#include <dt-bindings/clock/rockchip,rk3506-cru.h>
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#include "clk.h"
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+
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#define PVTPLL_SRC_SEL_PVTPLL (BIT(7) | BIT(23))
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+
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enum rk3506_plls {
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gpll, v0pll, v1pll,
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};
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+
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/*
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* [FRAC PLL]: GPLL, V0PLL, V1PLL
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* - VCO Frequency: 950MHz to 3800MHZ
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* - Output Frequency: 19MHz to 3800MHZ
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* - refdiv: 1 to 63 (Int Mode), 1 to 2 (Frac Mode)
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* - fbdiv: 16 to 3800 (Int Mode), 20 to 380 (Frac Mode)
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* - post1div: 1 to 7
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* - post2div: 1 to 7
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*/
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static struct rockchip_pll_rate_table rk3506_pll_rates[] = {
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/* _mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd, _frac */
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RK3036_PLL_RATE(1896000000, 1, 79, 1, 1, 1, 0),
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RK3036_PLL_RATE(1800000000, 1, 75, 1, 1, 1, 0),
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RK3036_PLL_RATE(1704000000, 1, 71, 1, 1, 1, 0),
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RK3036_PLL_RATE(1608000000, 1, 67, 1, 1, 1, 0),
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RK3036_PLL_RATE(1512000000, 1, 63, 1, 1, 1, 0),
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RK3036_PLL_RATE(1416000000, 1, 59, 1, 1, 1, 0),
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RK3036_PLL_RATE(1350000000, 4, 225, 1, 1, 1, 0),
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RK3036_PLL_RATE(1296000000, 1, 54, 1, 1, 1, 0),
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RK3036_PLL_RATE(1200000000, 1, 50, 1, 1, 1, 0),
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RK3036_PLL_RATE(1188000000, 1, 99, 2, 1, 1, 0),
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RK3036_PLL_RATE(1179648000, 1, 49, 1, 1, 0, 2550137),
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RK3036_PLL_RATE(1008000000, 1, 84, 2, 1, 1, 0),
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RK3036_PLL_RATE(1000000000, 3, 125, 1, 1, 1, 0),
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RK3036_PLL_RATE(993484800, 1, 41, 1, 1, 0, 6630355),
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RK3036_PLL_RATE(983040000, 1, 40, 1, 1, 0, 16106127),
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RK3036_PLL_RATE(960000000, 1, 80, 2, 1, 1, 0),
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RK3036_PLL_RATE(912000000, 1, 76, 2, 1, 1, 0),
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RK3036_PLL_RATE(903168000, 1, 75, 2, 1, 0, 4429185),
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RK3036_PLL_RATE(816000000, 1, 68, 2, 1, 1, 0),
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RK3036_PLL_RATE(800000000, 3, 200, 2, 1, 1, 0),
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RK3036_PLL_RATE(600000000, 1, 50, 2, 1, 1, 0),
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RK3036_PLL_RATE(594000000, 2, 99, 2, 1, 1, 0),
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RK3036_PLL_RATE(408000000, 1, 68, 2, 2, 1, 0),
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RK3036_PLL_RATE(312000000, 1, 78, 6, 1, 1, 0),
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RK3036_PLL_RATE(216000000, 1, 72, 4, 2, 1, 0),
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RK3036_PLL_RATE(96000000, 1, 48, 6, 2, 1, 0),
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{ /* sentinel */ },
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};
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+
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#define RK3506_DIV_ACLK_CORE_MASK 0xf
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#define RK3506_DIV_ACLK_CORE_SHIFT 9
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#define RK3506_DIV_PCLK_CORE_MASK 0xf
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#define RK3506_DIV_PCLK_CORE_SHIFT 0
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+
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#define RK3506_CLKSEL15(_aclk_core_div) \
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{ \
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.reg = RK3506_CLKSEL_CON(15), \
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.val = HIWORD_UPDATE(_aclk_core_div, RK3506_DIV_ACLK_CORE_MASK, \
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RK3506_DIV_ACLK_CORE_SHIFT), \
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}
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+
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#define RK3506_CLKSEL16(_pclk_core_div) \
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{ \
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.reg = RK3506_CLKSEL_CON(16), \
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.val = HIWORD_UPDATE(_pclk_core_div, RK3506_DIV_PCLK_CORE_MASK, \
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RK3506_DIV_PCLK_CORE_SHIFT), \
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}
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+
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/* SIGN-OFF: aclk_core: 500M, pclk_core: 125M, */
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#define RK3506_CPUCLK_RATE(_prate, _aclk_core_div, _pclk_core_div) \
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{ \
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.prate = _prate, \
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.divs = { \
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RK3506_CLKSEL15(_aclk_core_div), \
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RK3506_CLKSEL16(_pclk_core_div), \
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}, \
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}
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+
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static struct rockchip_cpuclk_rate_table rk3506_cpuclk_rates[] __initdata = {
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RK3506_CPUCLK_RATE(1608000000, 3, 12),
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RK3506_CPUCLK_RATE(1512000000, 3, 12),
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RK3506_CPUCLK_RATE(1416000000, 2, 11),
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RK3506_CPUCLK_RATE(1296000000, 2, 10),
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RK3506_CPUCLK_RATE(1200000000, 2, 9),
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RK3506_CPUCLK_RATE(1179648000, 2, 9),
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RK3506_CPUCLK_RATE(1008000000, 1, 7),
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RK3506_CPUCLK_RATE(903168000, 1, 7),
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RK3506_CPUCLK_RATE(800000000, 1, 6),
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RK3506_CPUCLK_RATE(750000000, 1, 5),
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RK3506_CPUCLK_RATE(589824000, 1, 4),
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RK3506_CPUCLK_RATE(400000000, 1, 3),
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RK3506_CPUCLK_RATE(200000000, 1, 1),
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};
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+
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PNAME(mux_pll_p) = { "xin24m" };
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PNAME(gpll_v0pll_v1pll_parents_p) = { "gpll", "v0pll", "v1pll" };
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PNAME(gpll_v0pll_v1pll_g_parents_p) = { "clk_gpll_gate", "clk_v0pll_gate", "clk_v1pll_gate" };
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PNAME(gpll_v0pll_v1pll_div_parents_p) = { "clk_gpll_div", "clk_v0pll_div", "clk_v1pll_div" };
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PNAME(xin24m_gpll_v0pll_v1pll_g_parents_p) = { "xin24m", "clk_gpll_gate", "clk_v0pll_gate", "clk_v1pll_gate" };
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PNAME(xin24m_g_gpll_v0pll_v1pll_g_parents_p) = { "xin24m_gate", "clk_gpll_gate", "clk_v0pll_gate", "clk_v1pll_gate" };
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PNAME(xin24m_g_gpll_v0pll_v1pll_div_parents_p) = { "xin24m_gate", "clk_gpll_div", "clk_v0pll_div", "clk_v1pll_div" };
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PNAME(xin24m_400k_32k_parents_p) = { "xin24m", "clk_rc", "clk_32k" };
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PNAME(clk_frac_uart_matrix0_mux_parents_p) = { "xin24m", "gpll", "clk_v0pll_gate", "clk_v1pll_gate" };
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PNAME(clk_timer0_parents_p) = { "xin24m", "clk_gpll_div_100m", "clk_32k", "clk_core_pvtpll", "sai0_mclk_in", "sai0_sclk_in" };
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PNAME(clk_timer1_parents_p) = { "xin24m", "clk_gpll_div_100m", "clk_32k", "clk_core_pvtpll", "sai1_mclk_in", "sai1_sclk_in" };
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PNAME(clk_timer2_parents_p) = { "xin24m", "clk_gpll_div_100m", "clk_32k", "clk_core_pvtpll", "sai2_mclk_in", "sai2_sclk_in" };
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PNAME(clk_timer3_parents_p) = { "xin24m", "clk_gpll_div_100m", "clk_32k", "clk_core_pvtpll", "sai3_mclk_in", "sai3_sclk_in" };
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PNAME(clk_timer4_parents_p) = { "xin24m", "clk_gpll_div_100m", "clk_32k", "clk_core_pvtpll", "mclk_asrc0" };
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PNAME(clk_timer5_parents_p) = { "xin24m", "clk_gpll_div_100m", "clk_32k", "clk_core_pvtpll", "mclk_asrc1" };
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PNAME(sclk_uart_parents_p) = { "xin24m", "clk_gpll_gate", "clk_v0pll_gate", "clk_frac_uart_matrix0", "clk_frac_uart_matrix1",
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"clk_frac_common_matrix0", "clk_frac_common_matrix1", "clk_frac_common_matrix2" };
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PNAME(clk_mac_ptp_root_parents_p) = { "gpll", "v0pll", "v1pll" };
126
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PNAME(clk_pwm_parents_p) = { "clk_rc", "sai0_mclk_in", "sai1_mclk_in", "sai2_mclk_in", "sai3_mclk_in", "sai0_sclk_in", "sai1_sclk_in",
127
+
"sai2_sclk_in", "sai3_sclk_in", "mclk_asrc0", "mclk_asrc1" };
128
+
PNAME(clk_can_parents_p) = { "xin24m", "gpll", "clk_v0pll_gate", "clk_v1pll_gate", "clk_frac_voice_matrix1",
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"clk_frac_common_matrix0", "clk_frac_common_matrix1", "clk_frac_common_matrix2" };
130
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PNAME(clk_pdm_parents_p) = { "xin24m_gate", "clk_int_voice_matrix0", "clk_int_voice_matrix1", "clk_int_voice_matrix2",
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"clk_frac_voice_matrix0", "clk_frac_voice_matrix1", "clk_frac_common_matrix0", "clk_frac_common_matrix1",
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"clk_frac_common_matrix2", "sai0_mclk_in", "sai1_mclk_in", "sai2_mclk_in", "sai3_mclk_in", "clk_gpll_div" };
133
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PNAME(mclk_sai_asrc_parents_p) = { "xin24m_gate", "clk_int_voice_matrix0", "clk_int_voice_matrix1", "clk_int_voice_matrix2",
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"clk_frac_voice_matrix0", "clk_frac_voice_matrix1", "clk_frac_common_matrix0", "clk_frac_common_matrix1",
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"clk_frac_common_matrix2", "sai0_mclk_in", "sai1_mclk_in", "sai2_mclk_in", "sai3_mclk_in" };
136
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PNAME(lrck_asrc_parents_p) = { "mclk_asrc0", "mclk_asrc1", "mclk_asrc2", "mclk_asrc3", "mclk_spdiftx", "clk_spdifrx_to_asrc", "clkout_pdm",
137
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"sai0_fs", "sai1_fs", "sai2_fs", "sai3_fs", "sai4_fs" };
138
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PNAME(cclk_src_sdmmc_parents_p) = { "xin24m_gate", "gpll", "clk_v0pll_gate", "clk_v1pll_gate" };
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PNAME(dclk_vop_parents_p) = { "xin24m_gate", "clk_gpll_gate", "clk_v0pll_gate", "clk_v1pll_gate", "dummy_vop_dclk",
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"dummy_vop_dclk", "dummy_vop_dclk", "dummy_vop_dclk" };
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PNAME(dbclk_gpio0_parents_p) = { "xin24m", "clk_rc", "clk_32k_pmu" };
142
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PNAME(clk_pmu_hp_timer_parents_p) = { "xin24m", "gpll_div_100m", "clk_core_pvtpll" };
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PNAME(clk_ref_out_parents_p) = { "xin24m", "gpll", "v0pll", "v1pll" };
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PNAME(clk_32k_frac_parents_p) = { "xin24m", "v0pll", "v1pll", "clk_rc" };
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PNAME(clk_32k_parents_p) = { "xin32k", "clk_32k_rc", "clk_32k_frac" };
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PNAME(clk_ref_phy_pmu_mux_parents_p) = { "xin24m", "clk_ref_phy_pll" };
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PNAME(clk_vpll_ref_parents_p) = { "xin24m", "clk_pll_ref_io" };
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PNAME(mux_armclk_p) = { "armclk_pll", "clk_core_pvtpll" };
149
+
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#define MFLAGS CLK_MUX_HIWORD_MASK
151
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#define DFLAGS CLK_DIVIDER_HIWORD_MASK
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#define GFLAGS (CLK_GATE_HIWORD_MASK | CLK_GATE_SET_TO_DISABLE)
153
+
154
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static struct rockchip_pll_clock rk3506_pll_clks[] __initdata = {
155
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[gpll] = PLL(pll_rk3328, PLL_GPLL, "gpll", mux_pll_p,
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CLK_IS_CRITICAL, RK3506_PLL_CON(0),
157
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RK3506_MODE_CON, 0, 2, 0, rk3506_pll_rates),
158
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[v0pll] = PLL(pll_rk3328, PLL_V0PLL, "v0pll", mux_pll_p,
159
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CLK_IS_CRITICAL, RK3506_PLL_CON(8),
160
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RK3506_MODE_CON, 2, 0, 0, rk3506_pll_rates),
161
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[v1pll] = PLL(pll_rk3328, PLL_V1PLL, "v1pll", mux_pll_p,
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CLK_IS_CRITICAL, RK3506_PLL_CON(16),
163
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RK3506_MODE_CON, 4, 1, 0, rk3506_pll_rates),
164
+
};
165
+
166
+
static struct rockchip_clk_branch rk3506_armclk __initdata =
167
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MUX(ARMCLK, "armclk", mux_armclk_p, CLK_IS_CRITICAL | CLK_SET_RATE_PARENT,
168
+
RK3506_CLKSEL_CON(15), 8, 1, MFLAGS);
169
+
170
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static struct rockchip_clk_branch rk3506_clk_branches[] __initdata = {
171
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/*
172
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* CRU Clock-Architecture
173
+
*/
174
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/* top */
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GATE(XIN24M_GATE, "xin24m_gate", "xin24m", CLK_IS_CRITICAL,
176
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RK3506_CLKGATE_CON(0), 1, GFLAGS),
177
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GATE(CLK_GPLL_GATE, "clk_gpll_gate", "gpll", CLK_IS_CRITICAL,
178
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RK3506_CLKGATE_CON(0), 2, GFLAGS),
179
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GATE(CLK_V0PLL_GATE, "clk_v0pll_gate", "v0pll", CLK_IS_CRITICAL,
180
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RK3506_CLKGATE_CON(0), 3, GFLAGS),
181
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GATE(CLK_V1PLL_GATE, "clk_v1pll_gate", "v1pll", 0,
182
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RK3506_CLKGATE_CON(0), 4, GFLAGS),
183
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COMPOSITE_NOMUX(CLK_GPLL_DIV, "clk_gpll_div", "clk_gpll_gate", CLK_IS_CRITICAL,
184
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RK3506_CLKSEL_CON(0), 6, 4, DFLAGS,
185
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RK3506_CLKGATE_CON(0), 5, GFLAGS),
186
+
COMPOSITE_NOMUX(CLK_GPLL_DIV_100M, "clk_gpll_div_100m", "clk_gpll_div", 0,
187
+
RK3506_CLKSEL_CON(0), 10, 4, DFLAGS,
188
+
RK3506_CLKGATE_CON(0), 6, GFLAGS),
189
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COMPOSITE_NOMUX(CLK_V0PLL_DIV, "clk_v0pll_div", "clk_v0pll_gate", CLK_IS_CRITICAL,
190
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RK3506_CLKSEL_CON(1), 0, 4, DFLAGS,
191
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RK3506_CLKGATE_CON(0), 7, GFLAGS),
192
+
COMPOSITE_NOMUX(CLK_V1PLL_DIV, "clk_v1pll_div", "clk_v1pll_gate", 0,
193
+
RK3506_CLKSEL_CON(1), 4, 4, DFLAGS,
194
+
RK3506_CLKGATE_CON(0), 8, GFLAGS),
195
+
COMPOSITE_NOMUX(CLK_INT_VOICE_MATRIX0, "clk_int_voice_matrix0", "clk_v0pll_gate", 0,
196
+
RK3506_CLKSEL_CON(1), 8, 5, DFLAGS,
197
+
RK3506_CLKGATE_CON(0), 9, GFLAGS),
198
+
COMPOSITE_NOMUX(CLK_INT_VOICE_MATRIX1, "clk_int_voice_matrix1", "clk_v1pll_gate", 0,
199
+
RK3506_CLKSEL_CON(2), 0, 5, DFLAGS,
200
+
RK3506_CLKGATE_CON(0), 10, GFLAGS),
201
+
COMPOSITE_NOMUX(CLK_INT_VOICE_MATRIX2, "clk_int_voice_matrix2", "clk_v0pll_gate", 0,
202
+
RK3506_CLKSEL_CON(2), 5, 5, DFLAGS,
203
+
RK3506_CLKGATE_CON(0), 11, GFLAGS),
204
+
MUX(CLK_FRAC_UART_MATRIX0_MUX, "clk_frac_uart_matrix0_mux", clk_frac_uart_matrix0_mux_parents_p, 0,
205
+
RK3506_CLKSEL_CON(3), 9, 2, MFLAGS),
206
+
MUX(CLK_FRAC_UART_MATRIX1_MUX, "clk_frac_uart_matrix1_mux", xin24m_gpll_v0pll_v1pll_g_parents_p, 0,
207
+
RK3506_CLKSEL_CON(3), 11, 2, MFLAGS),
208
+
MUX(CLK_FRAC_VOICE_MATRIX0_MUX, "clk_frac_voice_matrix0_mux", xin24m_g_gpll_v0pll_v1pll_g_parents_p, 0,
209
+
RK3506_CLKSEL_CON(3), 13, 2, MFLAGS),
210
+
MUX(CLK_FRAC_VOICE_MATRIX1_MUX, "clk_frac_voice_matrix1_mux", xin24m_g_gpll_v0pll_v1pll_g_parents_p, 0,
211
+
RK3506_CLKSEL_CON(4), 0, 2, MFLAGS),
212
+
MUX(CLK_FRAC_COMMON_MATRIX0_MUX, "clk_frac_common_matrix0_mux", xin24m_gpll_v0pll_v1pll_g_parents_p, 0,
213
+
RK3506_CLKSEL_CON(4), 2, 2, MFLAGS),
214
+
MUX(CLK_FRAC_COMMON_MATRIX1_MUX, "clk_frac_common_matrix1_mux", xin24m_g_gpll_v0pll_v1pll_g_parents_p, 0,
215
+
RK3506_CLKSEL_CON(4), 4, 2, MFLAGS),
216
+
MUX(CLK_FRAC_COMMON_MATRIX2_MUX, "clk_frac_common_matrix2_mux", xin24m_g_gpll_v0pll_v1pll_g_parents_p, 0,
217
+
RK3506_CLKSEL_CON(4), 6, 2, MFLAGS),
218
+
COMPOSITE_FRAC(CLK_FRAC_UART_MATRIX0, "clk_frac_uart_matrix0", "clk_frac_uart_matrix0_mux", 0,
219
+
RK3506_CLKSEL_CON(5), 0,
220
+
RK3506_CLKGATE_CON(0), 13, GFLAGS),
221
+
COMPOSITE_FRAC(CLK_FRAC_UART_MATRIX1, "clk_frac_uart_matrix1", "clk_frac_uart_matrix1_mux", 0,
222
+
RK3506_CLKSEL_CON(6), 0,
223
+
RK3506_CLKGATE_CON(0), 14, GFLAGS),
224
+
COMPOSITE_FRAC(CLK_FRAC_VOICE_MATRIX0, "clk_frac_voice_matrix0", "clk_frac_voice_matrix0_mux", 0,
225
+
RK3506_CLKSEL_CON(7), 0,
226
+
RK3506_CLKGATE_CON(0), 15, GFLAGS),
227
+
COMPOSITE_FRAC(CLK_FRAC_VOICE_MATRIX1, "clk_frac_voice_matrix1", "clk_frac_voice_matrix1_mux", 0,
228
+
RK3506_CLKSEL_CON(9), 0,
229
+
RK3506_CLKGATE_CON(1), 0, GFLAGS),
230
+
COMPOSITE_FRAC(CLK_FRAC_COMMON_MATRIX0, "clk_frac_common_matrix0", "clk_frac_common_matrix0_mux", 0,
231
+
RK3506_CLKSEL_CON(11), 0,
232
+
RK3506_CLKGATE_CON(1), 1, GFLAGS),
233
+
COMPOSITE_FRAC(CLK_FRAC_COMMON_MATRIX1, "clk_frac_common_matrix1", "clk_frac_common_matrix1_mux", 0,
234
+
RK3506_CLKSEL_CON(12), 0,
235
+
RK3506_CLKGATE_CON(1), 2, GFLAGS),
236
+
COMPOSITE_FRAC(CLK_FRAC_COMMON_MATRIX2, "clk_frac_common_matrix2", "clk_frac_common_matrix2_mux", 0,
237
+
RK3506_CLKSEL_CON(13), 0,
238
+
RK3506_CLKGATE_CON(1), 3, GFLAGS),
239
+
GATE(CLK_REF_USBPHY_TOP, "clk_ref_usbphy_top", "xin24m", 0,
240
+
RK3506_CLKGATE_CON(1), 4, GFLAGS),
241
+
GATE(CLK_REF_DPHY_TOP, "clk_ref_dphy_top", "xin24m", 0,
242
+
RK3506_CLKGATE_CON(1), 5, GFLAGS),
243
+
244
+
/* core */
245
+
COMPOSITE_NOGATE(0, "armclk_pll", gpll_v0pll_v1pll_parents_p, CLK_IS_CRITICAL,
246
+
RK3506_CLKSEL_CON(15), 5, 2, MFLAGS, 0, 5, DFLAGS),
247
+
COMPOSITE_NOMUX(ACLK_CORE_ROOT, "aclk_core_root", "armclk", CLK_IGNORE_UNUSED,
248
+
RK3506_CLKSEL_CON(15), 9, 4, DFLAGS | CLK_DIVIDER_READ_ONLY,
249
+
RK3506_CLKGATE_CON(2), 11, GFLAGS),
250
+
COMPOSITE_NOMUX(PCLK_CORE_ROOT, "pclk_core_root", "armclk", CLK_IGNORE_UNUSED,
251
+
RK3506_CLKSEL_CON(16), 0, 4, DFLAGS | CLK_DIVIDER_READ_ONLY,
252
+
RK3506_CLKGATE_CON(2), 12, GFLAGS),
253
+
GATE(PCLK_DBG, "pclk_dbg", "pclk_core_root", CLK_IGNORE_UNUSED,
254
+
RK3506_CLKGATE_CON(3), 1, GFLAGS),
255
+
GATE(PCLK_CORE_GRF, "pclk_core_grf", "pclk_core_root", CLK_IGNORE_UNUSED,
256
+
RK3506_CLKGATE_CON(3), 4, GFLAGS),
257
+
GATE(PCLK_CORE_CRU, "pclk_core_cru", "pclk_core_root", CLK_IGNORE_UNUSED,
258
+
RK3506_CLKGATE_CON(3), 5, GFLAGS),
259
+
GATE(CLK_CORE_EMA_DETECT, "clk_core_ema_detect", "xin24m_gate", CLK_IGNORE_UNUSED,
260
+
RK3506_CLKGATE_CON(3), 6, GFLAGS),
261
+
GATE(PCLK_GPIO1, "pclk_gpio1", "aclk_core_root", 0,
262
+
RK3506_CLKGATE_CON(3), 8, GFLAGS),
263
+
GATE(DBCLK_GPIO1, "dbclk_gpio1", "xin24m_gate", 0,
264
+
RK3506_CLKGATE_CON(3), 9, GFLAGS),
265
+
266
+
/* core peri */
267
+
COMPOSITE(ACLK_CORE_PERI_ROOT, "aclk_core_peri_root", gpll_v0pll_v1pll_g_parents_p, 0,
268
+
RK3506_CLKSEL_CON(18), 5, 2, MFLAGS, 0, 5, DFLAGS,
269
+
RK3506_CLKGATE_CON(4), 0, GFLAGS),
270
+
GATE(HCLK_CORE_PERI_ROOT, "hclk_core_peri_root", "aclk_core_peri_root", 0,
271
+
RK3506_CLKGATE_CON(4), 1, GFLAGS),
272
+
GATE(PCLK_CORE_PERI_ROOT, "pclk_core_peri_root", "aclk_core_peri_root", 0,
273
+
RK3506_CLKGATE_CON(4), 2, GFLAGS),
274
+
COMPOSITE(CLK_DSMC, "clk_dsmc", xin24m_gpll_v0pll_v1pll_g_parents_p, 0,
275
+
RK3506_CLKSEL_CON(18), 12, 2, MFLAGS, 7, 5, DFLAGS,
276
+
RK3506_CLKGATE_CON(4), 4, GFLAGS),
277
+
GATE(ACLK_DSMC, "aclk_dsmc", "aclk_core_peri_root", 0,
278
+
RK3506_CLKGATE_CON(4), 5, GFLAGS),
279
+
GATE(PCLK_DSMC, "pclk_dsmc", "pclk_core_peri_root", 0,
280
+
RK3506_CLKGATE_CON(4), 6, GFLAGS),
281
+
COMPOSITE(CLK_FLEXBUS_TX, "clk_flexbus_tx", xin24m_gpll_v0pll_v1pll_g_parents_p, 0,
282
+
RK3506_CLKSEL_CON(19), 5, 2, MFLAGS, 0, 5, DFLAGS,
283
+
RK3506_CLKGATE_CON(4), 7, GFLAGS),
284
+
COMPOSITE(CLK_FLEXBUS_RX, "clk_flexbus_rx", xin24m_gpll_v0pll_v1pll_g_parents_p, 0,
285
+
RK3506_CLKSEL_CON(19), 12, 2, MFLAGS, 7, 5, DFLAGS,
286
+
RK3506_CLKGATE_CON(4), 8, GFLAGS),
287
+
GATE(ACLK_FLEXBUS, "aclk_flexbus", "aclk_core_peri_root", 0,
288
+
RK3506_CLKGATE_CON(4), 9, GFLAGS),
289
+
GATE(HCLK_FLEXBUS, "hclk_flexbus", "hclk_core_peri_root", 0,
290
+
RK3506_CLKGATE_CON(4), 10, GFLAGS),
291
+
GATE(ACLK_DSMC_SLV, "aclk_dsmc_slv", "aclk_core_peri_root", 0,
292
+
RK3506_CLKGATE_CON(4), 11, GFLAGS),
293
+
GATE(HCLK_DSMC_SLV, "hclk_dsmc_slv", "hclk_core_peri_root", 0,
294
+
RK3506_CLKGATE_CON(4), 12, GFLAGS),
295
+
296
+
/* bus */
297
+
COMPOSITE(ACLK_BUS_ROOT, "aclk_bus_root", gpll_v0pll_v1pll_div_parents_p, CLK_IS_CRITICAL,
298
+
RK3506_CLKSEL_CON(21), 5, 2, MFLAGS, 0, 5, DFLAGS,
299
+
RK3506_CLKGATE_CON(5), 0, GFLAGS),
300
+
COMPOSITE(HCLK_BUS_ROOT, "hclk_bus_root", gpll_v0pll_v1pll_div_parents_p, CLK_IS_CRITICAL,
301
+
RK3506_CLKSEL_CON(21), 12, 2, MFLAGS, 7, 5, DFLAGS,
302
+
RK3506_CLKGATE_CON(5), 1, GFLAGS),
303
+
COMPOSITE(PCLK_BUS_ROOT, "pclk_bus_root", gpll_v0pll_v1pll_div_parents_p, CLK_IS_CRITICAL,
304
+
RK3506_CLKSEL_CON(22), 5, 2, MFLAGS, 0, 5, DFLAGS,
305
+
RK3506_CLKGATE_CON(5), 2, GFLAGS),
306
+
GATE(ACLK_SYSRAM, "aclk_sysram", "aclk_bus_root", CLK_IGNORE_UNUSED,
307
+
RK3506_CLKGATE_CON(5), 6, GFLAGS),
308
+
GATE(HCLK_SYSRAM, "hclk_sysram", "aclk_bus_root", CLK_IGNORE_UNUSED,
309
+
RK3506_CLKGATE_CON(5), 7, GFLAGS),
310
+
GATE(ACLK_DMAC0, "aclk_dmac0", "aclk_bus_root", 0,
311
+
RK3506_CLKGATE_CON(5), 8, GFLAGS),
312
+
GATE(ACLK_DMAC1, "aclk_dmac1", "aclk_bus_root", 0,
313
+
RK3506_CLKGATE_CON(5), 9, GFLAGS),
314
+
GATE(HCLK_M0, "hclk_m0", "aclk_bus_root", 0,
315
+
RK3506_CLKGATE_CON(5), 10, GFLAGS),
316
+
GATE(ACLK_CRYPTO_NS, "aclk_crypto_ns", "aclk_bus_root", 0,
317
+
RK3506_CLKGATE_CON(5), 14, GFLAGS),
318
+
GATE(HCLK_CRYPTO_NS, "hclk_crypto_ns", "hclk_bus_root", 0,
319
+
RK3506_CLKGATE_CON(5), 15, GFLAGS),
320
+
GATE(HCLK_RNG, "hclk_rng", "hclk_bus_root", 0,
321
+
RK3506_CLKGATE_CON(6), 0, GFLAGS),
322
+
GATE(PCLK_BUS_GRF, "pclk_bus_grf", "pclk_bus_root", CLK_IGNORE_UNUSED,
323
+
RK3506_CLKGATE_CON(6), 1, GFLAGS),
324
+
GATE(PCLK_TIMER, "pclk_timer", "pclk_bus_root", 0,
325
+
RK3506_CLKGATE_CON(6), 2, GFLAGS),
326
+
COMPOSITE_NODIV(CLK_TIMER0_CH0, "clk_timer0_ch0", clk_timer0_parents_p, 0,
327
+
RK3506_CLKSEL_CON(22), 7, 3, MFLAGS,
328
+
RK3506_CLKGATE_CON(6), 3, GFLAGS),
329
+
COMPOSITE_NODIV(CLK_TIMER0_CH1, "clk_timer0_ch1", clk_timer1_parents_p, 0,
330
+
RK3506_CLKSEL_CON(22), 10, 3, MFLAGS,
331
+
RK3506_CLKGATE_CON(6), 4, GFLAGS),
332
+
COMPOSITE_NODIV(CLK_TIMER0_CH2, "clk_timer0_ch2", clk_timer2_parents_p, 0,
333
+
RK3506_CLKSEL_CON(22), 13, 3, MFLAGS,
334
+
RK3506_CLKGATE_CON(6), 5, GFLAGS),
335
+
COMPOSITE_NODIV(CLK_TIMER0_CH3, "clk_timer0_ch3", clk_timer3_parents_p, 0,
336
+
RK3506_CLKSEL_CON(23), 0, 3, MFLAGS,
337
+
RK3506_CLKGATE_CON(6), 6, GFLAGS),
338
+
COMPOSITE_NODIV(CLK_TIMER0_CH4, "clk_timer0_ch4", clk_timer4_parents_p, 0,
339
+
RK3506_CLKSEL_CON(23), 3, 3, MFLAGS,
340
+
RK3506_CLKGATE_CON(6), 7, GFLAGS),
341
+
COMPOSITE_NODIV(CLK_TIMER0_CH5, "clk_timer0_ch5", clk_timer5_parents_p, 0,
342
+
RK3506_CLKSEL_CON(23), 6, 3, MFLAGS,
343
+
RK3506_CLKGATE_CON(6), 8, GFLAGS),
344
+
GATE(PCLK_WDT0, "pclk_wdt0", "pclk_bus_root", 0,
345
+
RK3506_CLKGATE_CON(6), 9, GFLAGS),
346
+
GATE(TCLK_WDT0, "tclk_wdt0", "xin24m_gate", 0,
347
+
RK3506_CLKGATE_CON(6), 10, GFLAGS),
348
+
GATE(PCLK_WDT1, "pclk_wdt1", "pclk_bus_root", 0,
349
+
RK3506_CLKGATE_CON(6), 11, GFLAGS),
350
+
GATE(TCLK_WDT1, "tclk_wdt1", "xin24m_gate", 0,
351
+
RK3506_CLKGATE_CON(6), 12, GFLAGS),
352
+
GATE(PCLK_MAILBOX, "pclk_mailbox", "pclk_bus_root", 0,
353
+
RK3506_CLKGATE_CON(6), 13, GFLAGS),
354
+
GATE(PCLK_INTMUX, "pclk_intmux", "pclk_bus_root", 0,
355
+
RK3506_CLKGATE_CON(6), 14, GFLAGS),
356
+
GATE(PCLK_SPINLOCK, "pclk_spinlock", "pclk_bus_root", 0,
357
+
RK3506_CLKGATE_CON(6), 15, GFLAGS),
358
+
GATE(PCLK_DDRC, "pclk_ddrc", "pclk_bus_root", CLK_IGNORE_UNUSED,
359
+
RK3506_CLKGATE_CON(7), 0, GFLAGS),
360
+
GATE(HCLK_DDRPHY, "hclk_ddrphy", "hclk_bus_root", CLK_IGNORE_UNUSED,
361
+
RK3506_CLKGATE_CON(7), 1, GFLAGS),
362
+
GATE(PCLK_DDRMON, "pclk_ddrmon", "pclk_bus_root", CLK_IGNORE_UNUSED,
363
+
RK3506_CLKGATE_CON(7), 2, GFLAGS),
364
+
GATE(CLK_DDRMON_OSC, "clk_ddrmon_osc", "xin24m_gate", CLK_IGNORE_UNUSED,
365
+
RK3506_CLKGATE_CON(7), 3, GFLAGS),
366
+
GATE(PCLK_STDBY, "pclk_stdby", "pclk_bus_root", CLK_IGNORE_UNUSED,
367
+
RK3506_CLKGATE_CON(7), 4, GFLAGS),
368
+
GATE(HCLK_USBOTG0, "hclk_usbotg0", "hclk_bus_root", 0,
369
+
RK3506_CLKGATE_CON(7), 5, GFLAGS),
370
+
GATE(HCLK_USBOTG0_PMU, "hclk_usbotg0_pmu", "hclk_bus_root", 0,
371
+
RK3506_CLKGATE_CON(7), 6, GFLAGS),
372
+
GATE(CLK_USBOTG0_ADP, "clk_usbotg0_adp", "clk_32k", 0,
373
+
RK3506_CLKGATE_CON(7), 7, GFLAGS),
374
+
GATE(HCLK_USBOTG1, "hclk_usbotg1", "hclk_bus_root", 0,
375
+
RK3506_CLKGATE_CON(7), 8, GFLAGS),
376
+
GATE(HCLK_USBOTG1_PMU, "hclk_usbotg1_pmu", "hclk_bus_root", 0,
377
+
RK3506_CLKGATE_CON(7), 9, GFLAGS),
378
+
GATE(CLK_USBOTG1_ADP, "clk_usbotg1_adp", "clk_32k", 0,
379
+
RK3506_CLKGATE_CON(7), 10, GFLAGS),
380
+
GATE(PCLK_USBPHY, "pclk_usbphy", "pclk_bus_root", 0,
381
+
RK3506_CLKGATE_CON(7), 11, GFLAGS),
382
+
GATE(ACLK_DMA2DDR, "aclk_dma2ddr", "aclk_bus_root", CLK_IGNORE_UNUSED,
383
+
RK3506_CLKGATE_CON(8), 0, GFLAGS),
384
+
GATE(PCLK_DMA2DDR, "pclk_dma2ddr", "pclk_bus_root", CLK_IGNORE_UNUSED,
385
+
RK3506_CLKGATE_CON(8), 1, GFLAGS),
386
+
COMPOSITE_NOMUX(STCLK_M0, "stclk_m0", "xin24m_gate", 0,
387
+
RK3506_CLKSEL_CON(23), 9, 6, DFLAGS,
388
+
RK3506_CLKGATE_CON(8), 2, GFLAGS),
389
+
COMPOSITE(CLK_DDRPHY, "clk_ddrphy", gpll_v0pll_v1pll_parents_p, CLK_IGNORE_UNUSED,
390
+
RK3506_PMU_CLKSEL_CON(4), 4, 2, MFLAGS, 0, 4, DFLAGS,
391
+
RK3506_PMU_CLKGATE_CON(1), 10, GFLAGS),
392
+
FACTOR(CLK_DDRC_SRC, "clk_ddrc_src", "clk_ddrphy", 0, 1, 4),
393
+
GATE(ACLK_DDRC_0, "aclk_ddrc_0", "clk_ddrc_src", CLK_IGNORE_UNUSED,
394
+
RK3506_CLKGATE_CON(10), 0, GFLAGS),
395
+
GATE(ACLK_DDRC_1, "aclk_ddrc_1", "clk_ddrc_src", CLK_IGNORE_UNUSED,
396
+
RK3506_CLKGATE_CON(10), 1, GFLAGS),
397
+
GATE(CLK_DDRC, "clk_ddrc", "clk_ddrc_src", CLK_IS_CRITICAL,
398
+
RK3506_CLKGATE_CON(10), 3, GFLAGS),
399
+
GATE(CLK_DDRMON, "clk_ddrmon", "clk_ddrc_src", CLK_IGNORE_UNUSED,
400
+
RK3506_CLKGATE_CON(10), 4, GFLAGS),
401
+
402
+
/* ls peri */
403
+
COMPOSITE(HCLK_LSPERI_ROOT, "hclk_lsperi_root", gpll_v0pll_v1pll_div_parents_p, 0,
404
+
RK3506_CLKSEL_CON(29), 5, 2, MFLAGS, 0, 5, DFLAGS,
405
+
RK3506_CLKGATE_CON(11), 0, GFLAGS),
406
+
GATE(PCLK_LSPERI_ROOT, "pclk_lsperi_root", "hclk_lsperi_root", 0,
407
+
RK3506_CLKGATE_CON(11), 1, GFLAGS),
408
+
GATE(PCLK_UART0, "pclk_uart0", "pclk_lsperi_root", 0,
409
+
RK3506_CLKGATE_CON(11), 4, GFLAGS),
410
+
GATE(PCLK_UART1, "pclk_uart1", "pclk_lsperi_root", 0,
411
+
RK3506_CLKGATE_CON(11), 5, GFLAGS),
412
+
GATE(PCLK_UART2, "pclk_uart2", "pclk_lsperi_root", 0,
413
+
RK3506_CLKGATE_CON(11), 6, GFLAGS),
414
+
GATE(PCLK_UART3, "pclk_uart3", "pclk_lsperi_root", 0,
415
+
RK3506_CLKGATE_CON(11), 7, GFLAGS),
416
+
GATE(PCLK_UART4, "pclk_uart4", "pclk_lsperi_root", 0,
417
+
RK3506_CLKGATE_CON(11), 8, GFLAGS),
418
+
COMPOSITE(SCLK_UART0, "sclk_uart0", sclk_uart_parents_p, 0,
419
+
RK3506_CLKSEL_CON(29), 12, 3, MFLAGS, 7, 5, DFLAGS,
420
+
RK3506_CLKGATE_CON(11), 9, GFLAGS),
421
+
COMPOSITE(SCLK_UART1, "sclk_uart1", sclk_uart_parents_p, 0,
422
+
RK3506_CLKSEL_CON(30), 5, 3, MFLAGS, 0, 5, DFLAGS,
423
+
RK3506_CLKGATE_CON(11), 10, GFLAGS),
424
+
COMPOSITE(SCLK_UART2, "sclk_uart2", sclk_uart_parents_p, 0,
425
+
RK3506_CLKSEL_CON(30), 13, 3, MFLAGS, 8, 5, DFLAGS,
426
+
RK3506_CLKGATE_CON(11), 11, GFLAGS),
427
+
COMPOSITE(SCLK_UART3, "sclk_uart3", sclk_uart_parents_p, 0,
428
+
RK3506_CLKSEL_CON(31), 5, 3, MFLAGS, 0, 5, DFLAGS,
429
+
RK3506_CLKGATE_CON(11), 12, GFLAGS),
430
+
COMPOSITE(SCLK_UART4, "sclk_uart4", sclk_uart_parents_p, 0,
431
+
RK3506_CLKSEL_CON(31), 13, 3, MFLAGS, 8, 5, DFLAGS,
432
+
RK3506_CLKGATE_CON(11), 13, GFLAGS),
433
+
GATE(PCLK_I2C0, "pclk_i2c0", "pclk_lsperi_root", 0,
434
+
RK3506_CLKGATE_CON(11), 14, GFLAGS),
435
+
COMPOSITE(CLK_I2C0, "clk_i2c0", xin24m_g_gpll_v0pll_v1pll_div_parents_p, 0,
436
+
RK3506_CLKSEL_CON(32), 4, 2, MFLAGS, 0, 4, DFLAGS,
437
+
RK3506_CLKGATE_CON(11), 15, GFLAGS),
438
+
GATE(PCLK_I2C1, "pclk_i2c1", "pclk_lsperi_root", 0,
439
+
RK3506_CLKGATE_CON(12), 0, GFLAGS),
440
+
COMPOSITE(CLK_I2C1, "clk_i2c1", xin24m_g_gpll_v0pll_v1pll_div_parents_p, 0,
441
+
RK3506_CLKSEL_CON(32), 10, 2, MFLAGS, 6, 4, DFLAGS,
442
+
RK3506_CLKGATE_CON(12), 1, GFLAGS),
443
+
GATE(PCLK_I2C2, "pclk_i2c2", "pclk_lsperi_root", 0,
444
+
RK3506_CLKGATE_CON(12), 2, GFLAGS),
445
+
COMPOSITE(CLK_I2C2, "clk_i2c2", xin24m_g_gpll_v0pll_v1pll_div_parents_p, 0,
446
+
RK3506_CLKSEL_CON(33), 4, 2, MFLAGS, 0, 4, DFLAGS,
447
+
RK3506_CLKGATE_CON(12), 3, GFLAGS),
448
+
GATE(PCLK_PWM1, "pclk_pwm1", "pclk_lsperi_root", 0,
449
+
RK3506_CLKGATE_CON(12), 4, GFLAGS),
450
+
COMPOSITE(CLK_PWM1, "clk_pwm1", gpll_v0pll_v1pll_div_parents_p, 0,
451
+
RK3506_CLKSEL_CON(33), 10, 2, MFLAGS, 6, 4, DFLAGS,
452
+
RK3506_CLKGATE_CON(12), 5, GFLAGS),
453
+
GATE(CLK_OSC_PWM1, "clk_osc_pwm1", "xin24m", 0,
454
+
RK3506_CLKGATE_CON(12), 6, GFLAGS),
455
+
GATE(CLK_RC_PWM1, "clk_rc_pwm1", "clk_rc", 0,
456
+
RK3506_CLKGATE_CON(12), 7, GFLAGS),
457
+
COMPOSITE_NODIV(CLK_FREQ_PWM1, "clk_freq_pwm1", clk_pwm_parents_p, 0,
458
+
RK3506_CLKSEL_CON(33), 12, 4, MFLAGS,
459
+
RK3506_CLKGATE_CON(12), 8, GFLAGS),
460
+
COMPOSITE_NODIV(CLK_COUNTER_PWM1, "clk_counter_pwm1", clk_pwm_parents_p, 0,
461
+
RK3506_CLKSEL_CON(34), 0, 4, MFLAGS,
462
+
RK3506_CLKGATE_CON(12), 9, GFLAGS),
463
+
GATE(PCLK_SPI0, "pclk_spi0", "pclk_lsperi_root", 0,
464
+
RK3506_CLKGATE_CON(12), 10, GFLAGS),
465
+
COMPOSITE(CLK_SPI0, "clk_spi0", xin24m_g_gpll_v0pll_v1pll_div_parents_p, 0,
466
+
RK3506_CLKSEL_CON(34), 8, 2, MFLAGS, 4, 4, DFLAGS,
467
+
RK3506_CLKGATE_CON(12), 11, GFLAGS),
468
+
GATE(PCLK_SPI1, "pclk_spi1", "pclk_lsperi_root", 0,
469
+
RK3506_CLKGATE_CON(12), 12, GFLAGS),
470
+
COMPOSITE(CLK_SPI1, "clk_spi1", xin24m_g_gpll_v0pll_v1pll_div_parents_p, 0,
471
+
RK3506_CLKSEL_CON(34), 14, 2, MFLAGS, 10, 4, DFLAGS,
472
+
RK3506_CLKGATE_CON(12), 13, GFLAGS),
473
+
GATE(PCLK_GPIO2, "pclk_gpio2", "pclk_lsperi_root", 0,
474
+
RK3506_CLKGATE_CON(12), 14, GFLAGS),
475
+
COMPOSITE_NODIV(DBCLK_GPIO2, "dbclk_gpio2", xin24m_400k_32k_parents_p, 0,
476
+
RK3506_CLKSEL_CON(35), 0, 2, MFLAGS,
477
+
RK3506_CLKGATE_CON(12), 15, GFLAGS),
478
+
GATE(PCLK_GPIO3, "pclk_gpio3", "pclk_lsperi_root", 0,
479
+
RK3506_CLKGATE_CON(13), 0, GFLAGS),
480
+
COMPOSITE_NODIV(DBCLK_GPIO3, "dbclk_gpio3", xin24m_400k_32k_parents_p, 0,
481
+
RK3506_CLKSEL_CON(35), 2, 2, MFLAGS,
482
+
RK3506_CLKGATE_CON(13), 1, GFLAGS),
483
+
GATE(PCLK_GPIO4, "pclk_gpio4", "pclk_lsperi_root", 0,
484
+
RK3506_CLKGATE_CON(13), 2, GFLAGS),
485
+
COMPOSITE_NODIV(DBCLK_GPIO4, "dbclk_gpio4", xin24m_400k_32k_parents_p, 0,
486
+
RK3506_CLKSEL_CON(35), 4, 2, MFLAGS,
487
+
RK3506_CLKGATE_CON(13), 3, GFLAGS),
488
+
GATE(HCLK_CAN0, "hclk_can0", "hclk_lsperi_root", 0,
489
+
RK3506_CLKGATE_CON(13), 4, GFLAGS),
490
+
COMPOSITE(CLK_CAN0, "clk_can0", clk_can_parents_p, 0,
491
+
RK3506_CLKSEL_CON(35), 11, 3, MFLAGS, 6, 5, DFLAGS,
492
+
RK3506_CLKGATE_CON(13), 5, GFLAGS),
493
+
GATE(HCLK_CAN1, "hclk_can1", "hclk_lsperi_root", 0,
494
+
RK3506_CLKGATE_CON(13), 6, GFLAGS),
495
+
COMPOSITE(CLK_CAN1, "clk_can1", clk_can_parents_p, 0,
496
+
RK3506_CLKSEL_CON(36), 5, 3, MFLAGS, 0, 5, DFLAGS,
497
+
RK3506_CLKGATE_CON(13), 7, GFLAGS),
498
+
GATE(HCLK_PDM, "hclk_pdm", "hclk_lsperi_root", 0,
499
+
RK3506_CLKGATE_CON(13), 8, GFLAGS),
500
+
COMPOSITE(MCLK_PDM, "mclk_pdm", clk_pdm_parents_p, 0,
501
+
RK3506_CLKSEL_CON(37), 5, 4, MFLAGS, 0, 5, DFLAGS,
502
+
RK3506_CLKGATE_CON(13), 9, GFLAGS),
503
+
COMPOSITE(CLKOUT_PDM, "clkout_pdm", clk_pdm_parents_p, 0,
504
+
RK3506_CLKSEL_CON(38), 10, 4, MFLAGS, 0, 10, DFLAGS,
505
+
RK3506_CLKGATE_CON(13), 10, GFLAGS),
506
+
COMPOSITE(MCLK_SPDIFTX, "mclk_spdiftx", mclk_sai_asrc_parents_p, 0,
507
+
RK3506_CLKSEL_CON(39), 5, 4, MFLAGS, 0, 5, DFLAGS,
508
+
RK3506_CLKGATE_CON(13), 11, GFLAGS),
509
+
GATE(HCLK_SPDIFTX, "hclk_spdiftx", "hclk_lsperi_root", 0,
510
+
RK3506_CLKGATE_CON(13), 12, GFLAGS),
511
+
GATE(HCLK_SPDIFRX, "hclk_spdifrx", "hclk_lsperi_root", 0,
512
+
RK3506_CLKGATE_CON(13), 13, GFLAGS),
513
+
COMPOSITE(MCLK_SPDIFRX, "mclk_spdifrx", gpll_v0pll_v1pll_g_parents_p, 0,
514
+
RK3506_CLKSEL_CON(39), 14, 2, MFLAGS, 9, 5, DFLAGS,
515
+
RK3506_CLKGATE_CON(13), 14, GFLAGS),
516
+
COMPOSITE(MCLK_SAI0, "mclk_sai0", mclk_sai_asrc_parents_p, 0,
517
+
RK3506_CLKSEL_CON(40), 8, 4, MFLAGS, 0, 8, DFLAGS,
518
+
RK3506_CLKGATE_CON(13), 15, GFLAGS),
519
+
GATE(HCLK_SAI0, "hclk_sai0", "hclk_lsperi_root", 0,
520
+
RK3506_CLKGATE_CON(14), 0, GFLAGS),
521
+
GATE(MCLK_OUT_SAI0, "mclk_out_sai0", "mclk_sai0", 0,
522
+
RK3506_CLKGATE_CON(14), 1, GFLAGS),
523
+
COMPOSITE(MCLK_SAI1, "mclk_sai1", mclk_sai_asrc_parents_p, 0,
524
+
RK3506_CLKSEL_CON(41), 8, 4, MFLAGS, 0, 8, DFLAGS,
525
+
RK3506_CLKGATE_CON(14), 2, GFLAGS),
526
+
GATE(HCLK_SAI1, "hclk_sai1", "hclk_lsperi_root", 0,
527
+
RK3506_CLKGATE_CON(14), 3, GFLAGS),
528
+
GATE(MCLK_OUT_SAI1, "mclk_out_sai1", "mclk_sai1", 0,
529
+
RK3506_CLKGATE_CON(14), 4, GFLAGS),
530
+
GATE(HCLK_ASRC0, "hclk_asrc0", "hclk_lsperi_root", 0,
531
+
RK3506_CLKGATE_CON(14), 5, GFLAGS),
532
+
COMPOSITE(CLK_ASRC0, "clk_asrc0", gpll_v0pll_v1pll_g_parents_p, 0,
533
+
RK3506_CLKSEL_CON(42), 5, 2, MFLAGS, 0, 5, DFLAGS,
534
+
RK3506_CLKGATE_CON(14), 6, GFLAGS),
535
+
GATE(HCLK_ASRC1, "hclk_asrc1", "hclk_lsperi_root", 0,
536
+
RK3506_CLKGATE_CON(14), 7, GFLAGS),
537
+
COMPOSITE(CLK_ASRC1, "clk_asrc1", gpll_v0pll_v1pll_g_parents_p, 0,
538
+
RK3506_CLKSEL_CON(42), 12, 2, MFLAGS, 7, 5, DFLAGS,
539
+
RK3506_CLKGATE_CON(14), 8, GFLAGS),
540
+
GATE(PCLK_CRU, "pclk_cru", "pclk_lsperi_root", CLK_IS_CRITICAL,
541
+
RK3506_CLKGATE_CON(14), 9, GFLAGS),
542
+
GATE(PCLK_PMU_ROOT, "pclk_pmu_root", "pclk_lsperi_root", CLK_IS_CRITICAL,
543
+
RK3506_CLKGATE_CON(14), 10, GFLAGS),
544
+
COMPOSITE_NODIV(MCLK_ASRC0, "mclk_asrc0", mclk_sai_asrc_parents_p, 0,
545
+
RK3506_CLKSEL_CON(46), 0, 4, MFLAGS,
546
+
RK3506_CLKGATE_CON(16), 0, GFLAGS),
547
+
COMPOSITE_NODIV(MCLK_ASRC1, "mclk_asrc1", mclk_sai_asrc_parents_p, 0,
548
+
RK3506_CLKSEL_CON(46), 4, 4, MFLAGS,
549
+
RK3506_CLKGATE_CON(16), 1, GFLAGS),
550
+
COMPOSITE_NODIV(MCLK_ASRC2, "mclk_asrc2", mclk_sai_asrc_parents_p, 0,
551
+
RK3506_CLKSEL_CON(46), 8, 4, MFLAGS,
552
+
RK3506_CLKGATE_CON(16), 2, GFLAGS),
553
+
COMPOSITE_NODIV(MCLK_ASRC3, "mclk_asrc3", mclk_sai_asrc_parents_p, 0,
554
+
RK3506_CLKSEL_CON(46), 12, 4, MFLAGS,
555
+
RK3506_CLKGATE_CON(16), 3, GFLAGS),
556
+
COMPOSITE_NODIV(LRCK_ASRC0_SRC, "lrck_asrc0_src", lrck_asrc_parents_p, 0,
557
+
RK3506_CLKSEL_CON(47), 0, 4, MFLAGS,
558
+
RK3506_CLKGATE_CON(16), 4, GFLAGS),
559
+
COMPOSITE_NODIV(LRCK_ASRC0_DST, "lrck_asrc0_dst", lrck_asrc_parents_p, 0,
560
+
RK3506_CLKSEL_CON(47), 4, 4, MFLAGS,
561
+
RK3506_CLKGATE_CON(16), 5, GFLAGS),
562
+
COMPOSITE_NODIV(LRCK_ASRC1_SRC, "lrck_asrc1_src", lrck_asrc_parents_p, 0,
563
+
RK3506_CLKSEL_CON(47), 8, 4, MFLAGS,
564
+
RK3506_CLKGATE_CON(16), 6, GFLAGS),
565
+
COMPOSITE_NODIV(LRCK_ASRC1_DST, "lrck_asrc1_dst", lrck_asrc_parents_p, 0,
566
+
RK3506_CLKSEL_CON(47), 12, 4, MFLAGS,
567
+
RK3506_CLKGATE_CON(16), 7, GFLAGS),
568
+
569
+
/* hs peri */
570
+
COMPOSITE(ACLK_HSPERI_ROOT, "aclk_hsperi_root", gpll_v0pll_v1pll_div_parents_p, CLK_IS_CRITICAL,
571
+
RK3506_CLKSEL_CON(49), 5, 2, MFLAGS, 0, 5, DFLAGS,
572
+
RK3506_CLKGATE_CON(17), 0, GFLAGS),
573
+
GATE(HCLK_HSPERI_ROOT, "hclk_hsperi_root", "aclk_hsperi_root", CLK_IS_CRITICAL,
574
+
RK3506_CLKGATE_CON(17), 1, GFLAGS),
575
+
GATE(PCLK_HSPERI_ROOT, "pclk_hsperi_root", "hclk_hsperi_root", CLK_IS_CRITICAL,
576
+
RK3506_CLKGATE_CON(17), 2, GFLAGS),
577
+
COMPOSITE(CCLK_SRC_SDMMC, "cclk_src_sdmmc", cclk_src_sdmmc_parents_p, 0,
578
+
RK3506_CLKSEL_CON(49), 13, 2, MFLAGS, 7, 6, DFLAGS,
579
+
RK3506_CLKGATE_CON(17), 6, GFLAGS),
580
+
GATE(HCLK_SDMMC, "hclk_sdmmc", "hclk_hsperi_root", 0,
581
+
RK3506_CLKGATE_CON(17), 7, GFLAGS),
582
+
GATE(HCLK_FSPI, "hclk_fspi", "hclk_hsperi_root", 0,
583
+
RK3506_CLKGATE_CON(17), 8, GFLAGS),
584
+
COMPOSITE(SCLK_FSPI, "sclk_fspi", xin24m_g_gpll_v0pll_v1pll_g_parents_p, 0,
585
+
RK3506_CLKSEL_CON(50), 5, 2, MFLAGS, 0, 5, DFLAGS,
586
+
RK3506_CLKGATE_CON(17), 9, GFLAGS),
587
+
GATE(PCLK_SPI2, "pclk_spi2", "pclk_hsperi_root", 0,
588
+
RK3506_CLKGATE_CON(17), 10, GFLAGS),
589
+
GATE(ACLK_MAC0, "aclk_mac0", "aclk_hsperi_root", 0,
590
+
RK3506_CLKGATE_CON(17), 11, GFLAGS),
591
+
GATE(ACLK_MAC1, "aclk_mac1", "aclk_hsperi_root", 0,
592
+
RK3506_CLKGATE_CON(17), 12, GFLAGS),
593
+
GATE(PCLK_MAC0, "pclk_mac0", "pclk_hsperi_root", 0,
594
+
RK3506_CLKGATE_CON(17), 13, GFLAGS),
595
+
GATE(PCLK_MAC1, "pclk_mac1", "pclk_hsperi_root", 0,
596
+
RK3506_CLKGATE_CON(17), 14, GFLAGS),
597
+
COMPOSITE_NOMUX(CLK_MAC_ROOT, "clk_mac_root", "gpll", 0,
598
+
RK3506_CLKSEL_CON(50), 7, 5, DFLAGS,
599
+
RK3506_CLKGATE_CON(17), 15, GFLAGS),
600
+
GATE(CLK_MAC0, "clk_mac0", "clk_mac_root", 0,
601
+
RK3506_CLKGATE_CON(18), 0, GFLAGS),
602
+
GATE(CLK_MAC1, "clk_mac1", "clk_mac_root", 0,
603
+
RK3506_CLKGATE_CON(18), 1, GFLAGS),
604
+
COMPOSITE(MCLK_SAI2, "mclk_sai2", mclk_sai_asrc_parents_p, 0,
605
+
RK3506_CLKSEL_CON(51), 8, 4, MFLAGS, 0, 8, DFLAGS,
606
+
RK3506_CLKGATE_CON(18), 2, GFLAGS),
607
+
GATE(HCLK_SAI2, "hclk_sai2", "hclk_hsperi_root", 0,
608
+
RK3506_CLKGATE_CON(18), 3, GFLAGS),
609
+
GATE(MCLK_OUT_SAI2, "mclk_out_sai2", "mclk_sai2", 0,
610
+
RK3506_CLKGATE_CON(18), 4, GFLAGS),
611
+
COMPOSITE(MCLK_SAI3_SRC, "mclk_sai3_src", mclk_sai_asrc_parents_p, 0,
612
+
RK3506_CLKSEL_CON(52), 8, 4, MFLAGS, 0, 8, DFLAGS,
613
+
RK3506_CLKGATE_CON(18), 5, GFLAGS),
614
+
GATE(HCLK_SAI3, "hclk_sai3", "hclk_hsperi_root", 0,
615
+
RK3506_CLKGATE_CON(18), 6, GFLAGS),
616
+
GATE(MCLK_SAI3, "mclk_sai3", "mclk_sai3_src", 0,
617
+
RK3506_CLKGATE_CON(18), 7, GFLAGS),
618
+
GATE(MCLK_OUT_SAI3, "mclk_out_sai3", "mclk_sai3_src", 0,
619
+
RK3506_CLKGATE_CON(18), 8, GFLAGS),
620
+
COMPOSITE(MCLK_SAI4_SRC, "mclk_sai4_src", mclk_sai_asrc_parents_p, 0,
621
+
RK3506_CLKSEL_CON(53), 8, 4, MFLAGS, 0, 8, DFLAGS,
622
+
RK3506_CLKGATE_CON(18), 9, GFLAGS),
623
+
GATE(HCLK_SAI4, "hclk_sai4", "hclk_hsperi_root", 0,
624
+
RK3506_CLKGATE_CON(18), 10, GFLAGS),
625
+
GATE(MCLK_SAI4, "mclk_sai4", "mclk_sai4_src", 0,
626
+
RK3506_CLKGATE_CON(18), 11, GFLAGS),
627
+
GATE(HCLK_DSM, "hclk_dsm", "hclk_hsperi_root", 0,
628
+
RK3506_CLKGATE_CON(18), 12, GFLAGS),
629
+
GATE(MCLK_DSM, "mclk_dsm", "mclk_sai3_src", 0,
630
+
RK3506_CLKGATE_CON(18), 13, GFLAGS),
631
+
GATE(PCLK_AUDIO_ADC, "pclk_audio_adc", "pclk_hsperi_root", 0,
632
+
RK3506_CLKGATE_CON(18), 14, GFLAGS),
633
+
GATE(MCLK_AUDIO_ADC, "mclk_audio_adc", "mclk_sai4_src", 0,
634
+
RK3506_CLKGATE_CON(18), 15, GFLAGS),
635
+
FACTOR(MCLK_AUDIO_ADC_DIV4, "mclk_audio_adc_div4", "mclk_audio_adc", 0, 1, 4),
636
+
GATE(PCLK_SARADC, "pclk_saradc", "pclk_hsperi_root", 0,
637
+
RK3506_CLKGATE_CON(19), 0, GFLAGS),
638
+
COMPOSITE(CLK_SARADC, "clk_saradc", xin24m_400k_32k_parents_p, 0,
639
+
RK3506_CLKSEL_CON(54), 4, 2, MFLAGS, 0, 4, DFLAGS,
640
+
RK3506_CLKGATE_CON(19), 1, GFLAGS),
641
+
GATE(PCLK_OTPC_NS, "pclk_otpc_ns", "pclk_hsperi_root", 0,
642
+
RK3506_CLKGATE_CON(19), 3, GFLAGS),
643
+
GATE(CLK_SBPI_OTPC_NS, "clk_sbpi_otpc_ns", "xin24m_gate", 0,
644
+
RK3506_CLKGATE_CON(19), 4, GFLAGS),
645
+
FACTOR(CLK_USER_OTPC_NS, "clk_user_otpc_ns", "clk_sbpi_otpc_ns", 0, 1, 2),
646
+
GATE(PCLK_UART5, "pclk_uart5", "pclk_hsperi_root", 0,
647
+
RK3506_CLKGATE_CON(19), 6, GFLAGS),
648
+
COMPOSITE(SCLK_UART5, "sclk_uart5", sclk_uart_parents_p, 0,
649
+
RK3506_CLKSEL_CON(54), 11, 3, MFLAGS, 6, 5, DFLAGS,
650
+
RK3506_CLKGATE_CON(19), 7, GFLAGS),
651
+
GATE(PCLK_GPIO234_IOC, "pclk_gpio234_ioc", "pclk_hsperi_root", CLK_IS_CRITICAL,
652
+
RK3506_CLKGATE_CON(19), 8, GFLAGS),
653
+
COMPOSITE(CLK_MAC_PTP_ROOT, "clk_mac_ptp_root", clk_mac_ptp_root_parents_p, 0,
654
+
RK3506_CLKSEL_CON(55), 5, 2, MFLAGS, 0, 5, DFLAGS,
655
+
RK3506_CLKGATE_CON(19), 9, GFLAGS),
656
+
GATE(CLK_MAC0_PTP, "clk_mac0_ptp", "clk_mac_ptp_root", 0,
657
+
RK3506_CLKGATE_CON(19), 10, GFLAGS),
658
+
GATE(CLK_MAC1_PTP, "clk_mac1_ptp", "clk_mac_ptp_root", 0,
659
+
RK3506_CLKGATE_CON(19), 11, GFLAGS),
660
+
COMPOSITE(ACLK_VIO_ROOT, "aclk_vio_root", gpll_v0pll_v1pll_g_parents_p, 0,
661
+
RK3506_CLKSEL_CON(58), 5, 2, MFLAGS, 0, 5, DFLAGS,
662
+
RK3506_CLKGATE_CON(21), 0, GFLAGS),
663
+
COMPOSITE(HCLK_VIO_ROOT, "hclk_vio_root", gpll_v0pll_v1pll_div_parents_p, 0,
664
+
RK3506_CLKSEL_CON(58), 12, 2, MFLAGS, 7, 5, DFLAGS,
665
+
RK3506_CLKGATE_CON(21), 1, GFLAGS),
666
+
GATE(PCLK_VIO_ROOT, "pclk_vio_root", "hclk_vio_root", 0,
667
+
RK3506_CLKGATE_CON(21), 2, GFLAGS),
668
+
GATE(HCLK_RGA, "hclk_rga", "hclk_vio_root", 0,
669
+
RK3506_CLKGATE_CON(21), 6, GFLAGS),
670
+
GATE(ACLK_RGA, "aclk_rga", "aclk_vio_root", 0,
671
+
RK3506_CLKGATE_CON(21), 7, GFLAGS),
672
+
COMPOSITE(CLK_CORE_RGA, "clk_core_rga", gpll_v0pll_v1pll_g_parents_p, 0,
673
+
RK3506_CLKSEL_CON(59), 5, 2, MFLAGS, 0, 5, DFLAGS,
674
+
RK3506_CLKGATE_CON(21), 8, GFLAGS),
675
+
GATE(ACLK_VOP, "aclk_vop", "aclk_vio_root", 0,
676
+
RK3506_CLKGATE_CON(21), 9, GFLAGS),
677
+
GATE(HCLK_VOP, "hclk_vop", "hclk_vio_root", 0,
678
+
RK3506_CLKGATE_CON(21), 10, GFLAGS),
679
+
COMPOSITE(DCLK_VOP, "dclk_vop", dclk_vop_parents_p, 0,
680
+
RK3506_CLKSEL_CON(60), 8, 3, MFLAGS, 0, 8, DFLAGS,
681
+
RK3506_CLKGATE_CON(21), 11, GFLAGS),
682
+
GATE(PCLK_DPHY, "pclk_dphy", "pclk_vio_root", 0,
683
+
RK3506_CLKGATE_CON(21), 12, GFLAGS),
684
+
GATE(PCLK_DSI_HOST, "pclk_dsi_host", "pclk_vio_root", 0,
685
+
RK3506_CLKGATE_CON(21), 13, GFLAGS),
686
+
GATE(PCLK_TSADC, "pclk_tsadc", "pclk_vio_root", 0,
687
+
RK3506_CLKGATE_CON(21), 14, GFLAGS),
688
+
COMPOSITE_NOMUX(CLK_TSADC, "clk_tsadc", "xin24m_gate", 0,
689
+
RK3506_CLKSEL_CON(61), 0, 8, DFLAGS,
690
+
RK3506_CLKGATE_CON(21), 15, GFLAGS),
691
+
COMPOSITE_NOMUX(CLK_TSADC_TSEN, "clk_tsadc_tsen", "xin24m_gate", 0,
692
+
RK3506_CLKSEL_CON(61), 8, 3, DFLAGS,
693
+
RK3506_CLKGATE_CON(22), 0, GFLAGS),
694
+
GATE(PCLK_GPIO1_IOC, "pclk_gpio1_ioc", "pclk_vio_root", CLK_IS_CRITICAL,
695
+
RK3506_CLKGATE_CON(22), 1, GFLAGS),
696
+
697
+
/* pmu */
698
+
GATE(CLK_PMU, "clk_pmu", "xin24m", CLK_IGNORE_UNUSED,
699
+
RK3506_PMU_CLKGATE_CON(0), 1, GFLAGS),
700
+
GATE(PCLK_PMU, "pclk_pmu", "pclk_pmu_root", CLK_IGNORE_UNUSED,
701
+
RK3506_PMU_CLKGATE_CON(0), 2, GFLAGS),
702
+
GATE(PCLK_PMU_CRU, "pclk_pmu_cru", "pclk_pmu_root", CLK_IGNORE_UNUSED,
703
+
RK3506_PMU_CLKGATE_CON(0), 4, GFLAGS),
704
+
GATE(PCLK_PMU_GRF, "pclk_pmu_grf", "pclk_pmu_root", CLK_IGNORE_UNUSED,
705
+
RK3506_PMU_CLKGATE_CON(0), 5, GFLAGS),
706
+
GATE(PCLK_GPIO0_IOC, "pclk_gpio0_ioc", "pclk_pmu_root", CLK_IS_CRITICAL,
707
+
RK3506_PMU_CLKGATE_CON(0), 7, GFLAGS),
708
+
GATE(PCLK_GPIO0, "pclk_gpio0", "pclk_pmu_root", 0,
709
+
RK3506_PMU_CLKGATE_CON(0), 8, GFLAGS),
710
+
COMPOSITE_NODIV(DBCLK_GPIO0, "dbclk_gpio0", dbclk_gpio0_parents_p, 0,
711
+
RK3506_PMU_CLKSEL_CON(0), 0, 2, MFLAGS,
712
+
RK3506_PMU_CLKGATE_CON(0), 9, GFLAGS),
713
+
GATE(PCLK_GPIO1_SHADOW, "pclk_gpio1_shadow", "pclk_pmu_root", 0,
714
+
RK3506_PMU_CLKGATE_CON(0), 10, GFLAGS),
715
+
COMPOSITE_NODIV(DBCLK_GPIO1_SHADOW, "dbclk_gpio1_shadow", dbclk_gpio0_parents_p, 0,
716
+
RK3506_PMU_CLKSEL_CON(0), 2, 2, MFLAGS,
717
+
RK3506_PMU_CLKGATE_CON(0), 11, GFLAGS),
718
+
GATE(PCLK_PMU_HP_TIMER, "pclk_pmu_hp_timer", "pclk_pmu_root", CLK_IGNORE_UNUSED,
719
+
RK3506_PMU_CLKGATE_CON(0), 12, GFLAGS),
720
+
MUX(CLK_PMU_HP_TIMER, "clk_pmu_hp_timer", clk_pmu_hp_timer_parents_p, CLK_IGNORE_UNUSED,
721
+
RK3506_PMU_CLKSEL_CON(0), 4, 2, MFLAGS),
722
+
GATE(PCLK_PWM0, "pclk_pwm0", "pclk_pmu_root", 0,
723
+
RK3506_PMU_CLKGATE_CON(0), 15, GFLAGS),
724
+
COMPOSITE_NOMUX(CLK_PWM0, "clk_pwm0", "clk_gpll_div_100m", 0,
725
+
RK3506_PMU_CLKSEL_CON(0), 6, 4, DFLAGS,
726
+
RK3506_PMU_CLKGATE_CON(1), 0, GFLAGS),
727
+
GATE(CLK_OSC_PWM0, "clk_osc_pwm0", "xin24m", 0,
728
+
RK3506_PMU_CLKGATE_CON(1), 1, GFLAGS),
729
+
GATE(CLK_RC_PWM0, "clk_rc_pwm0", "clk_rc", 0,
730
+
RK3506_PMU_CLKGATE_CON(1), 2, GFLAGS),
731
+
COMPOSITE_NOMUX(CLK_MAC_OUT, "clk_mac_out", "gpll", 0,
732
+
RK3506_PMU_CLKSEL_CON(0), 10, 6, DFLAGS,
733
+
RK3506_PMU_CLKGATE_CON(1), 3, GFLAGS),
734
+
COMPOSITE(CLK_REF_OUT0, "clk_ref_out0", clk_ref_out_parents_p, 0,
735
+
RK3506_PMU_CLKSEL_CON(1), 6, 2, MFLAGS, 0, 6, DFLAGS,
736
+
RK3506_PMU_CLKGATE_CON(1), 4, GFLAGS),
737
+
COMPOSITE(CLK_REF_OUT1, "clk_ref_out1", clk_ref_out_parents_p, 0,
738
+
RK3506_PMU_CLKSEL_CON(1), 14, 2, MFLAGS, 8, 6, DFLAGS,
739
+
RK3506_PMU_CLKGATE_CON(1), 5, GFLAGS),
740
+
MUX(CLK_32K_FRAC_MUX, "clk_32k_frac_mux", clk_32k_frac_parents_p, 0,
741
+
RK3506_PMU_CLKSEL_CON(3), 0, 2, MFLAGS),
742
+
COMPOSITE_FRAC(CLK_32K_FRAC, "clk_32k_frac", "clk_32k_frac_mux", 0,
743
+
RK3506_PMU_CLKSEL_CON(2), 0,
744
+
RK3506_PMU_CLKGATE_CON(1), 6, GFLAGS),
745
+
COMPOSITE_NOMUX(CLK_32K_RC, "clk_32k_rc", "clk_rc", CLK_IS_CRITICAL,
746
+
RK3506_PMU_CLKSEL_CON(3), 2, 5, DFLAGS,
747
+
RK3506_PMU_CLKGATE_CON(1), 7, GFLAGS),
748
+
COMPOSITE_NODIV(CLK_32K, "clk_32k", clk_32k_parents_p, CLK_IS_CRITICAL,
749
+
RK3506_PMU_CLKSEL_CON(3), 7, 2, MFLAGS,
750
+
RK3506_PMU_CLKGATE_CON(1), 8, GFLAGS),
751
+
COMPOSITE_NODIV(CLK_32K_PMU, "clk_32k_pmu", clk_32k_parents_p, CLK_IS_CRITICAL,
752
+
RK3506_PMU_CLKSEL_CON(3), 9, 2, MFLAGS,
753
+
RK3506_PMU_CLKGATE_CON(1), 9, GFLAGS),
754
+
GATE(CLK_PMU_32K, "clk_pmu_32k", "clk_32k_pmu", CLK_IGNORE_UNUSED,
755
+
RK3506_PMU_CLKGATE_CON(0), 3, GFLAGS),
756
+
GATE(CLK_PMU_HP_TIMER_32K, "clk_pmu_hp_timer_32k", "clk_32k_pmu", CLK_IGNORE_UNUSED,
757
+
RK3506_PMU_CLKGATE_CON(0), 14, GFLAGS),
758
+
GATE(PCLK_TOUCH_KEY, "pclk_touch_key", "pclk_pmu_root", CLK_IGNORE_UNUSED,
759
+
RK3506_PMU_CLKGATE_CON(1), 12, GFLAGS),
760
+
GATE(CLK_TOUCH_KEY, "clk_touch_key", "xin24m", CLK_IGNORE_UNUSED,
761
+
RK3506_PMU_CLKGATE_CON(1), 13, GFLAGS),
762
+
COMPOSITE(CLK_REF_PHY_PLL, "clk_ref_phy_pll", gpll_v0pll_v1pll_parents_p, 0,
763
+
RK3506_PMU_CLKSEL_CON(4), 13, 2, MFLAGS, 6, 7, DFLAGS,
764
+
RK3506_PMU_CLKGATE_CON(1), 14, GFLAGS),
765
+
MUX(CLK_REF_PHY_PMU_MUX, "clk_ref_phy_pmu_mux", clk_ref_phy_pmu_mux_parents_p, 0,
766
+
RK3506_PMU_CLKSEL_CON(4), 15, 1, MFLAGS),
767
+
GATE(CLK_WIFI_OUT, "clk_wifi_out", "xin24m", 0,
768
+
RK3506_PMU_CLKGATE_CON(2), 0, GFLAGS),
769
+
MUX(CLK_V0PLL_REF, "clk_v0pll_ref", clk_vpll_ref_parents_p, CLK_IGNORE_UNUSED,
770
+
RK3506_PMU_CLKSEL_CON(6), 0, 1, MFLAGS),
771
+
MUX(CLK_V1PLL_REF, "clk_v1pll_ref", clk_vpll_ref_parents_p, CLK_IGNORE_UNUSED,
772
+
RK3506_PMU_CLKSEL_CON(6), 1, 1, MFLAGS),
773
+
774
+
/* secure ns */
775
+
GATE(CLK_CORE_CRYPTO_NS, "clk_core_crypto_ns", "clk_core_crypto", 0,
776
+
RK3506_CLKGATE_CON(5), 12, GFLAGS),
777
+
GATE(CLK_PKA_CRYPTO_NS, "clk_pka_crypto_ns", "clk_pka_crypto", 0,
778
+
RK3506_CLKGATE_CON(5), 13, GFLAGS),
779
+
780
+
/* io */
781
+
GATE(CLK_SPI2, "clk_spi2", "clk_spi2_io", 0,
782
+
RK3506_CLKGATE_CON(20), 0, GFLAGS),
783
+
};
784
+
785
+
static void __init rk3506_clk_init(struct device_node *np)
786
+
{
787
+
struct rockchip_clk_provider *ctx;
788
+
unsigned long clk_nr_clks;
789
+
void __iomem *reg_base;
790
+
791
+
clk_nr_clks = rockchip_clk_find_max_clk_id(rk3506_clk_branches,
792
+
ARRAY_SIZE(rk3506_clk_branches)) + 1;
793
+
794
+
reg_base = of_iomap(np, 0);
795
+
if (!reg_base) {
796
+
pr_err("%s: could not map cru region\n", __func__);
797
+
return;
798
+
}
799
+
800
+
ctx = rockchip_clk_init(np, reg_base, clk_nr_clks);
801
+
if (IS_ERR(ctx)) {
802
+
pr_err("%s: rockchip clk init failed\n", __func__);
803
+
iounmap(reg_base);
804
+
return;
805
+
}
806
+
807
+
rockchip_clk_register_plls(ctx, rk3506_pll_clks,
808
+
ARRAY_SIZE(rk3506_pll_clks),
809
+
0);
810
+
811
+
rockchip_clk_register_armclk_multi_pll(ctx, &rk3506_armclk,
812
+
rk3506_cpuclk_rates,
813
+
ARRAY_SIZE(rk3506_cpuclk_rates));
814
+
815
+
rockchip_clk_register_branches(ctx, rk3506_clk_branches,
816
+
ARRAY_SIZE(rk3506_clk_branches));
817
+
818
+
rk3506_rst_init(np, reg_base);
819
+
820
+
rockchip_register_restart_notifier(ctx, RK3506_GLB_SRST_FST, NULL);
821
+
822
+
rockchip_clk_of_add_provider(np, ctx);
823
+
824
+
/* pvtpll src init */
825
+
writel_relaxed(PVTPLL_SRC_SEL_PVTPLL, reg_base + RK3506_CLKSEL_CON(15));
826
+
}
827
+
828
+
CLK_OF_DECLARE(rk3506_cru, "rockchip,rk3506-cru", rk3506_clk_init);
829
+
830
+
struct clk_rk3506_inits {
831
+
void (*inits)(struct device_node *np);
832
+
};
833
+
834
+
static const struct clk_rk3506_inits clk_rk3506_cru_init = {
835
+
.inits = rk3506_clk_init,
836
+
};
837
+
838
+
static const struct of_device_id clk_rk3506_match_table[] = {
839
+
{
840
+
.compatible = "rockchip,rk3506-cru",
841
+
.data = &clk_rk3506_cru_init,
842
+
},
843
+
{ }
844
+
};
845
+
846
+
static int clk_rk3506_probe(struct platform_device *pdev)
847
+
{
848
+
const struct clk_rk3506_inits *init_data;
849
+
struct device *dev = &pdev->dev;
850
+
851
+
init_data = device_get_match_data(dev);
852
+
if (!init_data)
853
+
return -EINVAL;
854
+
855
+
if (init_data->inits)
856
+
init_data->inits(dev->of_node);
857
+
858
+
return 0;
859
+
}
860
+
861
+
static struct platform_driver clk_rk3506_driver = {
862
+
.probe = clk_rk3506_probe,
863
+
.driver = {
864
+
.name = "clk-rk3506",
865
+
.of_match_table = clk_rk3506_match_table,
866
+
.suppress_bind_attrs = true,
867
+
},
868
+
};
869
+
builtin_platform_driver_probe(clk_rk3506_driver, clk_rk3506_probe);
+13
drivers/clk/rockchip/clk.h
+13
drivers/clk/rockchip/clk.h
···
275
275
#define RK3399_PMU_CLKGATE_CON(x) ((x) * 0x4 + 0x100)
276
276
#define RK3399_PMU_SOFTRST_CON(x) ((x) * 0x4 + 0x110)
277
277
278
+
#define RK3506_PMU_CRU_BASE 0x10000
279
+
#define RK3506_PLL_CON(x) ((x) * 0x4 + RK3506_PMU_CRU_BASE)
280
+
#define RK3506_CLKSEL_CON(x) ((x) * 0x4 + 0x300)
281
+
#define RK3506_CLKGATE_CON(x) ((x) * 0x4 + 0x800)
282
+
#define RK3506_SOFTRST_CON(x) ((x) * 0x4 + 0xa00)
283
+
#define RK3506_PMU_CLKSEL_CON(x) ((x) * 0x4 + 0x300 + RK3506_PMU_CRU_BASE)
284
+
#define RK3506_PMU_CLKGATE_CON(x) ((x) * 0x4 + 0x800 + RK3506_PMU_CRU_BASE)
285
+
#define RK3506_MODE_CON 0x280
286
+
#define RK3506_GLB_CNT_TH 0xc00
287
+
#define RK3506_GLB_SRST_FST 0xc08
288
+
#define RK3506_GLB_SRST_SND 0xc0c
289
+
278
290
#define RK3528_PMU_CRU_BASE 0x10000
279
291
#define RK3528_PCIE_CRU_BASE 0x20000
280
292
#define RK3528_DDRPHY_CRU_BASE 0x28000
···
1341
1329
}
1342
1330
1343
1331
void rv1126b_rst_init(struct device_node *np, void __iomem *reg_base);
1332
+
void rk3506_rst_init(struct device_node *np, void __iomem *reg_base);
1344
1333
void rk3528_rst_init(struct device_node *np, void __iomem *reg_base);
1345
1334
void rk3562_rst_init(struct device_node *np, void __iomem *reg_base);
1346
1335
void rk3576_rst_init(struct device_node *np, void __iomem *reg_base);
+226
drivers/clk/rockchip/rst-rk3506.c
+226
drivers/clk/rockchip/rst-rk3506.c
···
1
+
// SPDX-License-Identifier: GPL-2.0-or-later
2
+
/*
3
+
* Copyright (c) 2025 Rockchip Electronics Co., Ltd.
4
+
* Author: Finley Xiao <finley.xiao@rock-chips.com>
5
+
*/
6
+
7
+
#include <linux/module.h>
8
+
#include <linux/of.h>
9
+
#include <dt-bindings/reset/rockchip,rk3506-cru.h>
10
+
#include "clk.h"
11
+
12
+
/* 0xFF9A0000 + 0x0A00 */
13
+
#define RK3506_CRU_RESET_OFFSET(id, reg, bit) [id] = (0 + reg * 16 + bit)
14
+
15
+
/* mapping table for reset ID to register offset */
16
+
static const int rk3506_register_offset[] = {
17
+
/* CRU-->SOFTRST_CON00 */
18
+
RK3506_CRU_RESET_OFFSET(SRST_NCOREPORESET0_AC, 0, 0),
19
+
RK3506_CRU_RESET_OFFSET(SRST_NCOREPORESET1_AC, 0, 1),
20
+
RK3506_CRU_RESET_OFFSET(SRST_NCOREPORESET2_AC, 0, 2),
21
+
RK3506_CRU_RESET_OFFSET(SRST_NCORESET0_AC, 0, 4),
22
+
RK3506_CRU_RESET_OFFSET(SRST_NCORESET1_AC, 0, 5),
23
+
RK3506_CRU_RESET_OFFSET(SRST_NCORESET2_AC, 0, 6),
24
+
RK3506_CRU_RESET_OFFSET(SRST_NL2RESET_AC, 0, 8),
25
+
RK3506_CRU_RESET_OFFSET(SRST_A_CORE_BIU_AC, 0, 9),
26
+
RK3506_CRU_RESET_OFFSET(SRST_H_M0_AC, 0, 10),
27
+
28
+
/* CRU-->SOFTRST_CON02 */
29
+
RK3506_CRU_RESET_OFFSET(SRST_NDBGRESET, 2, 10),
30
+
RK3506_CRU_RESET_OFFSET(SRST_P_CORE_BIU, 2, 14),
31
+
RK3506_CRU_RESET_OFFSET(SRST_PMU, 2, 15),
32
+
33
+
/* CRU-->SOFTRST_CON03 */
34
+
RK3506_CRU_RESET_OFFSET(SRST_P_DBG, 3, 1),
35
+
RK3506_CRU_RESET_OFFSET(SRST_POT_DBG, 3, 2),
36
+
RK3506_CRU_RESET_OFFSET(SRST_P_CORE_GRF, 3, 4),
37
+
RK3506_CRU_RESET_OFFSET(SRST_CORE_EMA_DETECT, 3, 6),
38
+
RK3506_CRU_RESET_OFFSET(SRST_REF_PVTPLL_CORE, 3, 7),
39
+
RK3506_CRU_RESET_OFFSET(SRST_P_GPIO1, 3, 8),
40
+
RK3506_CRU_RESET_OFFSET(SRST_DB_GPIO1, 3, 9),
41
+
42
+
/* CRU-->SOFTRST_CON04 */
43
+
RK3506_CRU_RESET_OFFSET(SRST_A_CORE_PERI_BIU, 4, 3),
44
+
RK3506_CRU_RESET_OFFSET(SRST_A_DSMC, 4, 5),
45
+
RK3506_CRU_RESET_OFFSET(SRST_P_DSMC, 4, 6),
46
+
RK3506_CRU_RESET_OFFSET(SRST_FLEXBUS, 4, 7),
47
+
RK3506_CRU_RESET_OFFSET(SRST_A_FLEXBUS, 4, 9),
48
+
RK3506_CRU_RESET_OFFSET(SRST_H_FLEXBUS, 4, 10),
49
+
RK3506_CRU_RESET_OFFSET(SRST_A_DSMC_SLV, 4, 11),
50
+
RK3506_CRU_RESET_OFFSET(SRST_H_DSMC_SLV, 4, 12),
51
+
RK3506_CRU_RESET_OFFSET(SRST_DSMC_SLV, 4, 13),
52
+
53
+
/* CRU-->SOFTRST_CON05 */
54
+
RK3506_CRU_RESET_OFFSET(SRST_A_BUS_BIU, 5, 3),
55
+
RK3506_CRU_RESET_OFFSET(SRST_H_BUS_BIU, 5, 4),
56
+
RK3506_CRU_RESET_OFFSET(SRST_P_BUS_BIU, 5, 5),
57
+
RK3506_CRU_RESET_OFFSET(SRST_A_SYSRAM, 5, 6),
58
+
RK3506_CRU_RESET_OFFSET(SRST_H_SYSRAM, 5, 7),
59
+
RK3506_CRU_RESET_OFFSET(SRST_A_DMAC0, 5, 8),
60
+
RK3506_CRU_RESET_OFFSET(SRST_A_DMAC1, 5, 9),
61
+
RK3506_CRU_RESET_OFFSET(SRST_H_M0, 5, 10),
62
+
RK3506_CRU_RESET_OFFSET(SRST_M0_JTAG, 5, 11),
63
+
RK3506_CRU_RESET_OFFSET(SRST_H_CRYPTO, 5, 15),
64
+
65
+
/* CRU-->SOFTRST_CON06 */
66
+
RK3506_CRU_RESET_OFFSET(SRST_H_RNG, 6, 0),
67
+
RK3506_CRU_RESET_OFFSET(SRST_P_BUS_GRF, 6, 1),
68
+
RK3506_CRU_RESET_OFFSET(SRST_P_TIMER0, 6, 2),
69
+
RK3506_CRU_RESET_OFFSET(SRST_TIMER0_CH0, 6, 3),
70
+
RK3506_CRU_RESET_OFFSET(SRST_TIMER0_CH1, 6, 4),
71
+
RK3506_CRU_RESET_OFFSET(SRST_TIMER0_CH2, 6, 5),
72
+
RK3506_CRU_RESET_OFFSET(SRST_TIMER0_CH3, 6, 6),
73
+
RK3506_CRU_RESET_OFFSET(SRST_TIMER0_CH4, 6, 7),
74
+
RK3506_CRU_RESET_OFFSET(SRST_TIMER0_CH5, 6, 8),
75
+
RK3506_CRU_RESET_OFFSET(SRST_P_WDT0, 6, 9),
76
+
RK3506_CRU_RESET_OFFSET(SRST_T_WDT0, 6, 10),
77
+
RK3506_CRU_RESET_OFFSET(SRST_P_WDT1, 6, 11),
78
+
RK3506_CRU_RESET_OFFSET(SRST_T_WDT1, 6, 12),
79
+
RK3506_CRU_RESET_OFFSET(SRST_P_MAILBOX, 6, 13),
80
+
RK3506_CRU_RESET_OFFSET(SRST_P_INTMUX, 6, 14),
81
+
RK3506_CRU_RESET_OFFSET(SRST_P_SPINLOCK, 6, 15),
82
+
83
+
/* CRU-->SOFTRST_CON07 */
84
+
RK3506_CRU_RESET_OFFSET(SRST_P_DDRC, 7, 0),
85
+
RK3506_CRU_RESET_OFFSET(SRST_H_DDRPHY, 7, 1),
86
+
RK3506_CRU_RESET_OFFSET(SRST_P_DDRMON, 7, 2),
87
+
RK3506_CRU_RESET_OFFSET(SRST_DDRMON_OSC, 7, 3),
88
+
RK3506_CRU_RESET_OFFSET(SRST_P_DDR_LPC, 7, 4),
89
+
RK3506_CRU_RESET_OFFSET(SRST_H_USBOTG0, 7, 5),
90
+
RK3506_CRU_RESET_OFFSET(SRST_USBOTG0_ADP, 7, 7),
91
+
RK3506_CRU_RESET_OFFSET(SRST_H_USBOTG1, 7, 8),
92
+
RK3506_CRU_RESET_OFFSET(SRST_USBOTG1_ADP, 7, 10),
93
+
RK3506_CRU_RESET_OFFSET(SRST_P_USBPHY, 7, 11),
94
+
RK3506_CRU_RESET_OFFSET(SRST_USBPHY_POR, 7, 12),
95
+
RK3506_CRU_RESET_OFFSET(SRST_USBPHY_OTG0, 7, 13),
96
+
RK3506_CRU_RESET_OFFSET(SRST_USBPHY_OTG1, 7, 14),
97
+
98
+
/* CRU-->SOFTRST_CON08 */
99
+
RK3506_CRU_RESET_OFFSET(SRST_A_DMA2DDR, 8, 0),
100
+
RK3506_CRU_RESET_OFFSET(SRST_P_DMA2DDR, 8, 1),
101
+
102
+
/* CRU-->SOFTRST_CON09 */
103
+
RK3506_CRU_RESET_OFFSET(SRST_USBOTG0_UTMI, 9, 0),
104
+
RK3506_CRU_RESET_OFFSET(SRST_USBOTG1_UTMI, 9, 1),
105
+
106
+
/* CRU-->SOFTRST_CON10 */
107
+
RK3506_CRU_RESET_OFFSET(SRST_A_DDRC_0, 10, 0),
108
+
RK3506_CRU_RESET_OFFSET(SRST_A_DDRC_1, 10, 1),
109
+
RK3506_CRU_RESET_OFFSET(SRST_A_DDR_BIU, 10, 2),
110
+
RK3506_CRU_RESET_OFFSET(SRST_DDRC, 10, 3),
111
+
RK3506_CRU_RESET_OFFSET(SRST_DDRMON, 10, 4),
112
+
113
+
/* CRU-->SOFTRST_CON11 */
114
+
RK3506_CRU_RESET_OFFSET(SRST_H_LSPERI_BIU, 11, 2),
115
+
RK3506_CRU_RESET_OFFSET(SRST_P_UART0, 11, 4),
116
+
RK3506_CRU_RESET_OFFSET(SRST_P_UART1, 11, 5),
117
+
RK3506_CRU_RESET_OFFSET(SRST_P_UART2, 11, 6),
118
+
RK3506_CRU_RESET_OFFSET(SRST_P_UART3, 11, 7),
119
+
RK3506_CRU_RESET_OFFSET(SRST_P_UART4, 11, 8),
120
+
RK3506_CRU_RESET_OFFSET(SRST_UART0, 11, 9),
121
+
RK3506_CRU_RESET_OFFSET(SRST_UART1, 11, 10),
122
+
RK3506_CRU_RESET_OFFSET(SRST_UART2, 11, 11),
123
+
RK3506_CRU_RESET_OFFSET(SRST_UART3, 11, 12),
124
+
RK3506_CRU_RESET_OFFSET(SRST_UART4, 11, 13),
125
+
RK3506_CRU_RESET_OFFSET(SRST_P_I2C0, 11, 14),
126
+
RK3506_CRU_RESET_OFFSET(SRST_I2C0, 11, 15),
127
+
128
+
/* CRU-->SOFTRST_CON12 */
129
+
RK3506_CRU_RESET_OFFSET(SRST_P_I2C1, 12, 0),
130
+
RK3506_CRU_RESET_OFFSET(SRST_I2C1, 12, 1),
131
+
RK3506_CRU_RESET_OFFSET(SRST_P_I2C2, 12, 2),
132
+
RK3506_CRU_RESET_OFFSET(SRST_I2C2, 12, 3),
133
+
RK3506_CRU_RESET_OFFSET(SRST_P_PWM1, 12, 4),
134
+
RK3506_CRU_RESET_OFFSET(SRST_PWM1, 12, 5),
135
+
RK3506_CRU_RESET_OFFSET(SRST_P_SPI0, 12, 10),
136
+
RK3506_CRU_RESET_OFFSET(SRST_SPI0, 12, 11),
137
+
RK3506_CRU_RESET_OFFSET(SRST_P_SPI1, 12, 12),
138
+
RK3506_CRU_RESET_OFFSET(SRST_SPI1, 12, 13),
139
+
RK3506_CRU_RESET_OFFSET(SRST_P_GPIO2, 12, 14),
140
+
RK3506_CRU_RESET_OFFSET(SRST_DB_GPIO2, 12, 15),
141
+
142
+
/* CRU-->SOFTRST_CON13 */
143
+
RK3506_CRU_RESET_OFFSET(SRST_P_GPIO3, 13, 0),
144
+
RK3506_CRU_RESET_OFFSET(SRST_DB_GPIO3, 13, 1),
145
+
RK3506_CRU_RESET_OFFSET(SRST_P_GPIO4, 13, 2),
146
+
RK3506_CRU_RESET_OFFSET(SRST_DB_GPIO4, 13, 3),
147
+
RK3506_CRU_RESET_OFFSET(SRST_H_CAN0, 13, 4),
148
+
RK3506_CRU_RESET_OFFSET(SRST_CAN0, 13, 5),
149
+
RK3506_CRU_RESET_OFFSET(SRST_H_CAN1, 13, 6),
150
+
RK3506_CRU_RESET_OFFSET(SRST_CAN1, 13, 7),
151
+
RK3506_CRU_RESET_OFFSET(SRST_H_PDM, 13, 8),
152
+
RK3506_CRU_RESET_OFFSET(SRST_M_PDM, 13, 9),
153
+
RK3506_CRU_RESET_OFFSET(SRST_PDM, 13, 10),
154
+
RK3506_CRU_RESET_OFFSET(SRST_SPDIFTX, 13, 11),
155
+
RK3506_CRU_RESET_OFFSET(SRST_H_SPDIFTX, 13, 12),
156
+
RK3506_CRU_RESET_OFFSET(SRST_H_SPDIFRX, 13, 13),
157
+
RK3506_CRU_RESET_OFFSET(SRST_SPDIFRX, 13, 14),
158
+
RK3506_CRU_RESET_OFFSET(SRST_M_SAI0, 13, 15),
159
+
160
+
/* CRU-->SOFTRST_CON14 */
161
+
RK3506_CRU_RESET_OFFSET(SRST_H_SAI0, 14, 0),
162
+
RK3506_CRU_RESET_OFFSET(SRST_M_SAI1, 14, 2),
163
+
RK3506_CRU_RESET_OFFSET(SRST_H_SAI1, 14, 3),
164
+
RK3506_CRU_RESET_OFFSET(SRST_H_ASRC0, 14, 5),
165
+
RK3506_CRU_RESET_OFFSET(SRST_ASRC0, 14, 6),
166
+
RK3506_CRU_RESET_OFFSET(SRST_H_ASRC1, 14, 7),
167
+
RK3506_CRU_RESET_OFFSET(SRST_ASRC1, 14, 8),
168
+
169
+
/* CRU-->SOFTRST_CON17 */
170
+
RK3506_CRU_RESET_OFFSET(SRST_H_HSPERI_BIU, 17, 4),
171
+
RK3506_CRU_RESET_OFFSET(SRST_H_SDMMC, 17, 7),
172
+
RK3506_CRU_RESET_OFFSET(SRST_H_FSPI, 17, 8),
173
+
RK3506_CRU_RESET_OFFSET(SRST_S_FSPI, 17, 9),
174
+
RK3506_CRU_RESET_OFFSET(SRST_P_SPI2, 17, 10),
175
+
RK3506_CRU_RESET_OFFSET(SRST_A_MAC0, 17, 11),
176
+
RK3506_CRU_RESET_OFFSET(SRST_A_MAC1, 17, 12),
177
+
178
+
/* CRU-->SOFTRST_CON18 */
179
+
RK3506_CRU_RESET_OFFSET(SRST_M_SAI2, 18, 2),
180
+
RK3506_CRU_RESET_OFFSET(SRST_H_SAI2, 18, 3),
181
+
RK3506_CRU_RESET_OFFSET(SRST_H_SAI3, 18, 6),
182
+
RK3506_CRU_RESET_OFFSET(SRST_M_SAI3, 18, 7),
183
+
RK3506_CRU_RESET_OFFSET(SRST_H_SAI4, 18, 10),
184
+
RK3506_CRU_RESET_OFFSET(SRST_M_SAI4, 18, 11),
185
+
RK3506_CRU_RESET_OFFSET(SRST_H_DSM, 18, 12),
186
+
RK3506_CRU_RESET_OFFSET(SRST_M_DSM, 18, 13),
187
+
RK3506_CRU_RESET_OFFSET(SRST_P_AUDIO_ADC, 18, 14),
188
+
RK3506_CRU_RESET_OFFSET(SRST_M_AUDIO_ADC, 18, 15),
189
+
190
+
/* CRU-->SOFTRST_CON19 */
191
+
RK3506_CRU_RESET_OFFSET(SRST_P_SARADC, 19, 0),
192
+
RK3506_CRU_RESET_OFFSET(SRST_SARADC, 19, 1),
193
+
RK3506_CRU_RESET_OFFSET(SRST_SARADC_PHY, 19, 2),
194
+
RK3506_CRU_RESET_OFFSET(SRST_P_OTPC_NS, 19, 3),
195
+
RK3506_CRU_RESET_OFFSET(SRST_SBPI_OTPC_NS, 19, 4),
196
+
RK3506_CRU_RESET_OFFSET(SRST_USER_OTPC_NS, 19, 5),
197
+
RK3506_CRU_RESET_OFFSET(SRST_P_UART5, 19, 6),
198
+
RK3506_CRU_RESET_OFFSET(SRST_UART5, 19, 7),
199
+
RK3506_CRU_RESET_OFFSET(SRST_P_GPIO234_IOC, 19, 8),
200
+
201
+
/* CRU-->SOFTRST_CON21 */
202
+
RK3506_CRU_RESET_OFFSET(SRST_A_VIO_BIU, 21, 3),
203
+
RK3506_CRU_RESET_OFFSET(SRST_H_VIO_BIU, 21, 4),
204
+
RK3506_CRU_RESET_OFFSET(SRST_H_RGA, 21, 6),
205
+
RK3506_CRU_RESET_OFFSET(SRST_A_RGA, 21, 7),
206
+
RK3506_CRU_RESET_OFFSET(SRST_CORE_RGA, 21, 8),
207
+
RK3506_CRU_RESET_OFFSET(SRST_A_VOP, 21, 9),
208
+
RK3506_CRU_RESET_OFFSET(SRST_H_VOP, 21, 10),
209
+
RK3506_CRU_RESET_OFFSET(SRST_VOP, 21, 11),
210
+
RK3506_CRU_RESET_OFFSET(SRST_P_DPHY, 21, 12),
211
+
RK3506_CRU_RESET_OFFSET(SRST_P_DSI_HOST, 21, 13),
212
+
RK3506_CRU_RESET_OFFSET(SRST_P_TSADC, 21, 14),
213
+
RK3506_CRU_RESET_OFFSET(SRST_TSADC, 21, 15),
214
+
215
+
/* CRU-->SOFTRST_CON22 */
216
+
RK3506_CRU_RESET_OFFSET(SRST_P_GPIO1_IOC, 22, 1),
217
+
};
218
+
219
+
void rk3506_rst_init(struct device_node *np, void __iomem *reg_base)
220
+
{
221
+
rockchip_register_softrst_lut(np,
222
+
rk3506_register_offset,
223
+
ARRAY_SIZE(rk3506_register_offset),
224
+
reg_base + RK3506_SOFTRST_CON(0),
225
+
ROCKCHIP_SOFTRST_HIWORD_MASK);
226
+
}