Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux

arm64: Expose AIDR_EL1 via sysfs

The KVM PV ABI recently added a feature that allows the VM to discover
the set of physical CPU implementations, identified by a tuple of
{MIDR_EL1, REVIDR_EL1, AIDR_EL1}. Unlike other KVM PV features, the
expectation is that the VMM implements the hypercall instead of KVM as
it has the authoritative view of where the VM gets scheduled.

To do this the VMM needs to know the values of these registers on any
CPU in the system. While MIDR_EL1 and REVIDR_EL1 are already exposed,
AIDR_EL1 is not. Provide it in sysfs along with the other identification
registers.

Signed-off-by: Oliver Upton <oliver.upton@linux.dev>
Reviewed-by: Cornelia Huck <cohuck@redhat.com>
Reviewed-by: Anshuman Khandual <anshuman.khandual@arm.com>
Link: https://lore.kernel.org/r/20250403231626.3181116-1-oliver.upton@linux.dev
Signed-off-by: Will Deacon <will@kernel.org>

authored by

Oliver Upton and committed by
Will Deacon
17efc1ac 35382a36

+12 -6
+1
Documentation/ABI/testing/sysfs-devices-system-cpu
··· 485 485 /sys/devices/system/cpu/cpuX/regs/identification/ 486 486 /sys/devices/system/cpu/cpuX/regs/identification/midr_el1 487 487 /sys/devices/system/cpu/cpuX/regs/identification/revidr_el1 488 + /sys/devices/system/cpu/cpuX/regs/identification/aidr_el1 488 489 /sys/devices/system/cpu/cpuX/regs/identification/smidr_el1 489 490 Date: June 2016 490 491 Contact: Linux ARM Kernel Mailing list <linux-arm-kernel@lists.infradead.org>
+7 -6
Documentation/arch/arm64/cpu-feature-registers.rst
··· 72 72 process could be migrated to another CPU by the time it uses the 73 73 register value, unless the CPU affinity is set. Hence, there is no 74 74 guarantee that the value reflects the processor that it is 75 - currently executing on. The REVIDR is not exposed due to this 76 - constraint, as REVIDR makes sense only in conjunction with the 77 - MIDR. Alternately, MIDR_EL1 and REVIDR_EL1 are exposed via sysfs 78 - at:: 75 + currently executing on. REVIDR and AIDR are not exposed due to this 76 + constraint, as these registers only make sense in conjunction with 77 + the MIDR. Alternately, MIDR_EL1, REVIDR_EL1, and AIDR_EL1 are exposed 78 + via sysfs at:: 79 79 80 80 /sys/devices/system/cpu/cpu$ID/regs/identification/ 81 - \- midr 82 - \- revidr 81 + \- midr_el1 82 + \- revidr_el1 83 + \- aidr_el1 83 84 84 85 3. Implementation 85 86 --------------------
+1
arch/arm64/include/asm/cpu.h
··· 44 44 u64 reg_dczid; 45 45 u64 reg_midr; 46 46 u64 reg_revidr; 47 + u64 reg_aidr; 47 48 u64 reg_gmid; 48 49 u64 reg_smidr; 49 50 u64 reg_mpamidr;
+3
arch/arm64/kernel/cpuinfo.c
··· 328 328 329 329 CPUREGS_ATTR_RO(midr_el1, midr); 330 330 CPUREGS_ATTR_RO(revidr_el1, revidr); 331 + CPUREGS_ATTR_RO(aidr_el1, aidr); 331 332 CPUREGS_ATTR_RO(smidr_el1, smidr); 332 333 333 334 static struct attribute *cpuregs_id_attrs[] = { 334 335 &cpuregs_attr_midr_el1.attr, 335 336 &cpuregs_attr_revidr_el1.attr, 337 + &cpuregs_attr_aidr_el1.attr, 336 338 NULL 337 339 }; 338 340 ··· 471 469 info->reg_dczid = read_cpuid(DCZID_EL0); 472 470 info->reg_midr = read_cpuid_id(); 473 471 info->reg_revidr = read_cpuid(REVIDR_EL1); 472 + info->reg_aidr = read_cpuid(AIDR_EL1); 474 473 475 474 info->reg_id_aa64dfr0 = read_cpuid(ID_AA64DFR0_EL1); 476 475 info->reg_id_aa64dfr1 = read_cpuid(ID_AA64DFR1_EL1);