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dt-bindings: pci: Add DT binding for Toshiba Visconti PCIe controller
This commit adds the Device Tree binding documentation that allows
to describe the PCIe controller found in Toshiba Visconti SoCs.
Signed-off-by: Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>
Link: https://lore.kernel.org/r/20210723221421.113575-2-nobuhiro1.iwamatsu@toshiba.co.jp
[robh: reference snps,dw-pcie.yaml]
Signed-off-by: Rob Herring <robh@kernel.org>
authored by
Nobuhiro Iwamatsu
and committed by
Rob Herring
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Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml
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Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml
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Documentation/devicetree/bindings/pci/toshiba,visconti-pcie.yaml
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Documentation/devicetree/bindings/pci/toshiba,visconti-pcie.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/pci/toshiba,visconti-pcie.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Toshiba Visconti5 SoC PCIe Host Controller Device Tree Bindings
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maintainers:
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- Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>
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description:
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Toshiba Visconti5 SoC PCIe host controller is based on the Synopsys DesignWare PCIe IP.
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allOf:
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- $ref: /schemas/pci/snps,dw-pcie.yaml#
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properties:
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compatible:
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const: toshiba,visconti-pcie
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reg:
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items:
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- description: Data Bus Interface (DBI) registers.
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- description: PCIe configuration space region.
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- description: Visconti specific additional registers.
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- description: Visconti specific SMU registers
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- description: Visconti specific memory protection unit registers (MPU)
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reg-names:
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items:
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- const: dbi
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- const: config
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- const: ulreg
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- const: smu
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- const: mpu
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interrupts:
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maxItems: 1
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clocks:
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items:
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- description: PCIe reference clock
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- description: PCIe system clock
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- description: Auxiliary clock
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clock-names:
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items:
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- const: ref
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- const: core
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- const: aux
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num-lanes:
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const: 2
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required:
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- reg
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- reg-names
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- interrupts
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- "#interrupt-cells"
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- interrupt-map
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- interrupt-map-mask
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- num-lanes
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- clocks
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- clock-names
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- max-link-speed
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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soc {
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#address-cells = <2>;
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#size-cells = <2>;
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pcie: pcie@28400000 {
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compatible = "toshiba,visconti-pcie";
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reg = <0x0 0x28400000 0x0 0x00400000>,
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<0x0 0x70000000 0x0 0x10000000>,
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<0x0 0x28050000 0x0 0x00010000>,
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<0x0 0x24200000 0x0 0x00002000>,
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<0x0 0x24162000 0x0 0x00001000>;
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reg-names = "dbi", "config", "ulreg", "smu", "mpu";
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device_type = "pci";
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bus-range = <0x00 0xff>;
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num-lanes = <2>;
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num-viewport = <8>;
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#address-cells = <3>;
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#size-cells = <2>;
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#interrupt-cells = <1>;
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ranges = <0x81000000 0 0x40000000 0 0x40000000 0 0x00010000>,
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<0x82000000 0 0x50000000 0 0x50000000 0 0x20000000>;
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interrupts = <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "intr";
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interrupt-map-mask = <0 0 0 7>;
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interrupt-map =
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<0 0 0 1 &gic GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH
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0 0 0 2 &gic GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH
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0 0 0 3 &gic GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH
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0 0 0 4 &gic GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&extclk100mhz>, <&clk600mhz>, <&clk25mhz>;
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clock-names = "ref", "core", "aux";
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max-link-speed = <2>;
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};
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};
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...