tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'icc-6.9-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/djakov/icc into char-misc-next
Georgi writes:
interconnect changes for 6.9
This pull request contains the interconnect changes for the 6.9-rc1 merge
window. The highlights are below:
Core changes:
- Constify the of_phandle_args in xlate functions.
Driver changes:
- New interconnect driver for the MSM8909 platform.
- New interconnect driver for the SM7150 platform.
- Clean-up and removal of unused resources in drivers.
- Constify some pointers to structs.
Signed-off-by: Georgi Djakov <djakov@kernel.org>
* tag 'icc-6.9-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/djakov/icc:
interconnect: qcom: Add SM7150 driver support
dt-bindings: interconnect: Add Qualcomm SM7150 DT bindings
interconnect: constify of_phandle_args in xlate
dt-bindings: interconnect: qcom,rpmh: Fix bouncing @codeaurora address
interconnect: qcom: x1e80100: constify pointer to qcom_icc_bcm
interconnect: qcom: sa8775p: constify pointer to qcom_icc_bcm
interconnect: qcom: sm6115: constify pointer to qcom_icc_node
interconnect: qcom: sm8250: constify pointer to qcom_icc_node
interconnect: qcom: sa8775p: constify pointer to qcom_icc_node
interconnect: qcom: msm8909: constify pointer to qcom_icc_node
interconnect: qcom: x1e80100: Remove bogus per-RSC BCMs and nodes
dt-bindings: interconnect: Remove bogus interconnect nodes
interconnect: qcom: sm8550: Remove bogus per-RSC BCMs and nodes
interconnect: qcom: Add MSM8909 interconnect provider driver
dt-bindings: interconnect: Add Qualcomm MSM8909 DT bindings
+3764
-1138
+3
Documentation/devicetree/bindings/interconnect/qcom,rpm.yaml
+3
Documentation/devicetree/bindings/interconnect/qcom,rpm.yaml
+1
-1
Documentation/devicetree/bindings/interconnect/qcom,rpmh.yaml
+1
-1
Documentation/devicetree/bindings/interconnect/qcom,rpmh.yaml
+84
Documentation/devicetree/bindings/interconnect/qcom,sm7150-rpmh.yaml
+84
Documentation/devicetree/bindings/interconnect/qcom,sm7150-rpmh.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/interconnect/qcom,sm7150-rpmh.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Qualcomm RPMh Network-On-Chip Interconnect on SM7150
8
+
9
+
maintainers:
10
+
- Danila Tikhonov <danila@jiaxyga.com>
11
+
12
+
description: |
13
+
RPMh interconnect providers support system bandwidth requirements through
14
+
RPMh hardware accelerators known as Bus Clock Manager (BCM).
15
+
16
+
See also:: include/dt-bindings/interconnect/qcom,sm7150-rpmh.h
17
+
18
+
allOf:
19
+
- $ref: qcom,rpmh-common.yaml#
20
+
21
+
properties:
22
+
compatible:
23
+
enum:
24
+
- qcom,sm7150-aggre1-noc
25
+
- qcom,sm7150-aggre2-noc
26
+
- qcom,sm7150-compute-noc
27
+
- qcom,sm7150-config-noc
28
+
- qcom,sm7150-dc-noc
29
+
- qcom,sm7150-gem-noc
30
+
- qcom,sm7150-mc-virt
31
+
- qcom,sm7150-mmss-noc
32
+
- qcom,sm7150-system-noc
33
+
34
+
reg:
35
+
maxItems: 1
36
+
37
+
# Child node's properties
38
+
patternProperties:
39
+
'^interconnect-[0-9]+$':
40
+
type: object
41
+
description:
42
+
The interconnect providers do not have a separate QoS register space,
43
+
but share parent's space.
44
+
45
+
allOf:
46
+
- $ref: qcom,rpmh-common.yaml#
47
+
48
+
properties:
49
+
compatible:
50
+
enum:
51
+
- qcom,sm7150-camnoc-virt
52
+
53
+
required:
54
+
- compatible
55
+
56
+
unevaluatedProperties: false
57
+
58
+
required:
59
+
- compatible
60
+
- reg
61
+
62
+
unevaluatedProperties: false
63
+
64
+
examples:
65
+
- |
66
+
mc_virt: interconnect@1380000 {
67
+
compatible = "qcom,sm7150-mc-virt";
68
+
reg = <0x01380000 0x40000>;
69
+
#interconnect-cells = <2>;
70
+
qcom,bcm-voters = <&apps_bcm_voter>;
71
+
};
72
+
73
+
system_noc: interconnect@1620000 {
74
+
compatible = "qcom,sm7150-system-noc";
75
+
reg = <0x01620000 0x40000>;
76
+
#interconnect-cells = <2>;
77
+
qcom,bcm-voters = <&apps_bcm_voter>;
78
+
79
+
camnoc_virt: interconnect-0 {
80
+
compatible = "qcom,sm7150-camnoc-virt";
81
+
#interconnect-cells = <2>;
82
+
qcom,bcm-voters = <&apps_bcm_voter>;
83
+
};
84
+
};
+2
-2
drivers/interconnect/core.c
+2
-2
drivers/interconnect/core.c
···
343
343
* an array of icc nodes specified in the icc_onecell_data struct when
344
344
* registering the provider.
345
345
*/
346
-
struct icc_node *of_icc_xlate_onecell(struct of_phandle_args *spec,
346
+
struct icc_node *of_icc_xlate_onecell(const struct of_phandle_args *spec,
347
347
void *data)
348
348
{
349
349
struct icc_onecell_data *icc_data = data;
···
368
368
* Returns a valid pointer to struct icc_node_data on success or ERR_PTR()
369
369
* on failure.
370
370
*/
371
-
struct icc_node_data *of_icc_get_from_provider(struct of_phandle_args *spec)
371
+
struct icc_node_data *of_icc_get_from_provider(const struct of_phandle_args *spec)
372
372
{
373
373
struct icc_node *node = ERR_PTR(-EPROBE_DEFER);
374
374
struct icc_node_data *data = NULL;
+18
drivers/interconnect/qcom/Kconfig
+18
drivers/interconnect/qcom/Kconfig
···
8
8
config INTERCONNECT_QCOM_BCM_VOTER
9
9
tristate
10
10
11
+
config INTERCONNECT_QCOM_MSM8909
12
+
tristate "Qualcomm MSM8909 interconnect driver"
13
+
depends on INTERCONNECT_QCOM
14
+
depends on QCOM_SMD_RPM
15
+
select INTERCONNECT_QCOM_SMD_RPM
16
+
help
17
+
This is a driver for the Qualcomm Network-on-Chip on msm8909-based
18
+
platforms.
19
+
11
20
config INTERCONNECT_QCOM_MSM8916
12
21
tristate "Qualcomm MSM8916 interconnect driver"
13
22
depends on INTERCONNECT_QCOM
···
216
207
select INTERCONNECT_QCOM_BCM_VOTER
217
208
help
218
209
This is a driver for the Qualcomm Network-on-Chip on sm6350-based
210
+
platforms.
211
+
212
+
config INTERCONNECT_QCOM_SM7150
213
+
tristate "Qualcomm SM7150 interconnect driver"
214
+
depends on INTERCONNECT_QCOM_RPMH_POSSIBLE
215
+
select INTERCONNECT_QCOM_RPMH
216
+
select INTERCONNECT_QCOM_BCM_VOTER
217
+
help
218
+
This is a driver for the Qualcomm Network-on-Chip on sm7150-based
219
219
platforms.
220
220
221
221
config INTERCONNECT_QCOM_SM8150
+4
drivers/interconnect/qcom/Makefile
+4
drivers/interconnect/qcom/Makefile
···
4
4
5
5
interconnect_qcom-y := icc-common.o
6
6
icc-bcm-voter-objs := bcm-voter.o
7
+
qnoc-msm8909-objs := msm8909.o
7
8
qnoc-msm8916-objs := msm8916.o
8
9
qnoc-msm8939-objs := msm8939.o
9
10
qnoc-msm8974-objs := msm8974.o
···
27
26
qnoc-sdx75-objs := sdx75.o
28
27
qnoc-sm6115-objs := sm6115.o
29
28
qnoc-sm6350-objs := sm6350.o
29
+
qnoc-sm7150-objs := sm7150.o
30
30
qnoc-sm8150-objs := sm8150.o
31
31
qnoc-sm8250-objs := sm8250.o
32
32
qnoc-sm8350-objs := sm8350.o
···
38
36
icc-smd-rpm-objs := smd-rpm.o icc-rpm.o icc-rpm-clocks.o
39
37
40
38
obj-$(CONFIG_INTERCONNECT_QCOM_BCM_VOTER) += icc-bcm-voter.o
39
+
obj-$(CONFIG_INTERCONNECT_QCOM_MSM8909) += qnoc-msm8909.o
41
40
obj-$(CONFIG_INTERCONNECT_QCOM_MSM8916) += qnoc-msm8916.o
42
41
obj-$(CONFIG_INTERCONNECT_QCOM_MSM8939) += qnoc-msm8939.o
43
42
obj-$(CONFIG_INTERCONNECT_QCOM_MSM8974) += qnoc-msm8974.o
···
61
58
obj-$(CONFIG_INTERCONNECT_QCOM_SDX75) += qnoc-sdx75.o
62
59
obj-$(CONFIG_INTERCONNECT_QCOM_SM6115) += qnoc-sm6115.o
63
60
obj-$(CONFIG_INTERCONNECT_QCOM_SM6350) += qnoc-sm6350.o
61
+
obj-$(CONFIG_INTERCONNECT_QCOM_SM7150) += qnoc-sm7150.o
64
62
obj-$(CONFIG_INTERCONNECT_QCOM_SM8150) += qnoc-sm8150.o
65
63
obj-$(CONFIG_INTERCONNECT_QCOM_SM8250) += qnoc-sm8250.o
66
64
obj-$(CONFIG_INTERCONNECT_QCOM_SM8350) += qnoc-sm8350.o
+2
-1
drivers/interconnect/qcom/icc-common.c
+2
-1
drivers/interconnect/qcom/icc-common.c
···
9
9
10
10
#include "icc-common.h"
11
11
12
-
struct icc_node_data *qcom_icc_xlate_extended(struct of_phandle_args *spec, void *data)
12
+
struct icc_node_data *qcom_icc_xlate_extended(const struct of_phandle_args *spec,
13
+
void *data)
13
14
{
14
15
struct icc_node_data *ndata;
15
16
struct icc_node *node;
+2
-1
drivers/interconnect/qcom/icc-common.h
+2
-1
drivers/interconnect/qcom/icc-common.h
+1329
drivers/interconnect/qcom/msm8909.c
+1329
drivers/interconnect/qcom/msm8909.c
···
1
+
// SPDX-License-Identifier: GPL-2.0-only
2
+
/*
3
+
* Based on data from msm8909-bus.dtsi in Qualcomm's msm-3.18 release:
4
+
* Copyright (c) 2014-2016, The Linux Foundation. All rights reserved.
5
+
*/
6
+
7
+
#include <linux/device.h>
8
+
#include <linux/interconnect-provider.h>
9
+
#include <linux/mod_devicetable.h>
10
+
#include <linux/module.h>
11
+
#include <linux/platform_device.h>
12
+
#include <linux/regmap.h>
13
+
14
+
#include <dt-bindings/interconnect/qcom,msm8909.h>
15
+
16
+
#include "icc-rpm.h"
17
+
18
+
enum {
19
+
QNOC_MASTER_AMPSS_M0 = 1,
20
+
QNOC_MASTER_GRAPHICS_3D,
21
+
QNOC_SNOC_BIMC_0_MAS,
22
+
QNOC_SNOC_BIMC_1_MAS,
23
+
QNOC_MASTER_TCU_0,
24
+
QNOC_MASTER_TCU_1,
25
+
QNOC_MASTER_AUDIO,
26
+
QNOC_MASTER_SPDM,
27
+
QNOC_MASTER_DEHR,
28
+
QNOC_MASTER_QPIC,
29
+
QNOC_MASTER_BLSP_1,
30
+
QNOC_MASTER_USB_HS,
31
+
QNOC_MASTER_CRYPTO_CORE0,
32
+
QNOC_MASTER_SDCC_1,
33
+
QNOC_MASTER_SDCC_2,
34
+
QNOC_SNOC_PNOC_MAS,
35
+
QNOC_MASTER_QDSS_BAM,
36
+
QNOC_BIMC_SNOC_MAS,
37
+
QNOC_MASTER_MDP_PORT0,
38
+
QNOC_PNOC_SNOC_MAS,
39
+
QNOC_MASTER_VIDEO_P0,
40
+
QNOC_MASTER_VFE,
41
+
QNOC_MASTER_QDSS_ETR,
42
+
QNOC_PNOC_M_0,
43
+
QNOC_PNOC_M_1,
44
+
QNOC_PNOC_INT_0,
45
+
QNOC_PNOC_INT_1,
46
+
QNOC_PNOC_SLV_0,
47
+
QNOC_PNOC_SLV_1,
48
+
QNOC_PNOC_SLV_2,
49
+
QNOC_PNOC_SLV_3,
50
+
QNOC_PNOC_SLV_4,
51
+
QNOC_PNOC_SLV_5,
52
+
QNOC_PNOC_SLV_7,
53
+
QNOC_SNOC_MM_INT_0,
54
+
QNOC_SNOC_MM_INT_1,
55
+
QNOC_SNOC_MM_INT_2,
56
+
QNOC_SNOC_MM_INT_BIMC,
57
+
QNOC_SNOC_QDSS_INT,
58
+
QNOC_SNOC_INT_0,
59
+
QNOC_SNOC_INT_1,
60
+
QNOC_SNOC_INT_BIMC,
61
+
QNOC_SLAVE_EBI_CH0,
62
+
QNOC_BIMC_SNOC_SLV,
63
+
QNOC_SLAVE_TCSR,
64
+
QNOC_SLAVE_SDCC_1,
65
+
QNOC_SLAVE_BLSP_1,
66
+
QNOC_SLAVE_CRYPTO_0_CFG,
67
+
QNOC_SLAVE_MESSAGE_RAM,
68
+
QNOC_SLAVE_PDM,
69
+
QNOC_SLAVE_PRNG,
70
+
QNOC_SLAVE_USB_HS,
71
+
QNOC_SLAVE_QPIC,
72
+
QNOC_SLAVE_SPDM,
73
+
QNOC_SLAVE_SDCC_2,
74
+
QNOC_SLAVE_AUDIO,
75
+
QNOC_SLAVE_DEHR_CFG,
76
+
QNOC_SLAVE_SNOC_CFG,
77
+
QNOC_SLAVE_QDSS_CFG,
78
+
QNOC_SLAVE_USB_PHYS_CFG,
79
+
QNOC_SLAVE_CAMERA_CFG,
80
+
QNOC_SLAVE_DISPLAY_CFG,
81
+
QNOC_SLAVE_VENUS_CFG,
82
+
QNOC_SLAVE_TLMM,
83
+
QNOC_SLAVE_GRAPHICS_3D_CFG,
84
+
QNOC_SLAVE_IMEM_CFG,
85
+
QNOC_SLAVE_BIMC_CFG,
86
+
QNOC_SLAVE_PMIC_ARB,
87
+
QNOC_SLAVE_TCU,
88
+
QNOC_PNOC_SNOC_SLV,
89
+
QNOC_SLAVE_APPSS,
90
+
QNOC_SNOC_BIMC_0_SLV,
91
+
QNOC_SNOC_BIMC_1_SLV,
92
+
QNOC_SLAVE_SYSTEM_IMEM,
93
+
QNOC_SNOC_PNOC_SLV,
94
+
QNOC_SLAVE_QDSS_STM,
95
+
QNOC_SLAVE_CATS_128,
96
+
QNOC_SLAVE_OCMEM_64,
97
+
};
98
+
99
+
static const u16 mas_apps_proc_links[] = {
100
+
QNOC_BIMC_SNOC_SLV,
101
+
QNOC_SLAVE_EBI_CH0
102
+
};
103
+
104
+
static struct qcom_icc_node mas_apps_proc = {
105
+
.name = "mas_apps_proc",
106
+
.id = QNOC_MASTER_AMPSS_M0,
107
+
.buswidth = 8,
108
+
.mas_rpm_id = 0,
109
+
.slv_rpm_id = -1,
110
+
.qos.ap_owned = true,
111
+
.qos.qos_mode = NOC_QOS_MODE_FIXED,
112
+
.qos.areq_prio = 0,
113
+
.qos.prio_level = 0,
114
+
.qos.qos_port = 0,
115
+
.num_links = ARRAY_SIZE(mas_apps_proc_links),
116
+
.links = mas_apps_proc_links,
117
+
};
118
+
119
+
static const u16 mas_oxili_links[] = {
120
+
QNOC_BIMC_SNOC_SLV,
121
+
QNOC_SLAVE_EBI_CH0
122
+
};
123
+
124
+
static struct qcom_icc_node mas_oxili = {
125
+
.name = "mas_oxili",
126
+
.id = QNOC_MASTER_GRAPHICS_3D,
127
+
.buswidth = 8,
128
+
.mas_rpm_id = 6,
129
+
.slv_rpm_id = -1,
130
+
.qos.ap_owned = true,
131
+
.qos.qos_mode = NOC_QOS_MODE_FIXED,
132
+
.qos.areq_prio = 0,
133
+
.qos.prio_level = 0,
134
+
.qos.qos_port = 2,
135
+
.num_links = ARRAY_SIZE(mas_oxili_links),
136
+
.links = mas_oxili_links,
137
+
};
138
+
139
+
static const u16 mas_snoc_bimc_0_links[] = {
140
+
QNOC_SLAVE_EBI_CH0
141
+
};
142
+
143
+
static struct qcom_icc_node mas_snoc_bimc_0 = {
144
+
.name = "mas_snoc_bimc_0",
145
+
.id = QNOC_SNOC_BIMC_0_MAS,
146
+
.buswidth = 8,
147
+
.mas_rpm_id = 3,
148
+
.slv_rpm_id = -1,
149
+
.qos.qos_mode = NOC_QOS_MODE_BYPASS,
150
+
.qos.areq_prio = 0,
151
+
.qos.prio_level = 0,
152
+
.qos.qos_port = 3,
153
+
.num_links = ARRAY_SIZE(mas_snoc_bimc_0_links),
154
+
.links = mas_snoc_bimc_0_links,
155
+
};
156
+
157
+
static const u16 mas_snoc_bimc_1_links[] = {
158
+
QNOC_SLAVE_EBI_CH0
159
+
};
160
+
161
+
static struct qcom_icc_node mas_snoc_bimc_1 = {
162
+
.name = "mas_snoc_bimc_1",
163
+
.id = QNOC_SNOC_BIMC_1_MAS,
164
+
.buswidth = 8,
165
+
.mas_rpm_id = 76,
166
+
.slv_rpm_id = -1,
167
+
.qos.ap_owned = true,
168
+
.qos.qos_mode = NOC_QOS_MODE_BYPASS,
169
+
.qos.areq_prio = 0,
170
+
.qos.prio_level = 0,
171
+
.qos.qos_port = 4,
172
+
.num_links = ARRAY_SIZE(mas_snoc_bimc_1_links),
173
+
.links = mas_snoc_bimc_1_links,
174
+
};
175
+
176
+
static const u16 mas_tcu_0_links[] = {
177
+
QNOC_BIMC_SNOC_SLV,
178
+
QNOC_SLAVE_EBI_CH0
179
+
};
180
+
181
+
static struct qcom_icc_node mas_tcu_0 = {
182
+
.name = "mas_tcu_0",
183
+
.id = QNOC_MASTER_TCU_0,
184
+
.buswidth = 8,
185
+
.mas_rpm_id = 102,
186
+
.slv_rpm_id = -1,
187
+
.qos.ap_owned = true,
188
+
.qos.qos_mode = NOC_QOS_MODE_FIXED,
189
+
.qos.areq_prio = 0,
190
+
.qos.prio_level = 2,
191
+
.qos.qos_port = 5,
192
+
.num_links = ARRAY_SIZE(mas_tcu_0_links),
193
+
.links = mas_tcu_0_links,
194
+
};
195
+
196
+
static const u16 mas_tcu_1_links[] = {
197
+
QNOC_BIMC_SNOC_SLV,
198
+
QNOC_SLAVE_EBI_CH0
199
+
};
200
+
201
+
static struct qcom_icc_node mas_tcu_1 = {
202
+
.name = "mas_tcu_1",
203
+
.id = QNOC_MASTER_TCU_1,
204
+
.buswidth = 8,
205
+
.mas_rpm_id = 103,
206
+
.slv_rpm_id = -1,
207
+
.qos.ap_owned = true,
208
+
.qos.qos_mode = NOC_QOS_MODE_FIXED,
209
+
.qos.areq_prio = 0,
210
+
.qos.prio_level = 2,
211
+
.qos.qos_port = 6,
212
+
.num_links = ARRAY_SIZE(mas_tcu_1_links),
213
+
.links = mas_tcu_1_links,
214
+
};
215
+
216
+
static const u16 mas_audio_links[] = {
217
+
QNOC_PNOC_M_0
218
+
};
219
+
220
+
static struct qcom_icc_node mas_audio = {
221
+
.name = "mas_audio",
222
+
.id = QNOC_MASTER_AUDIO,
223
+
.buswidth = 4,
224
+
.mas_rpm_id = 78,
225
+
.slv_rpm_id = -1,
226
+
.num_links = ARRAY_SIZE(mas_audio_links),
227
+
.links = mas_audio_links,
228
+
};
229
+
230
+
static const u16 mas_spdm_links[] = {
231
+
QNOC_PNOC_M_0
232
+
};
233
+
234
+
static struct qcom_icc_node mas_spdm = {
235
+
.name = "mas_spdm",
236
+
.id = QNOC_MASTER_SPDM,
237
+
.buswidth = 4,
238
+
.mas_rpm_id = 50,
239
+
.slv_rpm_id = -1,
240
+
.num_links = ARRAY_SIZE(mas_spdm_links),
241
+
.links = mas_spdm_links,
242
+
};
243
+
244
+
static const u16 mas_dehr_links[] = {
245
+
QNOC_PNOC_M_0
246
+
};
247
+
248
+
static struct qcom_icc_node mas_dehr = {
249
+
.name = "mas_dehr",
250
+
.id = QNOC_MASTER_DEHR,
251
+
.buswidth = 4,
252
+
.mas_rpm_id = 48,
253
+
.slv_rpm_id = -1,
254
+
.num_links = ARRAY_SIZE(mas_dehr_links),
255
+
.links = mas_dehr_links,
256
+
};
257
+
258
+
static const u16 mas_qpic_links[] = {
259
+
QNOC_PNOC_M_0
260
+
};
261
+
262
+
static struct qcom_icc_node mas_qpic = {
263
+
.name = "mas_qpic",
264
+
.id = QNOC_MASTER_QPIC,
265
+
.buswidth = 4,
266
+
.mas_rpm_id = 58,
267
+
.slv_rpm_id = -1,
268
+
.num_links = ARRAY_SIZE(mas_qpic_links),
269
+
.links = mas_qpic_links,
270
+
};
271
+
272
+
static const u16 mas_blsp_1_links[] = {
273
+
QNOC_PNOC_M_1
274
+
};
275
+
276
+
static struct qcom_icc_node mas_blsp_1 = {
277
+
.name = "mas_blsp_1",
278
+
.id = QNOC_MASTER_BLSP_1,
279
+
.buswidth = 4,
280
+
.mas_rpm_id = 41,
281
+
.slv_rpm_id = -1,
282
+
.num_links = ARRAY_SIZE(mas_blsp_1_links),
283
+
.links = mas_blsp_1_links,
284
+
};
285
+
286
+
static const u16 mas_usb_hs_links[] = {
287
+
QNOC_PNOC_M_1
288
+
};
289
+
290
+
static struct qcom_icc_node mas_usb_hs = {
291
+
.name = "mas_usb_hs",
292
+
.id = QNOC_MASTER_USB_HS,
293
+
.buswidth = 4,
294
+
.mas_rpm_id = 42,
295
+
.slv_rpm_id = -1,
296
+
.num_links = ARRAY_SIZE(mas_usb_hs_links),
297
+
.links = mas_usb_hs_links,
298
+
};
299
+
300
+
static const u16 mas_crypto_links[] = {
301
+
QNOC_PNOC_INT_1
302
+
};
303
+
304
+
static struct qcom_icc_node mas_crypto = {
305
+
.name = "mas_crypto",
306
+
.id = QNOC_MASTER_CRYPTO_CORE0,
307
+
.buswidth = 8,
308
+
.mas_rpm_id = 23,
309
+
.slv_rpm_id = -1,
310
+
.qos.ap_owned = true,
311
+
.qos.qos_mode = NOC_QOS_MODE_FIXED,
312
+
.qos.areq_prio = 0,
313
+
.qos.prio_level = 0,
314
+
.qos.qos_port = 0,
315
+
.num_links = ARRAY_SIZE(mas_crypto_links),
316
+
.links = mas_crypto_links,
317
+
};
318
+
319
+
static const u16 mas_sdcc_1_links[] = {
320
+
QNOC_PNOC_INT_1
321
+
};
322
+
323
+
static struct qcom_icc_node mas_sdcc_1 = {
324
+
.name = "mas_sdcc_1",
325
+
.id = QNOC_MASTER_SDCC_1,
326
+
.buswidth = 8,
327
+
.mas_rpm_id = 33,
328
+
.slv_rpm_id = -1,
329
+
.qos.qos_mode = NOC_QOS_MODE_FIXED,
330
+
.qos.areq_prio = 0,
331
+
.qos.prio_level = 0,
332
+
.qos.qos_port = 7,
333
+
.num_links = ARRAY_SIZE(mas_sdcc_1_links),
334
+
.links = mas_sdcc_1_links,
335
+
};
336
+
337
+
static const u16 mas_sdcc_2_links[] = {
338
+
QNOC_PNOC_INT_1
339
+
};
340
+
341
+
static struct qcom_icc_node mas_sdcc_2 = {
342
+
.name = "mas_sdcc_2",
343
+
.id = QNOC_MASTER_SDCC_2,
344
+
.buswidth = 8,
345
+
.mas_rpm_id = 35,
346
+
.slv_rpm_id = -1,
347
+
.qos.qos_mode = NOC_QOS_MODE_FIXED,
348
+
.qos.areq_prio = 0,
349
+
.qos.prio_level = 0,
350
+
.qos.qos_port = 8,
351
+
.num_links = ARRAY_SIZE(mas_sdcc_2_links),
352
+
.links = mas_sdcc_2_links,
353
+
};
354
+
355
+
static const u16 mas_snoc_pcnoc_links[] = {
356
+
QNOC_PNOC_INT_0
357
+
};
358
+
359
+
static struct qcom_icc_node mas_snoc_pcnoc = {
360
+
.name = "mas_snoc_pcnoc",
361
+
.id = QNOC_SNOC_PNOC_MAS,
362
+
.buswidth = 8,
363
+
.mas_rpm_id = 77,
364
+
.slv_rpm_id = -1,
365
+
.qos.qos_mode = NOC_QOS_MODE_FIXED,
366
+
.qos.areq_prio = 0,
367
+
.qos.prio_level = 0,
368
+
.qos.qos_port = 9,
369
+
.num_links = ARRAY_SIZE(mas_snoc_pcnoc_links),
370
+
.links = mas_snoc_pcnoc_links,
371
+
};
372
+
373
+
static const u16 mas_qdss_bam_links[] = {
374
+
QNOC_SNOC_QDSS_INT
375
+
};
376
+
377
+
static struct qcom_icc_node mas_qdss_bam = {
378
+
.name = "mas_qdss_bam",
379
+
.id = QNOC_MASTER_QDSS_BAM,
380
+
.buswidth = 4,
381
+
.mas_rpm_id = 19,
382
+
.slv_rpm_id = -1,
383
+
.qos.ap_owned = true,
384
+
.qos.qos_mode = NOC_QOS_MODE_FIXED,
385
+
.qos.areq_prio = 1,
386
+
.qos.prio_level = 1,
387
+
.qos.qos_port = 11,
388
+
.num_links = ARRAY_SIZE(mas_qdss_bam_links),
389
+
.links = mas_qdss_bam_links,
390
+
};
391
+
392
+
static const u16 mas_bimc_snoc_links[] = {
393
+
QNOC_SNOC_INT_0,
394
+
QNOC_SNOC_INT_1
395
+
};
396
+
397
+
static struct qcom_icc_node mas_bimc_snoc = {
398
+
.name = "mas_bimc_snoc",
399
+
.id = QNOC_BIMC_SNOC_MAS,
400
+
.buswidth = 8,
401
+
.mas_rpm_id = 21,
402
+
.slv_rpm_id = -1,
403
+
.num_links = ARRAY_SIZE(mas_bimc_snoc_links),
404
+
.links = mas_bimc_snoc_links,
405
+
};
406
+
407
+
static const u16 mas_mdp_links[] = {
408
+
QNOC_SNOC_MM_INT_1,
409
+
QNOC_SNOC_MM_INT_2
410
+
};
411
+
412
+
static struct qcom_icc_node mas_mdp = {
413
+
.name = "mas_mdp",
414
+
.id = QNOC_MASTER_MDP_PORT0,
415
+
.buswidth = 16,
416
+
.mas_rpm_id = 8,
417
+
.slv_rpm_id = -1,
418
+
.qos.ap_owned = true,
419
+
.qos.qos_mode = NOC_QOS_MODE_BYPASS,
420
+
.qos.areq_prio = 0,
421
+
.qos.prio_level = 0,
422
+
.qos.qos_port = 7,
423
+
.num_links = ARRAY_SIZE(mas_mdp_links),
424
+
.links = mas_mdp_links,
425
+
.ab_coeff = 167,
426
+
};
427
+
428
+
static const u16 mas_pcnoc_snoc_links[] = {
429
+
QNOC_SNOC_INT_0,
430
+
QNOC_SNOC_INT_1,
431
+
QNOC_SNOC_INT_BIMC
432
+
};
433
+
434
+
static struct qcom_icc_node mas_pcnoc_snoc = {
435
+
.name = "mas_pcnoc_snoc",
436
+
.id = QNOC_PNOC_SNOC_MAS,
437
+
.buswidth = 8,
438
+
.mas_rpm_id = 29,
439
+
.slv_rpm_id = -1,
440
+
.qos.qos_mode = NOC_QOS_MODE_FIXED,
441
+
.qos.areq_prio = 0,
442
+
.qos.prio_level = 0,
443
+
.qos.qos_port = 5,
444
+
.num_links = ARRAY_SIZE(mas_pcnoc_snoc_links),
445
+
.links = mas_pcnoc_snoc_links,
446
+
};
447
+
448
+
static const u16 mas_venus_links[] = {
449
+
QNOC_SNOC_MM_INT_0,
450
+
QNOC_SNOC_MM_INT_2
451
+
};
452
+
453
+
static struct qcom_icc_node mas_venus = {
454
+
.name = "mas_venus",
455
+
.id = QNOC_MASTER_VIDEO_P0,
456
+
.buswidth = 16,
457
+
.mas_rpm_id = 9,
458
+
.slv_rpm_id = -1,
459
+
.qos.ap_owned = true,
460
+
.qos.qos_mode = NOC_QOS_MODE_BYPASS,
461
+
.qos.areq_prio = 0,
462
+
.qos.prio_level = 0,
463
+
.qos.qos_port = 8,
464
+
.num_links = ARRAY_SIZE(mas_venus_links),
465
+
.links = mas_venus_links,
466
+
.ab_coeff = 167,
467
+
};
468
+
469
+
static const u16 mas_vfe_links[] = {
470
+
QNOC_SNOC_MM_INT_1,
471
+
QNOC_SNOC_MM_INT_2
472
+
};
473
+
474
+
static struct qcom_icc_node mas_vfe = {
475
+
.name = "mas_vfe",
476
+
.id = QNOC_MASTER_VFE,
477
+
.buswidth = 16,
478
+
.mas_rpm_id = 11,
479
+
.slv_rpm_id = -1,
480
+
.qos.ap_owned = true,
481
+
.qos.qos_mode = NOC_QOS_MODE_BYPASS,
482
+
.qos.areq_prio = 0,
483
+
.qos.prio_level = 0,
484
+
.qos.qos_port = 9,
485
+
.num_links = ARRAY_SIZE(mas_vfe_links),
486
+
.links = mas_vfe_links,
487
+
.ab_coeff = 167,
488
+
};
489
+
490
+
static const u16 mas_qdss_etr_links[] = {
491
+
QNOC_SNOC_QDSS_INT
492
+
};
493
+
494
+
static struct qcom_icc_node mas_qdss_etr = {
495
+
.name = "mas_qdss_etr",
496
+
.id = QNOC_MASTER_QDSS_ETR,
497
+
.buswidth = 8,
498
+
.mas_rpm_id = 31,
499
+
.slv_rpm_id = -1,
500
+
.qos.ap_owned = true,
501
+
.qos.qos_mode = NOC_QOS_MODE_FIXED,
502
+
.qos.areq_prio = 1,
503
+
.qos.prio_level = 1,
504
+
.qos.qos_port = 10,
505
+
.num_links = ARRAY_SIZE(mas_qdss_etr_links),
506
+
.links = mas_qdss_etr_links,
507
+
};
508
+
509
+
static const u16 pcnoc_m_0_links[] = {
510
+
QNOC_PNOC_SNOC_SLV
511
+
};
512
+
513
+
static struct qcom_icc_node pcnoc_m_0 = {
514
+
.name = "pcnoc_m_0",
515
+
.id = QNOC_PNOC_M_0,
516
+
.buswidth = 8,
517
+
.mas_rpm_id = 87,
518
+
.slv_rpm_id = 116,
519
+
.qos.qos_mode = NOC_QOS_MODE_BYPASS,
520
+
.qos.areq_prio = 0,
521
+
.qos.prio_level = 0,
522
+
.qos.qos_port = 5,
523
+
.num_links = ARRAY_SIZE(pcnoc_m_0_links),
524
+
.links = pcnoc_m_0_links,
525
+
};
526
+
527
+
static const u16 pcnoc_m_1_links[] = {
528
+
QNOC_PNOC_SNOC_SLV
529
+
};
530
+
531
+
static struct qcom_icc_node pcnoc_m_1 = {
532
+
.name = "pcnoc_m_1",
533
+
.id = QNOC_PNOC_M_1,
534
+
.buswidth = 8,
535
+
.mas_rpm_id = 88,
536
+
.slv_rpm_id = 117,
537
+
.qos.qos_mode = NOC_QOS_MODE_FIXED,
538
+
.qos.areq_prio = 0,
539
+
.qos.prio_level = 0,
540
+
.qos.qos_port = 6,
541
+
.num_links = ARRAY_SIZE(pcnoc_m_1_links),
542
+
.links = pcnoc_m_1_links,
543
+
};
544
+
545
+
static const u16 pcnoc_int_0_links[] = {
546
+
QNOC_PNOC_SLV_3,
547
+
QNOC_PNOC_SLV_2,
548
+
QNOC_PNOC_SLV_1,
549
+
QNOC_PNOC_SLV_0,
550
+
QNOC_PNOC_SLV_7,
551
+
QNOC_PNOC_SLV_5,
552
+
QNOC_PNOC_SLV_4,
553
+
QNOC_SLAVE_TCU
554
+
};
555
+
556
+
static struct qcom_icc_node pcnoc_int_0 = {
557
+
.name = "pcnoc_int_0",
558
+
.id = QNOC_PNOC_INT_0,
559
+
.buswidth = 8,
560
+
.mas_rpm_id = 85,
561
+
.slv_rpm_id = 114,
562
+
.num_links = ARRAY_SIZE(pcnoc_int_0_links),
563
+
.links = pcnoc_int_0_links,
564
+
};
565
+
566
+
static const u16 pcnoc_int_1_links[] = {
567
+
QNOC_PNOC_SNOC_SLV
568
+
};
569
+
570
+
static struct qcom_icc_node pcnoc_int_1 = {
571
+
.name = "pcnoc_int_1",
572
+
.id = QNOC_PNOC_INT_1,
573
+
.buswidth = 8,
574
+
.mas_rpm_id = 86,
575
+
.slv_rpm_id = 115,
576
+
.num_links = ARRAY_SIZE(pcnoc_int_1_links),
577
+
.links = pcnoc_int_1_links,
578
+
};
579
+
580
+
static const u16 pcnoc_s_0_links[] = {
581
+
QNOC_SLAVE_SDCC_1,
582
+
QNOC_SLAVE_TCSR,
583
+
QNOC_SLAVE_BLSP_1
584
+
};
585
+
586
+
static struct qcom_icc_node pcnoc_s_0 = {
587
+
.name = "pcnoc_s_0",
588
+
.id = QNOC_PNOC_SLV_0,
589
+
.buswidth = 4,
590
+
.mas_rpm_id = 89,
591
+
.slv_rpm_id = 118,
592
+
.num_links = ARRAY_SIZE(pcnoc_s_0_links),
593
+
.links = pcnoc_s_0_links,
594
+
};
595
+
596
+
static const u16 pcnoc_s_1_links[] = {
597
+
QNOC_SLAVE_MESSAGE_RAM,
598
+
QNOC_SLAVE_CRYPTO_0_CFG,
599
+
QNOC_SLAVE_USB_HS,
600
+
QNOC_SLAVE_PDM,
601
+
QNOC_SLAVE_PRNG,
602
+
QNOC_SLAVE_QPIC
603
+
};
604
+
605
+
static struct qcom_icc_node pcnoc_s_1 = {
606
+
.name = "pcnoc_s_1",
607
+
.id = QNOC_PNOC_SLV_1,
608
+
.buswidth = 4,
609
+
.mas_rpm_id = 90,
610
+
.slv_rpm_id = 119,
611
+
.num_links = ARRAY_SIZE(pcnoc_s_1_links),
612
+
.links = pcnoc_s_1_links,
613
+
};
614
+
615
+
static const u16 pcnoc_s_2_links[] = {
616
+
QNOC_SLAVE_SPDM,
617
+
QNOC_SLAVE_SDCC_2,
618
+
QNOC_SLAVE_AUDIO,
619
+
QNOC_SLAVE_DEHR_CFG
620
+
};
621
+
622
+
static struct qcom_icc_node pcnoc_s_2 = {
623
+
.name = "pcnoc_s_2",
624
+
.id = QNOC_PNOC_SLV_2,
625
+
.buswidth = 4,
626
+
.mas_rpm_id = 91,
627
+
.slv_rpm_id = 120,
628
+
.num_links = ARRAY_SIZE(pcnoc_s_2_links),
629
+
.links = pcnoc_s_2_links,
630
+
};
631
+
632
+
static const u16 pcnoc_s_3_links[] = {
633
+
QNOC_SLAVE_QDSS_CFG,
634
+
QNOC_SLAVE_USB_PHYS_CFG,
635
+
QNOC_SLAVE_SNOC_CFG
636
+
};
637
+
638
+
static struct qcom_icc_node pcnoc_s_3 = {
639
+
.name = "pcnoc_s_3",
640
+
.id = QNOC_PNOC_SLV_3,
641
+
.buswidth = 4,
642
+
.mas_rpm_id = 92,
643
+
.slv_rpm_id = 121,
644
+
.num_links = ARRAY_SIZE(pcnoc_s_3_links),
645
+
.links = pcnoc_s_3_links,
646
+
};
647
+
648
+
static const u16 pcnoc_s_4_links[] = {
649
+
QNOC_SLAVE_CAMERA_CFG,
650
+
QNOC_SLAVE_DISPLAY_CFG,
651
+
QNOC_SLAVE_VENUS_CFG
652
+
};
653
+
654
+
static struct qcom_icc_node pcnoc_s_4 = {
655
+
.name = "pcnoc_s_4",
656
+
.id = QNOC_PNOC_SLV_4,
657
+
.buswidth = 4,
658
+
.mas_rpm_id = 93,
659
+
.slv_rpm_id = 122,
660
+
.qos.ap_owned = true,
661
+
.qos.qos_mode = NOC_QOS_MODE_INVALID,
662
+
.num_links = ARRAY_SIZE(pcnoc_s_4_links),
663
+
.links = pcnoc_s_4_links,
664
+
};
665
+
666
+
static const u16 pcnoc_s_5_links[] = {
667
+
QNOC_SLAVE_TLMM
668
+
};
669
+
670
+
static struct qcom_icc_node pcnoc_s_5 = {
671
+
.name = "pcnoc_s_5",
672
+
.id = QNOC_PNOC_SLV_5,
673
+
.buswidth = 4,
674
+
.mas_rpm_id = 129,
675
+
.slv_rpm_id = 189,
676
+
.num_links = ARRAY_SIZE(pcnoc_s_5_links),
677
+
.links = pcnoc_s_5_links,
678
+
};
679
+
680
+
static const u16 pcnoc_s_7_links[] = {
681
+
QNOC_SLAVE_GRAPHICS_3D_CFG,
682
+
QNOC_SLAVE_IMEM_CFG,
683
+
QNOC_SLAVE_BIMC_CFG,
684
+
QNOC_SLAVE_PMIC_ARB
685
+
};
686
+
687
+
static struct qcom_icc_node pcnoc_s_7 = {
688
+
.name = "pcnoc_s_7",
689
+
.id = QNOC_PNOC_SLV_7,
690
+
.buswidth = 4,
691
+
.mas_rpm_id = 95,
692
+
.slv_rpm_id = 124,
693
+
.num_links = ARRAY_SIZE(pcnoc_s_7_links),
694
+
.links = pcnoc_s_7_links,
695
+
};
696
+
697
+
static const u16 mm_int_0_links[] = {
698
+
QNOC_SNOC_MM_INT_BIMC
699
+
};
700
+
701
+
static struct qcom_icc_node mm_int_0 = {
702
+
.name = "mm_int_0",
703
+
.id = QNOC_SNOC_MM_INT_0,
704
+
.buswidth = 16,
705
+
.mas_rpm_id = 79,
706
+
.slv_rpm_id = 108,
707
+
.qos.ap_owned = true,
708
+
.qos.qos_mode = NOC_QOS_MODE_INVALID,
709
+
.num_links = ARRAY_SIZE(mm_int_0_links),
710
+
.links = mm_int_0_links,
711
+
.ab_coeff = 167,
712
+
};
713
+
714
+
static const u16 mm_int_1_links[] = {
715
+
QNOC_SNOC_MM_INT_BIMC
716
+
};
717
+
718
+
static struct qcom_icc_node mm_int_1 = {
719
+
.name = "mm_int_1",
720
+
.id = QNOC_SNOC_MM_INT_1,
721
+
.buswidth = 16,
722
+
.mas_rpm_id = 80,
723
+
.slv_rpm_id = 109,
724
+
.qos.ap_owned = true,
725
+
.qos.qos_mode = NOC_QOS_MODE_INVALID,
726
+
.num_links = ARRAY_SIZE(mm_int_1_links),
727
+
.links = mm_int_1_links,
728
+
.ab_coeff = 167,
729
+
};
730
+
731
+
static const u16 mm_int_2_links[] = {
732
+
QNOC_SNOC_INT_0
733
+
};
734
+
735
+
static struct qcom_icc_node mm_int_2 = {
736
+
.name = "mm_int_2",
737
+
.id = QNOC_SNOC_MM_INT_2,
738
+
.buswidth = 16,
739
+
.mas_rpm_id = 81,
740
+
.slv_rpm_id = 110,
741
+
.qos.ap_owned = true,
742
+
.qos.qos_mode = NOC_QOS_MODE_INVALID,
743
+
.num_links = ARRAY_SIZE(mm_int_2_links),
744
+
.links = mm_int_2_links,
745
+
.ab_coeff = 167,
746
+
};
747
+
748
+
static const u16 mm_int_bimc_links[] = {
749
+
QNOC_SNOC_BIMC_1_SLV
750
+
};
751
+
752
+
static struct qcom_icc_node mm_int_bimc = {
753
+
.name = "mm_int_bimc",
754
+
.id = QNOC_SNOC_MM_INT_BIMC,
755
+
.buswidth = 16,
756
+
.mas_rpm_id = 82,
757
+
.slv_rpm_id = 111,
758
+
.qos.ap_owned = true,
759
+
.qos.qos_mode = NOC_QOS_MODE_INVALID,
760
+
.num_links = ARRAY_SIZE(mm_int_bimc_links),
761
+
.links = mm_int_bimc_links,
762
+
.ab_coeff = 167,
763
+
};
764
+
765
+
static const u16 qdss_int_links[] = {
766
+
QNOC_SNOC_INT_0,
767
+
QNOC_SNOC_INT_BIMC
768
+
};
769
+
770
+
static struct qcom_icc_node qdss_int = {
771
+
.name = "qdss_int",
772
+
.id = QNOC_SNOC_QDSS_INT,
773
+
.buswidth = 8,
774
+
.mas_rpm_id = 98,
775
+
.slv_rpm_id = 128,
776
+
.qos.ap_owned = true,
777
+
.qos.qos_mode = NOC_QOS_MODE_INVALID,
778
+
.num_links = ARRAY_SIZE(qdss_int_links),
779
+
.links = qdss_int_links,
780
+
};
781
+
782
+
static const u16 snoc_int_0_links[] = {
783
+
QNOC_SLAVE_SYSTEM_IMEM,
784
+
QNOC_SLAVE_QDSS_STM,
785
+
QNOC_SNOC_PNOC_SLV
786
+
};
787
+
788
+
static struct qcom_icc_node snoc_int_0 = {
789
+
.name = "snoc_int_0",
790
+
.id = QNOC_SNOC_INT_0,
791
+
.buswidth = 8,
792
+
.mas_rpm_id = 99,
793
+
.slv_rpm_id = 130,
794
+
.num_links = ARRAY_SIZE(snoc_int_0_links),
795
+
.links = snoc_int_0_links,
796
+
};
797
+
798
+
static const u16 snoc_int_1_links[] = {
799
+
QNOC_SLAVE_CATS_128,
800
+
QNOC_SLAVE_APPSS,
801
+
QNOC_SLAVE_OCMEM_64
802
+
};
803
+
804
+
static struct qcom_icc_node snoc_int_1 = {
805
+
.name = "snoc_int_1",
806
+
.id = QNOC_SNOC_INT_1,
807
+
.buswidth = 8,
808
+
.mas_rpm_id = 100,
809
+
.slv_rpm_id = 131,
810
+
.qos.ap_owned = true,
811
+
.qos.qos_mode = NOC_QOS_MODE_INVALID,
812
+
.num_links = ARRAY_SIZE(snoc_int_1_links),
813
+
.links = snoc_int_1_links,
814
+
};
815
+
816
+
static const u16 snoc_int_bimc_links[] = {
817
+
QNOC_SNOC_BIMC_0_SLV
818
+
};
819
+
820
+
static struct qcom_icc_node snoc_int_bimc = {
821
+
.name = "snoc_int_bimc",
822
+
.id = QNOC_SNOC_INT_BIMC,
823
+
.buswidth = 8,
824
+
.mas_rpm_id = 101,
825
+
.slv_rpm_id = 132,
826
+
.num_links = ARRAY_SIZE(snoc_int_bimc_links),
827
+
.links = snoc_int_bimc_links,
828
+
};
829
+
830
+
static struct qcom_icc_node slv_ebi = {
831
+
.name = "slv_ebi",
832
+
.id = QNOC_SLAVE_EBI_CH0,
833
+
.buswidth = 8,
834
+
.mas_rpm_id = -1,
835
+
.slv_rpm_id = 0,
836
+
};
837
+
838
+
static const u16 slv_bimc_snoc_links[] = {
839
+
QNOC_BIMC_SNOC_MAS
840
+
};
841
+
842
+
static struct qcom_icc_node slv_bimc_snoc = {
843
+
.name = "slv_bimc_snoc",
844
+
.id = QNOC_BIMC_SNOC_SLV,
845
+
.buswidth = 8,
846
+
.mas_rpm_id = -1,
847
+
.slv_rpm_id = 2,
848
+
.num_links = ARRAY_SIZE(slv_bimc_snoc_links),
849
+
.links = slv_bimc_snoc_links,
850
+
};
851
+
852
+
static struct qcom_icc_node slv_tcsr = {
853
+
.name = "slv_tcsr",
854
+
.id = QNOC_SLAVE_TCSR,
855
+
.buswidth = 4,
856
+
.mas_rpm_id = -1,
857
+
.slv_rpm_id = 50,
858
+
};
859
+
860
+
static struct qcom_icc_node slv_sdcc_1 = {
861
+
.name = "slv_sdcc_1",
862
+
.id = QNOC_SLAVE_SDCC_1,
863
+
.buswidth = 4,
864
+
.mas_rpm_id = -1,
865
+
.slv_rpm_id = 31,
866
+
};
867
+
868
+
static struct qcom_icc_node slv_blsp_1 = {
869
+
.name = "slv_blsp_1",
870
+
.id = QNOC_SLAVE_BLSP_1,
871
+
.buswidth = 4,
872
+
.mas_rpm_id = -1,
873
+
.slv_rpm_id = 39,
874
+
};
875
+
876
+
static struct qcom_icc_node slv_crypto_0_cfg = {
877
+
.name = "slv_crypto_0_cfg",
878
+
.id = QNOC_SLAVE_CRYPTO_0_CFG,
879
+
.buswidth = 4,
880
+
.mas_rpm_id = -1,
881
+
.slv_rpm_id = 52,
882
+
.qos.ap_owned = true,
883
+
.qos.qos_mode = NOC_QOS_MODE_INVALID,
884
+
};
885
+
886
+
static struct qcom_icc_node slv_message_ram = {
887
+
.name = "slv_message_ram",
888
+
.id = QNOC_SLAVE_MESSAGE_RAM,
889
+
.buswidth = 4,
890
+
.mas_rpm_id = -1,
891
+
.slv_rpm_id = 55,
892
+
};
893
+
894
+
static struct qcom_icc_node slv_pdm = {
895
+
.name = "slv_pdm",
896
+
.id = QNOC_SLAVE_PDM,
897
+
.buswidth = 4,
898
+
.mas_rpm_id = -1,
899
+
.slv_rpm_id = 41,
900
+
};
901
+
902
+
static struct qcom_icc_node slv_prng = {
903
+
.name = "slv_prng",
904
+
.id = QNOC_SLAVE_PRNG,
905
+
.buswidth = 4,
906
+
.mas_rpm_id = -1,
907
+
.slv_rpm_id = 44,
908
+
.qos.ap_owned = true,
909
+
.qos.qos_mode = NOC_QOS_MODE_INVALID,
910
+
};
911
+
912
+
static struct qcom_icc_node slv_usb_hs = {
913
+
.name = "slv_usb_hs",
914
+
.id = QNOC_SLAVE_USB_HS,
915
+
.buswidth = 4,
916
+
.mas_rpm_id = -1,
917
+
.slv_rpm_id = 40,
918
+
};
919
+
920
+
static struct qcom_icc_node slv_qpic = {
921
+
.name = "slv_qpic",
922
+
.id = QNOC_SLAVE_QPIC,
923
+
.buswidth = 4,
924
+
.mas_rpm_id = -1,
925
+
.slv_rpm_id = 80,
926
+
};
927
+
928
+
static struct qcom_icc_node slv_spdm = {
929
+
.name = "slv_spdm",
930
+
.id = QNOC_SLAVE_SPDM,
931
+
.buswidth = 4,
932
+
.mas_rpm_id = -1,
933
+
.slv_rpm_id = 60,
934
+
};
935
+
936
+
static struct qcom_icc_node slv_sdcc_2 = {
937
+
.name = "slv_sdcc_2",
938
+
.id = QNOC_SLAVE_SDCC_2,
939
+
.buswidth = 4,
940
+
.mas_rpm_id = -1,
941
+
.slv_rpm_id = 33,
942
+
};
943
+
944
+
static struct qcom_icc_node slv_audio = {
945
+
.name = "slv_audio",
946
+
.id = QNOC_SLAVE_AUDIO,
947
+
.buswidth = 4,
948
+
.mas_rpm_id = -1,
949
+
.slv_rpm_id = 105,
950
+
};
951
+
952
+
static struct qcom_icc_node slv_dehr_cfg = {
953
+
.name = "slv_dehr_cfg",
954
+
.id = QNOC_SLAVE_DEHR_CFG,
955
+
.buswidth = 4,
956
+
.mas_rpm_id = -1,
957
+
.slv_rpm_id = 61,
958
+
};
959
+
960
+
static struct qcom_icc_node slv_snoc_cfg = {
961
+
.name = "slv_snoc_cfg",
962
+
.id = QNOC_SLAVE_SNOC_CFG,
963
+
.buswidth = 4,
964
+
.mas_rpm_id = -1,
965
+
.slv_rpm_id = 70,
966
+
};
967
+
968
+
static struct qcom_icc_node slv_qdss_cfg = {
969
+
.name = "slv_qdss_cfg",
970
+
.id = QNOC_SLAVE_QDSS_CFG,
971
+
.buswidth = 4,
972
+
.mas_rpm_id = -1,
973
+
.slv_rpm_id = 63,
974
+
};
975
+
976
+
static struct qcom_icc_node slv_usb_phy = {
977
+
.name = "slv_usb_phy",
978
+
.id = QNOC_SLAVE_USB_PHYS_CFG,
979
+
.buswidth = 4,
980
+
.mas_rpm_id = -1,
981
+
.slv_rpm_id = 95,
982
+
};
983
+
984
+
static struct qcom_icc_node slv_camera_ss_cfg = {
985
+
.name = "slv_camera_ss_cfg",
986
+
.id = QNOC_SLAVE_CAMERA_CFG,
987
+
.buswidth = 4,
988
+
.mas_rpm_id = -1,
989
+
.slv_rpm_id = 3,
990
+
.qos.ap_owned = true,
991
+
.qos.qos_mode = NOC_QOS_MODE_INVALID,
992
+
};
993
+
994
+
static struct qcom_icc_node slv_disp_ss_cfg = {
995
+
.name = "slv_disp_ss_cfg",
996
+
.id = QNOC_SLAVE_DISPLAY_CFG,
997
+
.buswidth = 4,
998
+
.mas_rpm_id = -1,
999
+
.slv_rpm_id = 4,
1000
+
.qos.ap_owned = true,
1001
+
.qos.qos_mode = NOC_QOS_MODE_INVALID,
1002
+
};
1003
+
1004
+
static struct qcom_icc_node slv_venus_cfg = {
1005
+
.name = "slv_venus_cfg",
1006
+
.id = QNOC_SLAVE_VENUS_CFG,
1007
+
.buswidth = 4,
1008
+
.mas_rpm_id = -1,
1009
+
.slv_rpm_id = 10,
1010
+
.qos.ap_owned = true,
1011
+
.qos.qos_mode = NOC_QOS_MODE_INVALID,
1012
+
};
1013
+
1014
+
static struct qcom_icc_node slv_tlmm = {
1015
+
.name = "slv_tlmm",
1016
+
.id = QNOC_SLAVE_TLMM,
1017
+
.buswidth = 4,
1018
+
.mas_rpm_id = -1,
1019
+
.slv_rpm_id = 51,
1020
+
};
1021
+
1022
+
static struct qcom_icc_node slv_gpu_cfg = {
1023
+
.name = "slv_gpu_cfg",
1024
+
.id = QNOC_SLAVE_GRAPHICS_3D_CFG,
1025
+
.buswidth = 4,
1026
+
.mas_rpm_id = -1,
1027
+
.slv_rpm_id = 11,
1028
+
.qos.ap_owned = true,
1029
+
.qos.qos_mode = NOC_QOS_MODE_INVALID,
1030
+
};
1031
+
1032
+
static struct qcom_icc_node slv_imem_cfg = {
1033
+
.name = "slv_imem_cfg",
1034
+
.id = QNOC_SLAVE_IMEM_CFG,
1035
+
.buswidth = 4,
1036
+
.mas_rpm_id = -1,
1037
+
.slv_rpm_id = 54,
1038
+
};
1039
+
1040
+
static struct qcom_icc_node slv_bimc_cfg = {
1041
+
.name = "slv_bimc_cfg",
1042
+
.id = QNOC_SLAVE_BIMC_CFG,
1043
+
.buswidth = 4,
1044
+
.mas_rpm_id = -1,
1045
+
.slv_rpm_id = 56,
1046
+
};
1047
+
1048
+
static struct qcom_icc_node slv_pmic_arb = {
1049
+
.name = "slv_pmic_arb",
1050
+
.id = QNOC_SLAVE_PMIC_ARB,
1051
+
.buswidth = 4,
1052
+
.mas_rpm_id = -1,
1053
+
.slv_rpm_id = 59,
1054
+
};
1055
+
1056
+
static struct qcom_icc_node slv_tcu = {
1057
+
.name = "slv_tcu",
1058
+
.id = QNOC_SLAVE_TCU,
1059
+
.buswidth = 8,
1060
+
.mas_rpm_id = -1,
1061
+
.slv_rpm_id = 133,
1062
+
.qos.ap_owned = true,
1063
+
.qos.qos_mode = NOC_QOS_MODE_INVALID,
1064
+
};
1065
+
1066
+
static const u16 slv_pcnoc_snoc_links[] = {
1067
+
QNOC_PNOC_SNOC_MAS
1068
+
};
1069
+
1070
+
static struct qcom_icc_node slv_pcnoc_snoc = {
1071
+
.name = "slv_pcnoc_snoc",
1072
+
.id = QNOC_PNOC_SNOC_SLV,
1073
+
.buswidth = 8,
1074
+
.mas_rpm_id = -1,
1075
+
.slv_rpm_id = 45,
1076
+
.num_links = ARRAY_SIZE(slv_pcnoc_snoc_links),
1077
+
.links = slv_pcnoc_snoc_links,
1078
+
};
1079
+
1080
+
static struct qcom_icc_node slv_kpss_ahb = {
1081
+
.name = "slv_kpss_ahb",
1082
+
.id = QNOC_SLAVE_APPSS,
1083
+
.buswidth = 4,
1084
+
.mas_rpm_id = -1,
1085
+
.slv_rpm_id = 20,
1086
+
.qos.ap_owned = true,
1087
+
.qos.qos_mode = NOC_QOS_MODE_INVALID,
1088
+
};
1089
+
1090
+
static const u16 slv_snoc_bimc_0_links[] = {
1091
+
QNOC_SNOC_BIMC_0_MAS
1092
+
};
1093
+
1094
+
static struct qcom_icc_node slv_snoc_bimc_0 = {
1095
+
.name = "slv_snoc_bimc_0",
1096
+
.id = QNOC_SNOC_BIMC_0_SLV,
1097
+
.buswidth = 8,
1098
+
.mas_rpm_id = -1,
1099
+
.slv_rpm_id = 24,
1100
+
.num_links = ARRAY_SIZE(slv_snoc_bimc_0_links),
1101
+
.links = slv_snoc_bimc_0_links,
1102
+
};
1103
+
1104
+
static const u16 slv_snoc_bimc_1_links[] = {
1105
+
QNOC_SNOC_BIMC_1_MAS
1106
+
};
1107
+
1108
+
static struct qcom_icc_node slv_snoc_bimc_1 = {
1109
+
.name = "slv_snoc_bimc_1",
1110
+
.id = QNOC_SNOC_BIMC_1_SLV,
1111
+
.buswidth = 16,
1112
+
.mas_rpm_id = -1,
1113
+
.slv_rpm_id = 104,
1114
+
.qos.ap_owned = true,
1115
+
.qos.qos_mode = NOC_QOS_MODE_INVALID,
1116
+
.num_links = ARRAY_SIZE(slv_snoc_bimc_1_links),
1117
+
.links = slv_snoc_bimc_1_links,
1118
+
};
1119
+
1120
+
static struct qcom_icc_node slv_imem = {
1121
+
.name = "slv_imem",
1122
+
.id = QNOC_SLAVE_SYSTEM_IMEM,
1123
+
.buswidth = 8,
1124
+
.mas_rpm_id = -1,
1125
+
.slv_rpm_id = 26,
1126
+
};
1127
+
1128
+
static const u16 slv_snoc_pcnoc_links[] = {
1129
+
QNOC_SNOC_PNOC_MAS
1130
+
};
1131
+
1132
+
static struct qcom_icc_node slv_snoc_pcnoc = {
1133
+
.name = "slv_snoc_pcnoc",
1134
+
.id = QNOC_SNOC_PNOC_SLV,
1135
+
.buswidth = 8,
1136
+
.mas_rpm_id = -1,
1137
+
.slv_rpm_id = 28,
1138
+
.num_links = ARRAY_SIZE(slv_snoc_pcnoc_links),
1139
+
.links = slv_snoc_pcnoc_links,
1140
+
};
1141
+
1142
+
static struct qcom_icc_node slv_qdss_stm = {
1143
+
.name = "slv_qdss_stm",
1144
+
.id = QNOC_SLAVE_QDSS_STM,
1145
+
.buswidth = 4,
1146
+
.mas_rpm_id = -1,
1147
+
.slv_rpm_id = 30,
1148
+
};
1149
+
1150
+
static struct qcom_icc_node slv_cats_0 = {
1151
+
.name = "slv_cats_0",
1152
+
.id = QNOC_SLAVE_CATS_128,
1153
+
.buswidth = 16,
1154
+
.mas_rpm_id = -1,
1155
+
.slv_rpm_id = 106,
1156
+
.qos.ap_owned = true,
1157
+
.qos.qos_mode = NOC_QOS_MODE_INVALID,
1158
+
};
1159
+
1160
+
static struct qcom_icc_node slv_cats_1 = {
1161
+
.name = "slv_cats_1",
1162
+
.id = QNOC_SLAVE_OCMEM_64,
1163
+
.buswidth = 8,
1164
+
.mas_rpm_id = -1,
1165
+
.slv_rpm_id = 107,
1166
+
.qos.ap_owned = true,
1167
+
.qos.qos_mode = NOC_QOS_MODE_INVALID,
1168
+
};
1169
+
1170
+
static struct qcom_icc_node * const msm8909_bimc_nodes[] = {
1171
+
[MAS_APPS_PROC] = &mas_apps_proc,
1172
+
[MAS_OXILI] = &mas_oxili,
1173
+
[MAS_SNOC_BIMC_0] = &mas_snoc_bimc_0,
1174
+
[MAS_SNOC_BIMC_1] = &mas_snoc_bimc_1,
1175
+
[MAS_TCU_0] = &mas_tcu_0,
1176
+
[MAS_TCU_1] = &mas_tcu_1,
1177
+
[SLV_EBI] = &slv_ebi,
1178
+
[SLV_BIMC_SNOC] = &slv_bimc_snoc,
1179
+
};
1180
+
1181
+
static const struct regmap_config msm8909_bimc_regmap_config = {
1182
+
.reg_bits = 32,
1183
+
.reg_stride = 4,
1184
+
.val_bits = 32,
1185
+
.max_register = 0x62000,
1186
+
.fast_io = true,
1187
+
};
1188
+
1189
+
static const struct qcom_icc_desc msm8909_bimc = {
1190
+
.type = QCOM_ICC_BIMC,
1191
+
.nodes = msm8909_bimc_nodes,
1192
+
.num_nodes = ARRAY_SIZE(msm8909_bimc_nodes),
1193
+
.bus_clk_desc = &bimc_clk,
1194
+
.regmap_cfg = &msm8909_bimc_regmap_config,
1195
+
.qos_offset = 0x8000,
1196
+
.ab_coeff = 154,
1197
+
};
1198
+
1199
+
static struct qcom_icc_node * const msm8909_pcnoc_nodes[] = {
1200
+
[MAS_AUDIO] = &mas_audio,
1201
+
[MAS_SPDM] = &mas_spdm,
1202
+
[MAS_DEHR] = &mas_dehr,
1203
+
[MAS_QPIC] = &mas_qpic,
1204
+
[MAS_BLSP_1] = &mas_blsp_1,
1205
+
[MAS_USB_HS] = &mas_usb_hs,
1206
+
[MAS_CRYPTO] = &mas_crypto,
1207
+
[MAS_SDCC_1] = &mas_sdcc_1,
1208
+
[MAS_SDCC_2] = &mas_sdcc_2,
1209
+
[MAS_SNOC_PCNOC] = &mas_snoc_pcnoc,
1210
+
[PCNOC_M_0] = &pcnoc_m_0,
1211
+
[PCNOC_M_1] = &pcnoc_m_1,
1212
+
[PCNOC_INT_0] = &pcnoc_int_0,
1213
+
[PCNOC_INT_1] = &pcnoc_int_1,
1214
+
[PCNOC_S_0] = &pcnoc_s_0,
1215
+
[PCNOC_S_1] = &pcnoc_s_1,
1216
+
[PCNOC_S_2] = &pcnoc_s_2,
1217
+
[PCNOC_S_3] = &pcnoc_s_3,
1218
+
[PCNOC_S_4] = &pcnoc_s_4,
1219
+
[PCNOC_S_5] = &pcnoc_s_5,
1220
+
[PCNOC_S_7] = &pcnoc_s_7,
1221
+
[SLV_TCSR] = &slv_tcsr,
1222
+
[SLV_SDCC_1] = &slv_sdcc_1,
1223
+
[SLV_BLSP_1] = &slv_blsp_1,
1224
+
[SLV_CRYPTO_0_CFG] = &slv_crypto_0_cfg,
1225
+
[SLV_MESSAGE_RAM] = &slv_message_ram,
1226
+
[SLV_PDM] = &slv_pdm,
1227
+
[SLV_PRNG] = &slv_prng,
1228
+
[SLV_USB_HS] = &slv_usb_hs,
1229
+
[SLV_QPIC] = &slv_qpic,
1230
+
[SLV_SPDM] = &slv_spdm,
1231
+
[SLV_SDCC_2] = &slv_sdcc_2,
1232
+
[SLV_AUDIO] = &slv_audio,
1233
+
[SLV_DEHR_CFG] = &slv_dehr_cfg,
1234
+
[SLV_SNOC_CFG] = &slv_snoc_cfg,
1235
+
[SLV_QDSS_CFG] = &slv_qdss_cfg,
1236
+
[SLV_USB_PHY] = &slv_usb_phy,
1237
+
[SLV_CAMERA_SS_CFG] = &slv_camera_ss_cfg,
1238
+
[SLV_DISP_SS_CFG] = &slv_disp_ss_cfg,
1239
+
[SLV_VENUS_CFG] = &slv_venus_cfg,
1240
+
[SLV_TLMM] = &slv_tlmm,
1241
+
[SLV_GPU_CFG] = &slv_gpu_cfg,
1242
+
[SLV_IMEM_CFG] = &slv_imem_cfg,
1243
+
[SLV_BIMC_CFG] = &slv_bimc_cfg,
1244
+
[SLV_PMIC_ARB] = &slv_pmic_arb,
1245
+
[SLV_TCU] = &slv_tcu,
1246
+
[SLV_PCNOC_SNOC] = &slv_pcnoc_snoc,
1247
+
};
1248
+
1249
+
static const struct regmap_config msm8909_pcnoc_regmap_config = {
1250
+
.reg_bits = 32,
1251
+
.reg_stride = 4,
1252
+
.val_bits = 32,
1253
+
.max_register = 0x11000,
1254
+
.fast_io = true,
1255
+
};
1256
+
1257
+
static const struct qcom_icc_desc msm8909_pcnoc = {
1258
+
.type = QCOM_ICC_NOC,
1259
+
.nodes = msm8909_pcnoc_nodes,
1260
+
.num_nodes = ARRAY_SIZE(msm8909_pcnoc_nodes),
1261
+
.bus_clk_desc = &bus_0_clk,
1262
+
.regmap_cfg = &msm8909_pcnoc_regmap_config,
1263
+
.qos_offset = 0x7000,
1264
+
};
1265
+
1266
+
static struct qcom_icc_node * const msm8909_snoc_nodes[] = {
1267
+
[MAS_QDSS_BAM] = &mas_qdss_bam,
1268
+
[MAS_BIMC_SNOC] = &mas_bimc_snoc,
1269
+
[MAS_MDP] = &mas_mdp,
1270
+
[MAS_PCNOC_SNOC] = &mas_pcnoc_snoc,
1271
+
[MAS_VENUS] = &mas_venus,
1272
+
[MAS_VFE] = &mas_vfe,
1273
+
[MAS_QDSS_ETR] = &mas_qdss_etr,
1274
+
[MM_INT_0] = &mm_int_0,
1275
+
[MM_INT_1] = &mm_int_1,
1276
+
[MM_INT_2] = &mm_int_2,
1277
+
[MM_INT_BIMC] = &mm_int_bimc,
1278
+
[QDSS_INT] = &qdss_int,
1279
+
[SNOC_INT_0] = &snoc_int_0,
1280
+
[SNOC_INT_1] = &snoc_int_1,
1281
+
[SNOC_INT_BIMC] = &snoc_int_bimc,
1282
+
[SLV_KPSS_AHB] = &slv_kpss_ahb,
1283
+
[SLV_SNOC_BIMC_0] = &slv_snoc_bimc_0,
1284
+
[SLV_SNOC_BIMC_1] = &slv_snoc_bimc_1,
1285
+
[SLV_IMEM] = &slv_imem,
1286
+
[SLV_SNOC_PCNOC] = &slv_snoc_pcnoc,
1287
+
[SLV_QDSS_STM] = &slv_qdss_stm,
1288
+
[SLV_CATS_0] = &slv_cats_0,
1289
+
[SLV_CATS_1] = &slv_cats_1,
1290
+
};
1291
+
1292
+
static const struct regmap_config msm8909_snoc_regmap_config = {
1293
+
.reg_bits = 32,
1294
+
.reg_stride = 4,
1295
+
.val_bits = 32,
1296
+
.max_register = 0x13000,
1297
+
.fast_io = true,
1298
+
};
1299
+
1300
+
static const struct qcom_icc_desc msm8909_snoc = {
1301
+
.type = QCOM_ICC_NOC,
1302
+
.nodes = msm8909_snoc_nodes,
1303
+
.num_nodes = ARRAY_SIZE(msm8909_snoc_nodes),
1304
+
.bus_clk_desc = &bus_1_clk,
1305
+
.regmap_cfg = &msm8909_snoc_regmap_config,
1306
+
.qos_offset = 0x7000,
1307
+
};
1308
+
1309
+
static const struct of_device_id msm8909_noc_of_match[] = {
1310
+
{ .compatible = "qcom,msm8909-bimc", .data = &msm8909_bimc },
1311
+
{ .compatible = "qcom,msm8909-pcnoc", .data = &msm8909_pcnoc },
1312
+
{ .compatible = "qcom,msm8909-snoc", .data = &msm8909_snoc },
1313
+
{ }
1314
+
};
1315
+
MODULE_DEVICE_TABLE(of, msm8909_noc_of_match);
1316
+
1317
+
static struct platform_driver msm8909_noc_driver = {
1318
+
.probe = qnoc_probe,
1319
+
.remove_new = qnoc_remove,
1320
+
.driver = {
1321
+
.name = "qnoc-msm8909",
1322
+
.of_match_table = msm8909_noc_of_match,
1323
+
.sync_state = icc_sync_state,
1324
+
},
1325
+
};
1326
+
module_platform_driver(msm8909_noc_driver);
1327
+
1328
+
MODULE_DESCRIPTION("Qualcomm MSM8909 NoC driver");
1329
+
MODULE_LICENSE("GPL");
+28
-28
drivers/interconnect/qcom/sa8775p.c
+28
-28
drivers/interconnect/qcom/sa8775p.c
···
2092
2092
.nodes = { &xs_qdss_stm },
2093
2093
};
2094
2094
2095
-
static struct qcom_icc_bcm *aggre1_noc_bcms[] = {
2095
+
static struct qcom_icc_bcm * const aggre1_noc_bcms[] = {
2096
2096
&bcm_sn3,
2097
2097
};
2098
2098
2099
-
static struct qcom_icc_node *aggre1_noc_nodes[] = {
2099
+
static struct qcom_icc_node * const aggre1_noc_nodes[] = {
2100
2100
[MASTER_QUP_3] = &qxm_qup3,
2101
2101
[MASTER_EMAC] = &xm_emac_0,
2102
2102
[MASTER_EMAC_1] = &xm_emac_1,
···
2115
2115
.num_bcms = ARRAY_SIZE(aggre1_noc_bcms),
2116
2116
};
2117
2117
2118
-
static struct qcom_icc_bcm *aggre2_noc_bcms[] = {
2118
+
static struct qcom_icc_bcm * const aggre2_noc_bcms[] = {
2119
2119
&bcm_ce0,
2120
2120
&bcm_sn4,
2121
2121
};
2122
2122
2123
-
static struct qcom_icc_node *aggre2_noc_nodes[] = {
2123
+
static struct qcom_icc_node * const aggre2_noc_nodes[] = {
2124
2124
[MASTER_QDSS_BAM] = &qhm_qdss_bam,
2125
2125
[MASTER_QUP_0] = &qhm_qup0,
2126
2126
[MASTER_QUP_1] = &qhm_qup1,
···
2142
2142
.num_bcms = ARRAY_SIZE(aggre2_noc_bcms),
2143
2143
};
2144
2144
2145
-
static struct qcom_icc_bcm *clk_virt_bcms[] = {
2145
+
static struct qcom_icc_bcm * const clk_virt_bcms[] = {
2146
2146
&bcm_qup0,
2147
2147
&bcm_qup1,
2148
2148
&bcm_qup2,
2149
2149
};
2150
2150
2151
-
static struct qcom_icc_node *clk_virt_nodes[] = {
2151
+
static struct qcom_icc_node * const clk_virt_nodes[] = {
2152
2152
[MASTER_QUP_CORE_0] = &qup0_core_master,
2153
2153
[MASTER_QUP_CORE_1] = &qup1_core_master,
2154
2154
[MASTER_QUP_CORE_2] = &qup2_core_master,
···
2166
2166
.num_bcms = ARRAY_SIZE(clk_virt_bcms),
2167
2167
};
2168
2168
2169
-
static struct qcom_icc_bcm *config_noc_bcms[] = {
2169
+
static struct qcom_icc_bcm * const config_noc_bcms[] = {
2170
2170
&bcm_cn0,
2171
2171
&bcm_cn1,
2172
2172
&bcm_cn2,
···
2175
2175
&bcm_sn10,
2176
2176
};
2177
2177
2178
-
static struct qcom_icc_node *config_noc_nodes[] = {
2178
+
static struct qcom_icc_node * const config_noc_nodes[] = {
2179
2179
[MASTER_GEM_NOC_CNOC] = &qnm_gemnoc_cnoc,
2180
2180
[MASTER_GEM_NOC_PCIE_SNOC] = &qnm_gemnoc_pcie,
2181
2181
[SLAVE_AHB2PHY_0] = &qhs_ahb2phy0,
···
2271
2271
.num_bcms = ARRAY_SIZE(config_noc_bcms),
2272
2272
};
2273
2273
2274
-
static struct qcom_icc_bcm *dc_noc_bcms[] = {
2274
+
static struct qcom_icc_bcm * const dc_noc_bcms[] = {
2275
2275
};
2276
2276
2277
-
static struct qcom_icc_node *dc_noc_nodes[] = {
2277
+
static struct qcom_icc_node * const dc_noc_nodes[] = {
2278
2278
[MASTER_CNOC_DC_NOC] = &qnm_cnoc_dc_noc,
2279
2279
[SLAVE_LLCC_CFG] = &qhs_llcc,
2280
2280
[SLAVE_GEM_NOC_CFG] = &qns_gemnoc,
···
2287
2287
.num_bcms = ARRAY_SIZE(dc_noc_bcms),
2288
2288
};
2289
2289
2290
-
static struct qcom_icc_bcm *gem_noc_bcms[] = {
2290
+
static struct qcom_icc_bcm * const gem_noc_bcms[] = {
2291
2291
&bcm_sh0,
2292
2292
&bcm_sh2,
2293
2293
};
2294
2294
2295
-
static struct qcom_icc_node *gem_noc_nodes[] = {
2295
+
static struct qcom_icc_node * const gem_noc_nodes[] = {
2296
2296
[MASTER_GPU_TCU] = &alm_gpu_tcu,
2297
2297
[MASTER_PCIE_TCU] = &alm_pcie_tcu,
2298
2298
[MASTER_SYS_TCU] = &alm_sys_tcu,
···
2323
2323
.num_bcms = ARRAY_SIZE(gem_noc_bcms),
2324
2324
};
2325
2325
2326
-
static struct qcom_icc_bcm *gpdsp_anoc_bcms[] = {
2326
+
static struct qcom_icc_bcm * const gpdsp_anoc_bcms[] = {
2327
2327
&bcm_gna0,
2328
2328
&bcm_gnb0,
2329
2329
};
2330
2330
2331
-
static struct qcom_icc_node *gpdsp_anoc_nodes[] = {
2331
+
static struct qcom_icc_node * const gpdsp_anoc_nodes[] = {
2332
2332
[MASTER_DSP0] = &qxm_dsp0,
2333
2333
[MASTER_DSP1] = &qxm_dsp1,
2334
2334
[SLAVE_GP_DSP_SAIL_NOC] = &qns_gp_dsp_sail_noc,
···
2341
2341
.num_bcms = ARRAY_SIZE(gpdsp_anoc_bcms),
2342
2342
};
2343
2343
2344
-
static struct qcom_icc_bcm *lpass_ag_noc_bcms[] = {
2344
+
static struct qcom_icc_bcm * const lpass_ag_noc_bcms[] = {
2345
2345
&bcm_sn9,
2346
2346
};
2347
2347
2348
-
static struct qcom_icc_node *lpass_ag_noc_nodes[] = {
2348
+
static struct qcom_icc_node * const lpass_ag_noc_nodes[] = {
2349
2349
[MASTER_CNOC_LPASS_AG_NOC] = &qhm_config_noc,
2350
2350
[MASTER_LPASS_PROC] = &qxm_lpass_dsp,
2351
2351
[SLAVE_LPASS_CORE_CFG] = &qhs_lpass_core,
···
2364
2364
.num_bcms = ARRAY_SIZE(lpass_ag_noc_bcms),
2365
2365
};
2366
2366
2367
-
static struct qcom_icc_bcm *mc_virt_bcms[] = {
2367
+
static struct qcom_icc_bcm * const mc_virt_bcms[] = {
2368
2368
&bcm_acv,
2369
2369
&bcm_mc0,
2370
2370
};
2371
2371
2372
-
static struct qcom_icc_node *mc_virt_nodes[] = {
2372
+
static struct qcom_icc_node * const mc_virt_nodes[] = {
2373
2373
[MASTER_LLCC] = &llcc_mc,
2374
2374
[SLAVE_EBI1] = &ebi,
2375
2375
};
···
2381
2381
.num_bcms = ARRAY_SIZE(mc_virt_bcms),
2382
2382
};
2383
2383
2384
-
static struct qcom_icc_bcm *mmss_noc_bcms[] = {
2384
+
static struct qcom_icc_bcm * const mmss_noc_bcms[] = {
2385
2385
&bcm_mm0,
2386
2386
&bcm_mm1,
2387
2387
};
2388
2388
2389
-
static struct qcom_icc_node *mmss_noc_nodes[] = {
2389
+
static struct qcom_icc_node * const mmss_noc_nodes[] = {
2390
2390
[MASTER_CAMNOC_HF] = &qnm_camnoc_hf,
2391
2391
[MASTER_CAMNOC_ICP] = &qnm_camnoc_icp,
2392
2392
[MASTER_CAMNOC_SF] = &qnm_camnoc_sf,
···
2413
2413
.num_bcms = ARRAY_SIZE(mmss_noc_bcms),
2414
2414
};
2415
2415
2416
-
static struct qcom_icc_bcm *nspa_noc_bcms[] = {
2416
+
static struct qcom_icc_bcm * const nspa_noc_bcms[] = {
2417
2417
&bcm_nsa0,
2418
2418
&bcm_nsa1,
2419
2419
};
2420
2420
2421
-
static struct qcom_icc_node *nspa_noc_nodes[] = {
2421
+
static struct qcom_icc_node * const nspa_noc_nodes[] = {
2422
2422
[MASTER_CDSP_NOC_CFG] = &qhm_nsp_noc_config,
2423
2423
[MASTER_CDSP_PROC] = &qxm_nsp,
2424
2424
[SLAVE_HCP_A] = &qns_hcp,
···
2433
2433
.num_bcms = ARRAY_SIZE(nspa_noc_bcms),
2434
2434
};
2435
2435
2436
-
static struct qcom_icc_bcm *nspb_noc_bcms[] = {
2436
+
static struct qcom_icc_bcm * const nspb_noc_bcms[] = {
2437
2437
&bcm_nsb0,
2438
2438
&bcm_nsb1,
2439
2439
};
2440
2440
2441
-
static struct qcom_icc_node *nspb_noc_nodes[] = {
2441
+
static struct qcom_icc_node * const nspb_noc_nodes[] = {
2442
2442
[MASTER_CDSPB_NOC_CFG] = &qhm_nspb_noc_config,
2443
2443
[MASTER_CDSP_PROC_B] = &qxm_nspb,
2444
2444
[SLAVE_CDSPB_MEM_NOC] = &qns_nspb_gemnoc,
···
2453
2453
.num_bcms = ARRAY_SIZE(nspb_noc_bcms),
2454
2454
};
2455
2455
2456
-
static struct qcom_icc_bcm *pcie_anoc_bcms[] = {
2456
+
static struct qcom_icc_bcm * const pcie_anoc_bcms[] = {
2457
2457
&bcm_pci0,
2458
2458
};
2459
2459
2460
-
static struct qcom_icc_node *pcie_anoc_nodes[] = {
2460
+
static struct qcom_icc_node * const pcie_anoc_nodes[] = {
2461
2461
[MASTER_PCIE_0] = &xm_pcie3_0,
2462
2462
[MASTER_PCIE_1] = &xm_pcie3_1,
2463
2463
[SLAVE_ANOC_PCIE_GEM_NOC] = &qns_pcie_mem_noc,
···
2470
2470
.num_bcms = ARRAY_SIZE(pcie_anoc_bcms),
2471
2471
};
2472
2472
2473
-
static struct qcom_icc_bcm *system_noc_bcms[] = {
2473
+
static struct qcom_icc_bcm * const system_noc_bcms[] = {
2474
2474
&bcm_sn0,
2475
2475
&bcm_sn1,
2476
2476
&bcm_sn3,
···
2478
2478
&bcm_sn9,
2479
2479
};
2480
2480
2481
-
static struct qcom_icc_node *system_noc_nodes[] = {
2481
+
static struct qcom_icc_node * const system_noc_nodes[] = {
2482
2482
[MASTER_GIC_AHB] = &qhm_gic,
2483
2483
[MASTER_A1NOC_SNOC] = &qnm_aggre1_noc,
2484
2484
[MASTER_A2NOC_SNOC] = &qnm_aggre2_noc,
+6
-6
drivers/interconnect/qcom/sm6115.c
+6
-6
drivers/interconnect/qcom/sm6115.c
···
1193
1193
.links = slv_anoc_snoc_links,
1194
1194
};
1195
1195
1196
-
static struct qcom_icc_node *bimc_nodes[] = {
1196
+
static struct qcom_icc_node * const bimc_nodes[] = {
1197
1197
[MASTER_AMPSS_M0] = &apps_proc,
1198
1198
[MASTER_SNOC_BIMC_RT] = &mas_snoc_bimc_rt,
1199
1199
[MASTER_SNOC_BIMC_NRT] = &mas_snoc_bimc_nrt,
···
1223
1223
.ab_coeff = 153,
1224
1224
};
1225
1225
1226
-
static struct qcom_icc_node *config_noc_nodes[] = {
1226
+
static struct qcom_icc_node * const config_noc_nodes[] = {
1227
1227
[SNOC_CNOC_MAS] = &mas_snoc_cnoc,
1228
1228
[MASTER_QDSS_DAP] = &xm_dap,
1229
1229
[SLAVE_AHB2PHY_USB] = &qhs_ahb2phy_usb,
···
1294
1294
.keep_alive = true,
1295
1295
};
1296
1296
1297
-
static struct qcom_icc_node *sys_noc_nodes[] = {
1297
+
static struct qcom_icc_node * const sys_noc_nodes[] = {
1298
1298
[MASTER_CRYPTO_CORE0] = &crypto_c0,
1299
1299
[MASTER_SNOC_CFG] = &qhm_snoc_cfg,
1300
1300
[MASTER_TIC] = &qhm_tic,
···
1339
1339
.keep_alive = true,
1340
1340
};
1341
1341
1342
-
static struct qcom_icc_node *clk_virt_nodes[] = {
1342
+
static struct qcom_icc_node * const clk_virt_nodes[] = {
1343
1343
[MASTER_QUP_CORE_0] = &qup0_core_master,
1344
1344
[SLAVE_QUP_CORE_0] = &qup0_core_slave,
1345
1345
};
···
1353
1353
.keep_alive = true,
1354
1354
};
1355
1355
1356
-
static struct qcom_icc_node *mmnrt_virt_nodes[] = {
1356
+
static struct qcom_icc_node * const mmnrt_virt_nodes[] = {
1357
1357
[MASTER_CAMNOC_SF] = &qnm_camera_nrt,
1358
1358
[MASTER_VIDEO_P0] = &qxm_venus0,
1359
1359
[MASTER_VIDEO_PROC] = &qxm_venus_cpu,
···
1370
1370
.ab_coeff = 142,
1371
1371
};
1372
1372
1373
-
static struct qcom_icc_node *mmrt_virt_nodes[] = {
1373
+
static struct qcom_icc_node * const mmrt_virt_nodes[] = {
1374
1374
[MASTER_CAMNOC_HF] = &qnm_camera_rt,
1375
1375
[MASTER_MDP_PORT0] = &qxm_mdp0,
1376
1376
[SLAVE_SNOC_BIMC_RT] = &slv_snoc_bimc_rt,
+1754
drivers/interconnect/qcom/sm7150.c
+1754
drivers/interconnect/qcom/sm7150.c
···
1
+
// SPDX-License-Identifier: GPL-2.0-only
2
+
/*
3
+
* Copyright (c) 2020, The Linux Foundation. All rights reserved.
4
+
* Copyright (c) 2024, Danila Tikhonov <danila@jiaxyga.com>
5
+
*/
6
+
7
+
#include <linux/device.h>
8
+
#include <linux/interconnect.h>
9
+
#include <linux/interconnect-provider.h>
10
+
#include <linux/mod_devicetable.h>
11
+
#include <linux/module.h>
12
+
#include <linux/platform_device.h>
13
+
#include <dt-bindings/interconnect/qcom,sm7150-rpmh.h>
14
+
15
+
#include "bcm-voter.h"
16
+
#include "icc-rpmh.h"
17
+
#include "sm7150.h"
18
+
19
+
static struct qcom_icc_node qhm_a1noc_cfg = {
20
+
.name = "qhm-a1noc-cfg",
21
+
.id = SM7150_MASTER_A1NOC_CFG,
22
+
.channels = 1,
23
+
.buswidth = 4,
24
+
.num_links = 1,
25
+
.links = { SM7150_SLAVE_SERVICE_A1NOC },
26
+
};
27
+
28
+
static struct qcom_icc_node qhm_qup_center = {
29
+
.name = "qhm_qup_center",
30
+
.id = SM7150_MASTER_QUP_0,
31
+
.channels = 1,
32
+
.buswidth = 4,
33
+
.num_links = 1,
34
+
.links = { SM7150_A1NOC_SNOC_SLV },
35
+
};
36
+
37
+
static struct qcom_icc_node qhm_tsif = {
38
+
.name = "qhm_tsif",
39
+
.id = SM7150_MASTER_TSIF,
40
+
.channels = 1,
41
+
.buswidth = 4,
42
+
.num_links = 1,
43
+
.links = { SM7150_A1NOC_SNOC_SLV },
44
+
};
45
+
46
+
static struct qcom_icc_node xm_emmc = {
47
+
.name = "xm_emmc",
48
+
.id = SM7150_MASTER_EMMC,
49
+
.channels = 1,
50
+
.buswidth = 8,
51
+
.num_links = 1,
52
+
.links = { SM7150_A1NOC_SNOC_SLV },
53
+
};
54
+
55
+
static struct qcom_icc_node xm_sdc2 = {
56
+
.name = "xm_sdc2",
57
+
.id = SM7150_MASTER_SDCC_2,
58
+
.channels = 1,
59
+
.buswidth = 8,
60
+
.num_links = 1,
61
+
.links = { SM7150_A1NOC_SNOC_SLV },
62
+
};
63
+
64
+
static struct qcom_icc_node xm_sdc4 = {
65
+
.name = "xm_sdc4",
66
+
.id = SM7150_MASTER_SDCC_4,
67
+
.channels = 1,
68
+
.buswidth = 8,
69
+
.num_links = 1,
70
+
.links = { SM7150_A1NOC_SNOC_SLV },
71
+
};
72
+
73
+
static struct qcom_icc_node xm_ufs_mem = {
74
+
.name = "xm_ufs_mem",
75
+
.id = SM7150_MASTER_UFS_MEM,
76
+
.channels = 1,
77
+
.buswidth = 8,
78
+
.num_links = 1,
79
+
.links = { SM7150_A1NOC_SNOC_SLV },
80
+
};
81
+
82
+
static struct qcom_icc_node qhm_a2noc_cfg = {
83
+
.name = "qhm_a2noc_cfg",
84
+
.id = SM7150_MASTER_A2NOC_CFG,
85
+
.channels = 1,
86
+
.buswidth = 4,
87
+
.num_links = 1,
88
+
.links = { SM7150_SLAVE_SERVICE_A2NOC },
89
+
};
90
+
91
+
static struct qcom_icc_node qhm_qdss_bam = {
92
+
.name = "qhm_qdss_bam",
93
+
.id = SM7150_MASTER_QDSS_BAM,
94
+
.channels = 1,
95
+
.buswidth = 4,
96
+
.num_links = 1,
97
+
.links = { SM7150_A2NOC_SNOC_SLV },
98
+
};
99
+
100
+
static struct qcom_icc_node qhm_qup_north = {
101
+
.name = "qhm_qup_north",
102
+
.id = SM7150_MASTER_QUP_1,
103
+
.channels = 1,
104
+
.buswidth = 4,
105
+
.num_links = 1,
106
+
.links = { SM7150_A2NOC_SNOC_SLV },
107
+
};
108
+
109
+
static struct qcom_icc_node qnm_cnoc = {
110
+
.name = "qnm_cnoc",
111
+
.id = SM7150_MASTER_CNOC_A2NOC,
112
+
.channels = 1,
113
+
.buswidth = 8,
114
+
.num_links = 1,
115
+
.links = { SM7150_A2NOC_SNOC_SLV },
116
+
};
117
+
118
+
static struct qcom_icc_node qxm_crypto = {
119
+
.name = "qxm_crypto",
120
+
.id = SM7150_MASTER_CRYPTO_CORE_0,
121
+
.channels = 1,
122
+
.buswidth = 8,
123
+
.num_links = 1,
124
+
.links = { SM7150_A2NOC_SNOC_SLV },
125
+
};
126
+
127
+
static struct qcom_icc_node qxm_ipa = {
128
+
.name = "qxm_ipa",
129
+
.id = SM7150_MASTER_IPA,
130
+
.channels = 1,
131
+
.buswidth = 8,
132
+
.num_links = 1,
133
+
.links = { SM7150_A2NOC_SNOC_SLV },
134
+
};
135
+
136
+
static struct qcom_icc_node xm_pcie3_0 = {
137
+
.name = "xm_pcie3_0",
138
+
.id = SM7150_MASTER_PCIE,
139
+
.channels = 1,
140
+
.buswidth = 8,
141
+
.num_links = 1,
142
+
.links = { SM7150_SLAVE_ANOC_PCIE_GEM_NOC },
143
+
};
144
+
145
+
static struct qcom_icc_node xm_qdss_etr = {
146
+
.name = "xm_qdss_etr",
147
+
.id = SM7150_MASTER_QDSS_ETR,
148
+
.channels = 1,
149
+
.buswidth = 8,
150
+
.num_links = 1,
151
+
.links = { SM7150_A2NOC_SNOC_SLV },
152
+
};
153
+
154
+
static struct qcom_icc_node xm_usb3_0 = {
155
+
.name = "xm_usb3_0",
156
+
.id = SM7150_MASTER_USB3,
157
+
.channels = 1,
158
+
.buswidth = 8,
159
+
.num_links = 1,
160
+
.links = { SM7150_A2NOC_SNOC_SLV },
161
+
};
162
+
163
+
static struct qcom_icc_node qxm_camnoc_hf0_uncomp = {
164
+
.name = "qxm_camnoc_hf0_uncomp",
165
+
.id = SM7150_MASTER_CAMNOC_HF0_UNCOMP,
166
+
.channels = 2,
167
+
.buswidth = 32,
168
+
.num_links = 1,
169
+
.links = { SM7150_SLAVE_CAMNOC_UNCOMP },
170
+
};
171
+
172
+
static struct qcom_icc_node qxm_camnoc_rt_uncomp = {
173
+
.name = "qxm_camnoc_rt_uncomp",
174
+
.id = SM7150_MASTER_CAMNOC_RT_UNCOMP,
175
+
.channels = 1,
176
+
.buswidth = 32,
177
+
.num_links = 1,
178
+
.links = { SM7150_SLAVE_CAMNOC_UNCOMP },
179
+
};
180
+
181
+
static struct qcom_icc_node qxm_camnoc_sf_uncomp = {
182
+
.name = "qxm_camnoc_sf_uncomp",
183
+
.id = SM7150_MASTER_CAMNOC_SF_UNCOMP,
184
+
.channels = 1,
185
+
.buswidth = 32,
186
+
.num_links = 1,
187
+
.links = { SM7150_SLAVE_CAMNOC_UNCOMP },
188
+
};
189
+
190
+
static struct qcom_icc_node qxm_camnoc_nrt_uncomp = {
191
+
.name = "qxm_camnoc_nrt_uncomp",
192
+
.id = SM7150_MASTER_CAMNOC_NRT_UNCOMP,
193
+
.channels = 1,
194
+
.buswidth = 32,
195
+
.num_links = 1,
196
+
.links = { SM7150_SLAVE_CAMNOC_UNCOMP },
197
+
};
198
+
199
+
static struct qcom_icc_node qnm_npu = {
200
+
.name = "qnm_npu",
201
+
.id = SM7150_MASTER_NPU,
202
+
.channels = 1,
203
+
.buswidth = 32,
204
+
.num_links = 1,
205
+
.links = { SM7150_SLAVE_CDSP_GEM_NOC },
206
+
};
207
+
208
+
static struct qcom_icc_node qhm_spdm = {
209
+
.name = "qhm_spdm",
210
+
.id = SM7150_MASTER_SPDM,
211
+
.channels = 1,
212
+
.buswidth = 4,
213
+
.num_links = 1,
214
+
.links = { SM7150_SLAVE_CNOC_A2NOC },
215
+
};
216
+
217
+
static struct qcom_icc_node qnm_snoc = {
218
+
.name = "qnm_snoc",
219
+
.id = SM7150_SNOC_CNOC_MAS,
220
+
.channels = 1,
221
+
.buswidth = 8,
222
+
.num_links = 47,
223
+
.links = { SM7150_SLAVE_TLMM_SOUTH,
224
+
SM7150_SLAVE_CAMERA_CFG,
225
+
SM7150_SLAVE_SDCC_4,
226
+
SM7150_SLAVE_SDCC_2,
227
+
SM7150_SLAVE_CNOC_MNOC_CFG,
228
+
SM7150_SLAVE_UFS_MEM_CFG,
229
+
SM7150_SLAVE_QUP_0,
230
+
SM7150_SLAVE_GLM,
231
+
SM7150_SLAVE_PDM,
232
+
SM7150_SLAVE_CAMERA_NRT_THROTTLE_CFG,
233
+
SM7150_SLAVE_A2NOC_CFG,
234
+
SM7150_SLAVE_QDSS_CFG,
235
+
SM7150_SLAVE_CAMERA_RT_THROTTLE_CFG,
236
+
SM7150_SLAVE_DISPLAY_CFG,
237
+
SM7150_SLAVE_PCIE_CFG,
238
+
SM7150_SLAVE_DISPLAY_THROTTLE_CFG,
239
+
SM7150_SLAVE_TCSR,
240
+
SM7150_SLAVE_VENUS_CVP_THROTTLE_CFG,
241
+
SM7150_SLAVE_CNOC_DDRSS,
242
+
SM7150_SLAVE_AHB2PHY_NORTH,
243
+
SM7150_SLAVE_SNOC_CFG,
244
+
SM7150_SLAVE_GRAPHICS_3D_CFG,
245
+
SM7150_SLAVE_VENUS_CFG,
246
+
SM7150_SLAVE_TSIF,
247
+
SM7150_SLAVE_CDSP_CFG,
248
+
SM7150_SLAVE_CLK_CTL,
249
+
SM7150_SLAVE_AOP,
250
+
SM7150_SLAVE_QUP_1,
251
+
SM7150_SLAVE_AHB2PHY_SOUTH,
252
+
SM7150_SLAVE_SERVICE_CNOC,
253
+
SM7150_SLAVE_AHB2PHY_WEST,
254
+
SM7150_SLAVE_USB3,
255
+
SM7150_SLAVE_VENUS_THROTTLE_CFG,
256
+
SM7150_SLAVE_IPA_CFG,
257
+
SM7150_SLAVE_RBCPR_CX_CFG,
258
+
SM7150_SLAVE_TLMM_WEST,
259
+
SM7150_SLAVE_A1NOC_CFG,
260
+
SM7150_SLAVE_AOSS,
261
+
SM7150_SLAVE_PRNG,
262
+
SM7150_SLAVE_VSENSE_CTRL_CFG,
263
+
SM7150_SLAVE_EMMC_CFG,
264
+
SM7150_SLAVE_SPDM_WRAPPER,
265
+
SM7150_SLAVE_CRYPTO_0_CFG,
266
+
SM7150_SLAVE_PIMEM_CFG,
267
+
SM7150_SLAVE_TLMM_NORTH,
268
+
SM7150_SLAVE_RBCPR_MX_CFG,
269
+
SM7150_SLAVE_IMEM_CFG
270
+
},
271
+
};
272
+
273
+
static struct qcom_icc_node xm_qdss_dap = {
274
+
.name = "xm_qdss_dap",
275
+
.id = SM7150_MASTER_QDSS_DAP,
276
+
.channels = 1,
277
+
.buswidth = 8,
278
+
.num_links = 48,
279
+
.links = { SM7150_SLAVE_TLMM_SOUTH,
280
+
SM7150_SLAVE_CAMERA_CFG,
281
+
SM7150_SLAVE_SDCC_4,
282
+
SM7150_SLAVE_SDCC_2,
283
+
SM7150_SLAVE_CNOC_MNOC_CFG,
284
+
SM7150_SLAVE_UFS_MEM_CFG,
285
+
SM7150_SLAVE_QUP_0,
286
+
SM7150_SLAVE_GLM,
287
+
SM7150_SLAVE_PDM,
288
+
SM7150_SLAVE_CAMERA_NRT_THROTTLE_CFG,
289
+
SM7150_SLAVE_A2NOC_CFG,
290
+
SM7150_SLAVE_QDSS_CFG,
291
+
SM7150_SLAVE_CAMERA_RT_THROTTLE_CFG,
292
+
SM7150_SLAVE_DISPLAY_CFG,
293
+
SM7150_SLAVE_PCIE_CFG,
294
+
SM7150_SLAVE_DISPLAY_THROTTLE_CFG,
295
+
SM7150_SLAVE_TCSR,
296
+
SM7150_SLAVE_VENUS_CVP_THROTTLE_CFG,
297
+
SM7150_SLAVE_CNOC_DDRSS,
298
+
SM7150_SLAVE_CNOC_A2NOC,
299
+
SM7150_SLAVE_AHB2PHY_NORTH,
300
+
SM7150_SLAVE_SNOC_CFG,
301
+
SM7150_SLAVE_GRAPHICS_3D_CFG,
302
+
SM7150_SLAVE_VENUS_CFG,
303
+
SM7150_SLAVE_TSIF,
304
+
SM7150_SLAVE_CDSP_CFG,
305
+
SM7150_SLAVE_CLK_CTL,
306
+
SM7150_SLAVE_AOP,
307
+
SM7150_SLAVE_QUP_1,
308
+
SM7150_SLAVE_AHB2PHY_SOUTH,
309
+
SM7150_SLAVE_SERVICE_CNOC,
310
+
SM7150_SLAVE_AHB2PHY_WEST,
311
+
SM7150_SLAVE_USB3,
312
+
SM7150_SLAVE_VENUS_THROTTLE_CFG,
313
+
SM7150_SLAVE_IPA_CFG,
314
+
SM7150_SLAVE_RBCPR_CX_CFG,
315
+
SM7150_SLAVE_TLMM_WEST,
316
+
SM7150_SLAVE_A1NOC_CFG,
317
+
SM7150_SLAVE_AOSS,
318
+
SM7150_SLAVE_PRNG,
319
+
SM7150_SLAVE_VSENSE_CTRL_CFG,
320
+
SM7150_SLAVE_EMMC_CFG,
321
+
SM7150_SLAVE_SPDM_WRAPPER,
322
+
SM7150_SLAVE_CRYPTO_0_CFG,
323
+
SM7150_SLAVE_PIMEM_CFG,
324
+
SM7150_SLAVE_TLMM_NORTH,
325
+
SM7150_SLAVE_RBCPR_MX_CFG,
326
+
SM7150_SLAVE_IMEM_CFG
327
+
},
328
+
};
329
+
330
+
static struct qcom_icc_node qhm_cnoc_dc_noc = {
331
+
.name = "qhm_cnoc_dc_noc",
332
+
.id = SM7150_MASTER_CNOC_DC_NOC,
333
+
.channels = 1,
334
+
.buswidth = 4,
335
+
.num_links = 2,
336
+
.links = { SM7150_SLAVE_LLCC_CFG,
337
+
SM7150_SLAVE_GEM_NOC_CFG
338
+
},
339
+
};
340
+
341
+
static struct qcom_icc_node acm_apps = {
342
+
.name = "acm_apps",
343
+
.id = SM7150_MASTER_AMPSS_M0,
344
+
.channels = 1,
345
+
.buswidth = 16,
346
+
.num_links = 2,
347
+
.links = { SM7150_SLAVE_LLCC,
348
+
SM7150_SLAVE_GEM_NOC_SNOC
349
+
},
350
+
};
351
+
352
+
static struct qcom_icc_node acm_sys_tcu = {
353
+
.name = "acm_sys_tcu",
354
+
.id = SM7150_MASTER_SYS_TCU,
355
+
.channels = 1,
356
+
.buswidth = 8,
357
+
.num_links = 2,
358
+
.links = { SM7150_SLAVE_LLCC,
359
+
SM7150_SLAVE_GEM_NOC_SNOC
360
+
},
361
+
};
362
+
363
+
static struct qcom_icc_node qhm_gemnoc_cfg = {
364
+
.name = "qhm_gemnoc_cfg",
365
+
.id = SM7150_MASTER_GEM_NOC_CFG,
366
+
.channels = 1,
367
+
.buswidth = 4,
368
+
.num_links = 2,
369
+
.links = { SM7150_SLAVE_SERVICE_GEM_NOC,
370
+
SM7150_SLAVE_MSS_PROC_MS_MPU_CFG
371
+
},
372
+
};
373
+
374
+
static struct qcom_icc_node qnm_cmpnoc = {
375
+
.name = "qnm_cmpnoc",
376
+
.id = SM7150_MASTER_COMPUTE_NOC,
377
+
.channels = 1,
378
+
.buswidth = 32,
379
+
.num_links = 2,
380
+
.links = { SM7150_SLAVE_LLCC,
381
+
SM7150_SLAVE_GEM_NOC_SNOC
382
+
},
383
+
};
384
+
385
+
static struct qcom_icc_node qnm_mnoc_hf = {
386
+
.name = "qnm_mnoc_hf",
387
+
.id = SM7150_MASTER_MNOC_HF_MEM_NOC,
388
+
.channels = 2,
389
+
.buswidth = 32,
390
+
.num_links = 1,
391
+
.links = { SM7150_SLAVE_LLCC },
392
+
};
393
+
394
+
static struct qcom_icc_node qnm_mnoc_sf = {
395
+
.name = "qnm_mnoc_sf",
396
+
.id = SM7150_MASTER_MNOC_SF_MEM_NOC,
397
+
.channels = 1,
398
+
.buswidth = 32,
399
+
.num_links = 2,
400
+
.links = { SM7150_SLAVE_LLCC,
401
+
SM7150_SLAVE_GEM_NOC_SNOC
402
+
},
403
+
};
404
+
405
+
static struct qcom_icc_node qnm_pcie = {
406
+
.name = "qnm_pcie",
407
+
.id = SM7150_MASTER_GEM_NOC_PCIE_SNOC,
408
+
.channels = 1,
409
+
.buswidth = 8,
410
+
.num_links = 2,
411
+
.links = { SM7150_SLAVE_LLCC,
412
+
SM7150_SLAVE_GEM_NOC_SNOC
413
+
},
414
+
};
415
+
416
+
static struct qcom_icc_node qnm_snoc_gc = {
417
+
.name = "qnm_snoc_gc",
418
+
.id = SM7150_MASTER_SNOC_GC_MEM_NOC,
419
+
.channels = 1,
420
+
.buswidth = 8,
421
+
.num_links = 1,
422
+
.links = { SM7150_SLAVE_LLCC },
423
+
};
424
+
425
+
static struct qcom_icc_node qnm_snoc_sf = {
426
+
.name = "qnm_snoc_sf",
427
+
.id = SM7150_MASTER_SNOC_SF_MEM_NOC,
428
+
.channels = 1,
429
+
.buswidth = 16,
430
+
.num_links = 1,
431
+
.links = { SM7150_SLAVE_LLCC },
432
+
};
433
+
434
+
static struct qcom_icc_node qxm_gpu = {
435
+
.name = "qxm_gpu",
436
+
.id = SM7150_MASTER_GRAPHICS_3D,
437
+
.channels = 2,
438
+
.buswidth = 32,
439
+
.num_links = 2,
440
+
.links = { SM7150_SLAVE_LLCC,
441
+
SM7150_SLAVE_GEM_NOC_SNOC
442
+
},
443
+
};
444
+
445
+
static struct qcom_icc_node llcc_mc = {
446
+
.name = "llcc_mc",
447
+
.id = SM7150_MASTER_LLCC,
448
+
.channels = 2,
449
+
.buswidth = 4,
450
+
.num_links = 1,
451
+
.links = { SM7150_SLAVE_EBI_CH0 },
452
+
};
453
+
454
+
static struct qcom_icc_node qhm_mnoc_cfg = {
455
+
.name = "qhm_mnoc_cfg",
456
+
.id = SM7150_MASTER_CNOC_MNOC_CFG,
457
+
.channels = 1,
458
+
.buswidth = 4,
459
+
.num_links = 1,
460
+
.links = { SM7150_SLAVE_SERVICE_MNOC },
461
+
};
462
+
463
+
static struct qcom_icc_node qxm_camnoc_hf = {
464
+
.name = "qxm_camnoc_hf",
465
+
.id = SM7150_MASTER_CAMNOC_HF0,
466
+
.channels = 2,
467
+
.buswidth = 32,
468
+
.num_links = 1,
469
+
.links = { SM7150_SLAVE_MNOC_HF_MEM_NOC },
470
+
};
471
+
472
+
static struct qcom_icc_node qxm_camnoc_nrt = {
473
+
.name = "qxm_camnoc_nrt",
474
+
.id = SM7150_MASTER_CAMNOC_NRT,
475
+
.channels = 1,
476
+
.buswidth = 8,
477
+
.num_links = 1,
478
+
.links = { SM7150_SLAVE_MNOC_SF_MEM_NOC },
479
+
};
480
+
481
+
static struct qcom_icc_node qxm_camnoc_rt = {
482
+
.name = "qxm_camnoc_rt",
483
+
.id = SM7150_MASTER_CAMNOC_RT,
484
+
.channels = 1,
485
+
.buswidth = 32,
486
+
.num_links = 1,
487
+
.links = { SM7150_SLAVE_MNOC_HF_MEM_NOC },
488
+
};
489
+
490
+
static struct qcom_icc_node qxm_camnoc_sf = {
491
+
.name = "qxm_camnoc_sf",
492
+
.id = SM7150_MASTER_CAMNOC_SF,
493
+
.channels = 1,
494
+
.buswidth = 32,
495
+
.num_links = 1,
496
+
.links = { SM7150_SLAVE_MNOC_SF_MEM_NOC },
497
+
};
498
+
499
+
static struct qcom_icc_node qxm_mdp0 = {
500
+
.name = "qxm_mdp0",
501
+
.id = SM7150_MASTER_MDP_PORT0,
502
+
.channels = 1,
503
+
.buswidth = 32,
504
+
.num_links = 1,
505
+
.links = { SM7150_SLAVE_MNOC_HF_MEM_NOC },
506
+
};
507
+
508
+
static struct qcom_icc_node qxm_mdp1 = {
509
+
.name = "qxm_mdp1",
510
+
.id = SM7150_MASTER_MDP_PORT1,
511
+
.channels = 1,
512
+
.buswidth = 32,
513
+
.num_links = 1,
514
+
.links = { SM7150_SLAVE_MNOC_HF_MEM_NOC },
515
+
};
516
+
517
+
static struct qcom_icc_node qxm_rot = {
518
+
.name = "qxm_rot",
519
+
.id = SM7150_MASTER_ROTATOR,
520
+
.channels = 1,
521
+
.buswidth = 32,
522
+
.num_links = 1,
523
+
.links = { SM7150_SLAVE_MNOC_SF_MEM_NOC },
524
+
};
525
+
526
+
static struct qcom_icc_node qxm_venus0 = {
527
+
.name = "qxm_venus0",
528
+
.id = SM7150_MASTER_VIDEO_P0,
529
+
.channels = 1,
530
+
.buswidth = 32,
531
+
.num_links = 1,
532
+
.links = { SM7150_SLAVE_MNOC_SF_MEM_NOC },
533
+
};
534
+
535
+
static struct qcom_icc_node qxm_venus1 = {
536
+
.name = "qxm_venus1",
537
+
.id = SM7150_MASTER_VIDEO_P1,
538
+
.channels = 1,
539
+
.buswidth = 32,
540
+
.num_links = 1,
541
+
.links = { SM7150_SLAVE_MNOC_SF_MEM_NOC },
542
+
};
543
+
544
+
static struct qcom_icc_node qxm_venus_arm9 = {
545
+
.name = "qxm_venus_arm9",
546
+
.id = SM7150_MASTER_VIDEO_PROC,
547
+
.channels = 1,
548
+
.buswidth = 8,
549
+
.num_links = 1,
550
+
.links = { SM7150_SLAVE_MNOC_SF_MEM_NOC },
551
+
};
552
+
553
+
static struct qcom_icc_node qhm_snoc_cfg = {
554
+
.name = "qhm_snoc_cfg",
555
+
.id = SM7150_MASTER_SNOC_CFG,
556
+
.channels = 1,
557
+
.buswidth = 4,
558
+
.num_links = 1,
559
+
.links = { SM7150_SLAVE_SERVICE_SNOC },
560
+
};
561
+
562
+
static struct qcom_icc_node qnm_aggre1_noc = {
563
+
.name = "qnm_aggre1_noc",
564
+
.id = SM7150_A1NOC_SNOC_MAS,
565
+
.channels = 1,
566
+
.buswidth = 16,
567
+
.num_links = 6,
568
+
.links = { SM7150_SLAVE_SNOC_GEM_NOC_SF,
569
+
SM7150_SLAVE_PIMEM,
570
+
SM7150_SLAVE_OCIMEM,
571
+
SM7150_SLAVE_APPSS,
572
+
SM7150_SNOC_CNOC_SLV,
573
+
SM7150_SLAVE_QDSS_STM
574
+
},
575
+
};
576
+
577
+
static struct qcom_icc_node qnm_aggre2_noc = {
578
+
.name = "qnm_aggre2_noc",
579
+
.id = SM7150_A2NOC_SNOC_MAS,
580
+
.channels = 1,
581
+
.buswidth = 16,
582
+
.num_links = 7,
583
+
.links = { SM7150_SLAVE_SNOC_GEM_NOC_SF,
584
+
SM7150_SLAVE_PIMEM,
585
+
SM7150_SLAVE_OCIMEM,
586
+
SM7150_SLAVE_APPSS,
587
+
SM7150_SNOC_CNOC_SLV,
588
+
SM7150_SLAVE_TCU,
589
+
SM7150_SLAVE_QDSS_STM
590
+
},
591
+
};
592
+
593
+
static struct qcom_icc_node qnm_gemnoc = {
594
+
.name = "qnm_gemnoc",
595
+
.id = SM7150_MASTER_GEM_NOC_SNOC,
596
+
.channels = 1,
597
+
.buswidth = 8,
598
+
.num_links = 6,
599
+
.links = { SM7150_SLAVE_PIMEM,
600
+
SM7150_SLAVE_OCIMEM,
601
+
SM7150_SLAVE_APPSS,
602
+
SM7150_SNOC_CNOC_SLV,
603
+
SM7150_SLAVE_TCU,
604
+
SM7150_SLAVE_QDSS_STM
605
+
},
606
+
};
607
+
608
+
static struct qcom_icc_node qxm_pimem = {
609
+
.name = "qxm_pimem",
610
+
.id = SM7150_MASTER_PIMEM,
611
+
.channels = 1,
612
+
.buswidth = 8,
613
+
.num_links = 2,
614
+
.links = { SM7150_SLAVE_SNOC_GEM_NOC_GC,
615
+
SM7150_SLAVE_OCIMEM
616
+
},
617
+
};
618
+
619
+
static struct qcom_icc_node xm_gic = {
620
+
.name = "xm_gic",
621
+
.id = SM7150_MASTER_GIC,
622
+
.channels = 1,
623
+
.buswidth = 8,
624
+
.num_links = 2,
625
+
.links = { SM7150_SLAVE_SNOC_GEM_NOC_GC,
626
+
SM7150_SLAVE_OCIMEM
627
+
},
628
+
};
629
+
630
+
static struct qcom_icc_node qns_a1noc_snoc = {
631
+
.name = "qns_a1noc_snoc",
632
+
.id = SM7150_A1NOC_SNOC_SLV,
633
+
.channels = 1,
634
+
.buswidth = 16,
635
+
.num_links = 1,
636
+
.links = { SM7150_A1NOC_SNOC_MAS },
637
+
};
638
+
639
+
static struct qcom_icc_node srvc_aggre1_noc = {
640
+
.name = "srvc_aggre1_noc",
641
+
.id = SM7150_SLAVE_SERVICE_A1NOC,
642
+
.channels = 1,
643
+
.buswidth = 4,
644
+
};
645
+
646
+
static struct qcom_icc_node qns_a2noc_snoc = {
647
+
.name = "qns_a2noc_snoc",
648
+
.id = SM7150_A2NOC_SNOC_SLV,
649
+
.channels = 1,
650
+
.buswidth = 16,
651
+
.num_links = 1,
652
+
.links = { SM7150_A2NOC_SNOC_MAS },
653
+
};
654
+
655
+
static struct qcom_icc_node qns_pcie_gemnoc = {
656
+
.name = "qns_pcie_gemnoc",
657
+
.id = SM7150_SLAVE_ANOC_PCIE_GEM_NOC,
658
+
.channels = 1,
659
+
.buswidth = 8,
660
+
.num_links = 1,
661
+
.links = { SM7150_MASTER_GEM_NOC_PCIE_SNOC },
662
+
};
663
+
664
+
static struct qcom_icc_node srvc_aggre2_noc = {
665
+
.name = "srvc_aggre2_noc",
666
+
.id = SM7150_SLAVE_SERVICE_A2NOC,
667
+
.channels = 1,
668
+
.buswidth = 4,
669
+
};
670
+
671
+
static struct qcom_icc_node qns_camnoc_uncomp = {
672
+
.name = "qns_camnoc_uncomp",
673
+
.id = SM7150_SLAVE_CAMNOC_UNCOMP,
674
+
.channels = 1,
675
+
.buswidth = 32,
676
+
};
677
+
678
+
static struct qcom_icc_node qns_cdsp_gemnoc = {
679
+
.name = "qns_cdsp_gemnoc",
680
+
.id = SM7150_SLAVE_CDSP_GEM_NOC,
681
+
.channels = 1,
682
+
.buswidth = 32,
683
+
.num_links = 1,
684
+
.links = { SM7150_MASTER_COMPUTE_NOC },
685
+
};
686
+
687
+
static struct qcom_icc_node qhs_a1_noc_cfg = {
688
+
.name = "qhs_a1_noc_cfg",
689
+
.id = SM7150_SLAVE_A1NOC_CFG,
690
+
.channels = 1,
691
+
.buswidth = 4,
692
+
.num_links = 1,
693
+
.links = { SM7150_MASTER_A1NOC_CFG },
694
+
};
695
+
696
+
static struct qcom_icc_node qhs_a2_noc_cfg = {
697
+
.name = "qhs_a2_noc_cfg",
698
+
.id = SM7150_SLAVE_A2NOC_CFG,
699
+
.channels = 1,
700
+
.buswidth = 4,
701
+
.num_links = 1,
702
+
.links = { SM7150_MASTER_A2NOC_CFG },
703
+
};
704
+
705
+
static struct qcom_icc_node qhs_ahb2phy_north = {
706
+
.name = "qhs_ahb2phy_north",
707
+
.id = SM7150_SLAVE_AHB2PHY_NORTH,
708
+
.channels = 1,
709
+
.buswidth = 4,
710
+
};
711
+
712
+
static struct qcom_icc_node qhs_ahb2phy_south = {
713
+
.name = "qhs_ahb2phy_south",
714
+
.id = SM7150_SLAVE_AHB2PHY_SOUTH,
715
+
.channels = 1,
716
+
.buswidth = 4,
717
+
};
718
+
719
+
static struct qcom_icc_node qhs_ahb2phy_west = {
720
+
.name = "qhs_ahb2phy_west",
721
+
.id = SM7150_SLAVE_AHB2PHY_WEST,
722
+
.channels = 1,
723
+
.buswidth = 4,
724
+
};
725
+
726
+
static struct qcom_icc_node qhs_aop = {
727
+
.name = "qhs_aop",
728
+
.id = SM7150_SLAVE_AOP,
729
+
.channels = 1,
730
+
.buswidth = 4,
731
+
};
732
+
733
+
static struct qcom_icc_node qhs_aoss = {
734
+
.name = "qhs_aoss",
735
+
.id = SM7150_SLAVE_AOSS,
736
+
.channels = 1,
737
+
.buswidth = 4,
738
+
};
739
+
740
+
static struct qcom_icc_node qhs_camera_cfg = {
741
+
.name = "qhs_camera_cfg",
742
+
.id = SM7150_SLAVE_CAMERA_CFG,
743
+
.channels = 1,
744
+
.buswidth = 4,
745
+
};
746
+
747
+
static struct qcom_icc_node qhs_camera_nrt_thrott_cfg = {
748
+
.name = "qhs_camera_nrt_thrott_cfg",
749
+
.id = SM7150_SLAVE_CAMERA_NRT_THROTTLE_CFG,
750
+
.channels = 1,
751
+
.buswidth = 4,
752
+
};
753
+
754
+
static struct qcom_icc_node qhs_camera_rt_throttle_cfg = {
755
+
.name = "qhs_camera_rt_throttle_cfg",
756
+
.id = SM7150_SLAVE_CAMERA_RT_THROTTLE_CFG,
757
+
.channels = 1,
758
+
.buswidth = 4,
759
+
};
760
+
761
+
static struct qcom_icc_node qhs_clk_ctl = {
762
+
.name = "qhs_clk_ctl",
763
+
.id = SM7150_SLAVE_CLK_CTL,
764
+
.channels = 1,
765
+
.buswidth = 4,
766
+
};
767
+
768
+
static struct qcom_icc_node qhs_compute_dsp_cfg = {
769
+
.name = "qhs_compute_dsp_cfg",
770
+
.id = SM7150_SLAVE_CDSP_CFG,
771
+
.channels = 1,
772
+
.buswidth = 4,
773
+
};
774
+
775
+
static struct qcom_icc_node qhs_cpr_cx = {
776
+
.name = "qhs_cpr_cx",
777
+
.id = SM7150_SLAVE_RBCPR_CX_CFG,
778
+
.channels = 1,
779
+
.buswidth = 4,
780
+
};
781
+
782
+
static struct qcom_icc_node qhs_cpr_mx = {
783
+
.name = "qhs_cpr_mx",
784
+
.id = SM7150_SLAVE_RBCPR_MX_CFG,
785
+
.channels = 1,
786
+
.buswidth = 4,
787
+
};
788
+
789
+
static struct qcom_icc_node qhs_crypto0_cfg = {
790
+
.name = "qhs_crypto0_cfg",
791
+
.id = SM7150_SLAVE_CRYPTO_0_CFG,
792
+
.channels = 1,
793
+
.buswidth = 4,
794
+
};
795
+
796
+
static struct qcom_icc_node qhs_ddrss_cfg = {
797
+
.name = "qhs_ddrss_cfg",
798
+
.id = SM7150_SLAVE_CNOC_DDRSS,
799
+
.channels = 1,
800
+
.buswidth = 4,
801
+
.num_links = 1,
802
+
.links = { SM7150_MASTER_CNOC_DC_NOC },
803
+
};
804
+
805
+
static struct qcom_icc_node qhs_display_cfg = {
806
+
.name = "qhs_display_cfg",
807
+
.id = SM7150_SLAVE_DISPLAY_CFG,
808
+
.channels = 1,
809
+
.buswidth = 4,
810
+
};
811
+
812
+
static struct qcom_icc_node qhs_display_throttle_cfg = {
813
+
.name = "qhs_display_throttle_cfg",
814
+
.id = SM7150_SLAVE_DISPLAY_THROTTLE_CFG,
815
+
.channels = 1,
816
+
.buswidth = 4,
817
+
};
818
+
819
+
static struct qcom_icc_node qhs_emmc_cfg = {
820
+
.name = "qhs_emmc_cfg",
821
+
.id = SM7150_SLAVE_EMMC_CFG,
822
+
.channels = 1,
823
+
.buswidth = 4,
824
+
};
825
+
826
+
static struct qcom_icc_node qhs_glm = {
827
+
.name = "qhs_glm",
828
+
.id = SM7150_SLAVE_GLM,
829
+
.channels = 1,
830
+
.buswidth = 4,
831
+
};
832
+
833
+
static struct qcom_icc_node qhs_gpuss_cfg = {
834
+
.name = "qhs_gpuss_cfg",
835
+
.id = SM7150_SLAVE_GRAPHICS_3D_CFG,
836
+
.channels = 1,
837
+
.buswidth = 8,
838
+
};
839
+
840
+
static struct qcom_icc_node qhs_imem_cfg = {
841
+
.name = "qhs_imem_cfg",
842
+
.id = SM7150_SLAVE_IMEM_CFG,
843
+
.channels = 1,
844
+
.buswidth = 4,
845
+
};
846
+
847
+
static struct qcom_icc_node qhs_ipa = {
848
+
.name = "qhs_ipa",
849
+
.id = SM7150_SLAVE_IPA_CFG,
850
+
.channels = 1,
851
+
.buswidth = 4,
852
+
};
853
+
854
+
static struct qcom_icc_node qhs_mnoc_cfg = {
855
+
.name = "qhs_mnoc_cfg",
856
+
.id = SM7150_SLAVE_CNOC_MNOC_CFG,
857
+
.channels = 1,
858
+
.buswidth = 4,
859
+
.num_links = 1,
860
+
.links = { SM7150_MASTER_CNOC_MNOC_CFG },
861
+
};
862
+
863
+
static struct qcom_icc_node qhs_pcie_cfg = {
864
+
.name = "qhs_pcie_cfg",
865
+
.id = SM7150_SLAVE_PCIE_CFG,
866
+
.channels = 1,
867
+
.buswidth = 4,
868
+
};
869
+
870
+
static struct qcom_icc_node qhs_pdm = {
871
+
.name = "qhs_pdm",
872
+
.id = SM7150_SLAVE_PDM,
873
+
.channels = 1,
874
+
.buswidth = 4,
875
+
};
876
+
877
+
static struct qcom_icc_node qhs_pimem_cfg = {
878
+
.name = "qhs_pimem_cfg",
879
+
.id = SM7150_SLAVE_PIMEM_CFG,
880
+
.channels = 1,
881
+
.buswidth = 4,
882
+
};
883
+
884
+
static struct qcom_icc_node qhs_prng = {
885
+
.name = "qhs_prng",
886
+
.id = SM7150_SLAVE_PRNG,
887
+
.channels = 1,
888
+
.buswidth = 4,
889
+
};
890
+
891
+
static struct qcom_icc_node qhs_qdss_cfg = {
892
+
.name = "qhs_qdss_cfg",
893
+
.id = SM7150_SLAVE_QDSS_CFG,
894
+
.channels = 1,
895
+
.buswidth = 4,
896
+
};
897
+
898
+
static struct qcom_icc_node qhs_qupv3_center = {
899
+
.name = "qhs_qupv3_center",
900
+
.id = SM7150_SLAVE_QUP_0,
901
+
.channels = 1,
902
+
.buswidth = 4,
903
+
};
904
+
905
+
static struct qcom_icc_node qhs_qupv3_north = {
906
+
.name = "qhs_qupv3_north",
907
+
.id = SM7150_SLAVE_QUP_1,
908
+
.channels = 1,
909
+
.buswidth = 4,
910
+
};
911
+
912
+
static struct qcom_icc_node qhs_sdc2 = {
913
+
.name = "qhs_sdc2",
914
+
.id = SM7150_SLAVE_SDCC_2,
915
+
.channels = 1,
916
+
.buswidth = 4,
917
+
};
918
+
919
+
static struct qcom_icc_node qhs_sdc4 = {
920
+
.name = "qhs_sdc4",
921
+
.id = SM7150_SLAVE_SDCC_4,
922
+
.channels = 1,
923
+
.buswidth = 4,
924
+
};
925
+
926
+
static struct qcom_icc_node qhs_snoc_cfg = {
927
+
.name = "qhs_snoc_cfg",
928
+
.id = SM7150_SLAVE_SNOC_CFG,
929
+
.channels = 1,
930
+
.buswidth = 4,
931
+
.num_links = 1,
932
+
.links = { SM7150_MASTER_SNOC_CFG },
933
+
};
934
+
935
+
static struct qcom_icc_node qhs_spdm = {
936
+
.name = "qhs_spdm",
937
+
.id = SM7150_SLAVE_SPDM_WRAPPER,
938
+
.channels = 1,
939
+
.buswidth = 4,
940
+
};
941
+
942
+
static struct qcom_icc_node qhs_tcsr = {
943
+
.name = "qhs_tcsr",
944
+
.id = SM7150_SLAVE_TCSR,
945
+
.channels = 1,
946
+
.buswidth = 4,
947
+
};
948
+
949
+
static struct qcom_icc_node qhs_tlmm_north = {
950
+
.name = "qhs_tlmm_north",
951
+
.id = SM7150_SLAVE_TLMM_NORTH,
952
+
.channels = 1,
953
+
.buswidth = 4,
954
+
};
955
+
956
+
static struct qcom_icc_node qhs_tlmm_south = {
957
+
.name = "qhs_tlmm_south",
958
+
.id = SM7150_SLAVE_TLMM_SOUTH,
959
+
.channels = 1,
960
+
.buswidth = 4,
961
+
};
962
+
963
+
static struct qcom_icc_node qhs_tlmm_west = {
964
+
.name = "qhs_tlmm_west",
965
+
.id = SM7150_SLAVE_TLMM_WEST,
966
+
.channels = 1,
967
+
.buswidth = 4,
968
+
};
969
+
970
+
static struct qcom_icc_node qhs_tsif = {
971
+
.name = "qhs_tsif",
972
+
.id = SM7150_SLAVE_TSIF,
973
+
.channels = 1,
974
+
.buswidth = 4,
975
+
};
976
+
977
+
static struct qcom_icc_node qhs_ufs_mem_cfg = {
978
+
.name = "qhs_ufs_mem_cfg",
979
+
.id = SM7150_SLAVE_UFS_MEM_CFG,
980
+
.channels = 1,
981
+
.buswidth = 4,
982
+
};
983
+
984
+
static struct qcom_icc_node qhs_usb3_0 = {
985
+
.name = "qhs_usb3_0",
986
+
.id = SM7150_SLAVE_USB3,
987
+
.channels = 1,
988
+
.buswidth = 4,
989
+
};
990
+
991
+
static struct qcom_icc_node qhs_venus_cfg = {
992
+
.name = "qhs_venus_cfg",
993
+
.id = SM7150_SLAVE_VENUS_CFG,
994
+
.channels = 1,
995
+
.buswidth = 4,
996
+
};
997
+
998
+
static struct qcom_icc_node qhs_venus_cvp_throttle_cfg = {
999
+
.name = "qhs_venus_cvp_throttle_cfg",
1000
+
.id = SM7150_SLAVE_VENUS_CVP_THROTTLE_CFG,
1001
+
.channels = 1,
1002
+
.buswidth = 4,
1003
+
};
1004
+
1005
+
static struct qcom_icc_node qhs_venus_throttle_cfg = {
1006
+
.name = "qhs_venus_throttle_cfg",
1007
+
.id = SM7150_SLAVE_VENUS_THROTTLE_CFG,
1008
+
.channels = 1,
1009
+
.buswidth = 4,
1010
+
};
1011
+
1012
+
static struct qcom_icc_node qhs_vsense_ctrl_cfg = {
1013
+
.name = "qhs_vsense_ctrl_cfg",
1014
+
.id = SM7150_SLAVE_VSENSE_CTRL_CFG,
1015
+
.channels = 1,
1016
+
.buswidth = 4,
1017
+
};
1018
+
1019
+
static struct qcom_icc_node qns_cnoc_a2noc = {
1020
+
.name = "qns_cnoc_a2noc",
1021
+
.id = SM7150_SLAVE_CNOC_A2NOC,
1022
+
.channels = 1,
1023
+
.buswidth = 8,
1024
+
.num_links = 1,
1025
+
.links = { SM7150_MASTER_CNOC_A2NOC },
1026
+
};
1027
+
1028
+
static struct qcom_icc_node srvc_cnoc = {
1029
+
.name = "srvc_cnoc",
1030
+
.id = SM7150_SLAVE_SERVICE_CNOC,
1031
+
.channels = 1,
1032
+
.buswidth = 4,
1033
+
};
1034
+
1035
+
static struct qcom_icc_node qhs_gemnoc = {
1036
+
.name = "qhs_gemnoc",
1037
+
.id = SM7150_SLAVE_GEM_NOC_CFG,
1038
+
.channels = 1,
1039
+
.buswidth = 4,
1040
+
.num_links = 1,
1041
+
.links = { SM7150_MASTER_GEM_NOC_CFG },
1042
+
};
1043
+
1044
+
static struct qcom_icc_node qhs_llcc = {
1045
+
.name = "qhs_llcc",
1046
+
.id = SM7150_SLAVE_LLCC_CFG,
1047
+
.channels = 1,
1048
+
.buswidth = 4,
1049
+
};
1050
+
1051
+
static struct qcom_icc_node qhs_mdsp_ms_mpu_cfg = {
1052
+
.name = "qhs_mdsp_ms_mpu_cfg",
1053
+
.id = SM7150_SLAVE_MSS_PROC_MS_MPU_CFG,
1054
+
.channels = 1,
1055
+
.buswidth = 4,
1056
+
};
1057
+
1058
+
static struct qcom_icc_node qns_gem_noc_snoc = {
1059
+
.name = "qns_gem_noc_snoc",
1060
+
.id = SM7150_SLAVE_GEM_NOC_SNOC,
1061
+
.channels = 1,
1062
+
.buswidth = 8,
1063
+
.num_links = 1,
1064
+
.links = { SM7150_MASTER_GEM_NOC_SNOC },
1065
+
};
1066
+
1067
+
static struct qcom_icc_node qns_llcc = {
1068
+
.name = "qns_llcc",
1069
+
.id = SM7150_SLAVE_LLCC,
1070
+
.channels = 2,
1071
+
.buswidth = 16,
1072
+
.num_links = 1,
1073
+
.links = { SM7150_MASTER_LLCC },
1074
+
};
1075
+
1076
+
static struct qcom_icc_node srvc_gemnoc = {
1077
+
.name = "srvc_gemnoc",
1078
+
.id = SM7150_SLAVE_SERVICE_GEM_NOC,
1079
+
.channels = 1,
1080
+
.buswidth = 4,
1081
+
};
1082
+
1083
+
static struct qcom_icc_node ebi = {
1084
+
.name = "ebi",
1085
+
.id = SM7150_SLAVE_EBI_CH0,
1086
+
.channels = 2,
1087
+
.buswidth = 4,
1088
+
};
1089
+
1090
+
static struct qcom_icc_node qns2_mem_noc = {
1091
+
.name = "qns2_mem_noc",
1092
+
.id = SM7150_SLAVE_MNOC_SF_MEM_NOC,
1093
+
.channels = 1,
1094
+
.buswidth = 32,
1095
+
.num_links = 1,
1096
+
.links = { SM7150_MASTER_MNOC_SF_MEM_NOC },
1097
+
};
1098
+
1099
+
static struct qcom_icc_node qns_mem_noc_hf = {
1100
+
.name = "qns_mem_noc_hf",
1101
+
.id = SM7150_SLAVE_MNOC_HF_MEM_NOC,
1102
+
.channels = 2,
1103
+
.buswidth = 32,
1104
+
.num_links = 1,
1105
+
.links = { SM7150_MASTER_MNOC_HF_MEM_NOC },
1106
+
};
1107
+
1108
+
static struct qcom_icc_node srvc_mnoc = {
1109
+
.name = "srvc_mnoc",
1110
+
.id = SM7150_SLAVE_SERVICE_MNOC,
1111
+
.channels = 1,
1112
+
.buswidth = 4,
1113
+
};
1114
+
1115
+
static struct qcom_icc_node qhs_apss = {
1116
+
.name = "qhs_apss",
1117
+
.id = SM7150_SLAVE_APPSS,
1118
+
.channels = 1,
1119
+
.buswidth = 8,
1120
+
};
1121
+
1122
+
static struct qcom_icc_node qns_cnoc = {
1123
+
.name = "qns_cnoc",
1124
+
.id = SM7150_SNOC_CNOC_SLV,
1125
+
.channels = 1,
1126
+
.buswidth = 8,
1127
+
.num_links = 1,
1128
+
.links = { SM7150_SNOC_CNOC_MAS },
1129
+
};
1130
+
1131
+
static struct qcom_icc_node qns_gemnoc_gc = {
1132
+
.name = "qns_gemnoc_gc",
1133
+
.id = SM7150_SLAVE_SNOC_GEM_NOC_GC,
1134
+
.channels = 1,
1135
+
.buswidth = 8,
1136
+
.num_links = 1,
1137
+
.links = { SM7150_MASTER_SNOC_GC_MEM_NOC },
1138
+
};
1139
+
1140
+
static struct qcom_icc_node qns_gemnoc_sf = {
1141
+
.name = "qns_gemnoc_sf",
1142
+
.id = SM7150_SLAVE_SNOC_GEM_NOC_SF,
1143
+
.channels = 1,
1144
+
.buswidth = 16,
1145
+
.num_links = 1,
1146
+
.links = { SM7150_MASTER_SNOC_SF_MEM_NOC },
1147
+
};
1148
+
1149
+
static struct qcom_icc_node qxs_imem = {
1150
+
.name = "qxs_imem",
1151
+
.id = SM7150_SLAVE_OCIMEM,
1152
+
.channels = 1,
1153
+
.buswidth = 8,
1154
+
};
1155
+
1156
+
static struct qcom_icc_node qxs_pimem = {
1157
+
.name = "qxs_pimem",
1158
+
.id = SM7150_SLAVE_PIMEM,
1159
+
.channels = 1,
1160
+
.buswidth = 8,
1161
+
};
1162
+
1163
+
static struct qcom_icc_node srvc_snoc = {
1164
+
.name = "srvc_snoc",
1165
+
.id = SM7150_SLAVE_SERVICE_SNOC,
1166
+
.channels = 1,
1167
+
.buswidth = 4,
1168
+
};
1169
+
1170
+
static struct qcom_icc_node xs_qdss_stm = {
1171
+
.name = "xs_qdss_stm",
1172
+
.id = SM7150_SLAVE_QDSS_STM,
1173
+
.channels = 1,
1174
+
.buswidth = 4,
1175
+
};
1176
+
1177
+
static struct qcom_icc_node xs_sys_tcu_cfg = {
1178
+
.name = "xs_sys_tcu_cfg",
1179
+
.id = SM7150_SLAVE_TCU,
1180
+
.channels = 1,
1181
+
.buswidth = 8,
1182
+
};
1183
+
1184
+
static struct qcom_icc_bcm bcm_acv = {
1185
+
.name = "ACV",
1186
+
.enable_mask = BIT(3),
1187
+
.keepalive = false,
1188
+
.num_nodes = 1,
1189
+
.nodes = { &ebi },
1190
+
};
1191
+
1192
+
static struct qcom_icc_bcm bcm_mc0 = {
1193
+
.name = "MC0",
1194
+
.keepalive = true,
1195
+
.num_nodes = 1,
1196
+
.nodes = { &ebi },
1197
+
};
1198
+
1199
+
static struct qcom_icc_bcm bcm_sh0 = {
1200
+
.name = "SH0",
1201
+
.keepalive = true,
1202
+
.num_nodes = 1,
1203
+
.nodes = { &qns_llcc },
1204
+
};
1205
+
1206
+
static struct qcom_icc_bcm bcm_mm0 = {
1207
+
.name = "MM0",
1208
+
.keepalive = true,
1209
+
.num_nodes = 1,
1210
+
.nodes = { &qns_mem_noc_hf },
1211
+
};
1212
+
1213
+
static struct qcom_icc_bcm bcm_mm1 = {
1214
+
.name = "MM1",
1215
+
.keepalive = true,
1216
+
.num_nodes = 8,
1217
+
.nodes = { &qxm_camnoc_hf0_uncomp,
1218
+
&qxm_camnoc_rt_uncomp,
1219
+
&qxm_camnoc_sf_uncomp,
1220
+
&qxm_camnoc_nrt_uncomp,
1221
+
&qxm_camnoc_hf,
1222
+
&qxm_camnoc_rt,
1223
+
&qxm_mdp0,
1224
+
&qxm_mdp1
1225
+
},
1226
+
};
1227
+
1228
+
static struct qcom_icc_bcm bcm_sh2 = {
1229
+
.name = "SH2",
1230
+
.keepalive = false,
1231
+
.num_nodes = 1,
1232
+
.nodes = { &qns_gem_noc_snoc },
1233
+
};
1234
+
1235
+
static struct qcom_icc_bcm bcm_sh3 = {
1236
+
.name = "SH3",
1237
+
.keepalive = false,
1238
+
.num_nodes = 1,
1239
+
.nodes = { &acm_sys_tcu },
1240
+
};
1241
+
1242
+
static struct qcom_icc_bcm bcm_mm2 = {
1243
+
.name = "MM2",
1244
+
.keepalive = false,
1245
+
.num_nodes = 2,
1246
+
.nodes = { &qxm_camnoc_nrt,
1247
+
&qns2_mem_noc
1248
+
},
1249
+
};
1250
+
1251
+
static struct qcom_icc_bcm bcm_mm3 = {
1252
+
.name = "MM3",
1253
+
.keepalive = false,
1254
+
.num_nodes = 5,
1255
+
.nodes = { &qxm_camnoc_sf,
1256
+
&qxm_rot,
1257
+
&qxm_venus0,
1258
+
&qxm_venus1,
1259
+
&qxm_venus_arm9
1260
+
},
1261
+
};
1262
+
1263
+
static struct qcom_icc_bcm bcm_sh5 = {
1264
+
.name = "SH5",
1265
+
.keepalive = false,
1266
+
.num_nodes = 1,
1267
+
.nodes = { &acm_apps },
1268
+
};
1269
+
1270
+
static struct qcom_icc_bcm bcm_sn0 = {
1271
+
.name = "SN0",
1272
+
.keepalive = true,
1273
+
.num_nodes = 1,
1274
+
.nodes = { &qns_gemnoc_sf },
1275
+
};
1276
+
1277
+
static struct qcom_icc_bcm bcm_sh8 = {
1278
+
.name = "SH8",
1279
+
.keepalive = false,
1280
+
.num_nodes = 1,
1281
+
.nodes = { &qns_cdsp_gemnoc },
1282
+
};
1283
+
1284
+
static struct qcom_icc_bcm bcm_sh10 = {
1285
+
.name = "SH10",
1286
+
.keepalive = false,
1287
+
.num_nodes = 1,
1288
+
.nodes = { &qnm_npu },
1289
+
};
1290
+
1291
+
static struct qcom_icc_bcm bcm_ce0 = {
1292
+
.name = "CE0",
1293
+
.keepalive = false,
1294
+
.num_nodes = 1,
1295
+
.nodes = { &qxm_crypto },
1296
+
};
1297
+
1298
+
static struct qcom_icc_bcm bcm_cn0 = {
1299
+
.name = "CN0",
1300
+
.keepalive = true,
1301
+
.num_nodes = 54,
1302
+
.nodes = { &qhm_tsif,
1303
+
&xm_emmc,
1304
+
&xm_sdc2,
1305
+
&xm_sdc4,
1306
+
&qhm_spdm,
1307
+
&qnm_snoc,
1308
+
&qhs_a1_noc_cfg,
1309
+
&qhs_a2_noc_cfg,
1310
+
&qhs_ahb2phy_north,
1311
+
&qhs_ahb2phy_south,
1312
+
&qhs_ahb2phy_west,
1313
+
&qhs_aop,
1314
+
&qhs_aoss,
1315
+
&qhs_camera_cfg,
1316
+
&qhs_camera_nrt_thrott_cfg,
1317
+
&qhs_camera_rt_throttle_cfg,
1318
+
&qhs_clk_ctl,
1319
+
&qhs_compute_dsp_cfg,
1320
+
&qhs_cpr_cx,
1321
+
&qhs_cpr_mx,
1322
+
&qhs_crypto0_cfg,
1323
+
&qhs_ddrss_cfg,
1324
+
&qhs_display_cfg,
1325
+
&qhs_display_throttle_cfg,
1326
+
&qhs_emmc_cfg,
1327
+
&qhs_glm,
1328
+
&qhs_gpuss_cfg,
1329
+
&qhs_imem_cfg,
1330
+
&qhs_ipa,
1331
+
&qhs_mnoc_cfg,
1332
+
&qhs_pcie_cfg,
1333
+
&qhs_pdm,
1334
+
&qhs_pimem_cfg,
1335
+
&qhs_prng,
1336
+
&qhs_qdss_cfg,
1337
+
&qhs_qupv3_center,
1338
+
&qhs_qupv3_north,
1339
+
&qhs_sdc2,
1340
+
&qhs_sdc4,
1341
+
&qhs_snoc_cfg,
1342
+
&qhs_spdm,
1343
+
&qhs_tcsr,
1344
+
&qhs_tlmm_north,
1345
+
&qhs_tlmm_south,
1346
+
&qhs_tlmm_west,
1347
+
&qhs_tsif,
1348
+
&qhs_ufs_mem_cfg,
1349
+
&qhs_usb3_0,
1350
+
&qhs_venus_cfg,
1351
+
&qhs_venus_cvp_throttle_cfg,
1352
+
&qhs_venus_throttle_cfg,
1353
+
&qhs_vsense_ctrl_cfg,
1354
+
&qns_cnoc_a2noc,
1355
+
&srvc_cnoc
1356
+
},
1357
+
};
1358
+
1359
+
static struct qcom_icc_bcm bcm_qup0 = {
1360
+
.name = "QUP0",
1361
+
.keepalive = false,
1362
+
.num_nodes = 2,
1363
+
.nodes = { &qhm_qup_center,
1364
+
&qhm_qup_north
1365
+
},
1366
+
};
1367
+
1368
+
static struct qcom_icc_bcm bcm_sn1 = {
1369
+
.name = "SN1",
1370
+
.keepalive = false,
1371
+
.num_nodes = 1,
1372
+
.nodes = { &qxs_imem },
1373
+
};
1374
+
1375
+
static struct qcom_icc_bcm bcm_sn2 = {
1376
+
.name = "SN2",
1377
+
.keepalive = false,
1378
+
.num_nodes = 1,
1379
+
.nodes = { &qns_gemnoc_gc },
1380
+
};
1381
+
1382
+
static struct qcom_icc_bcm bcm_sn4 = {
1383
+
.name = "SN4",
1384
+
.keepalive = false,
1385
+
.num_nodes = 1,
1386
+
.nodes = { &qxs_pimem },
1387
+
};
1388
+
1389
+
static struct qcom_icc_bcm bcm_sn9 = {
1390
+
.name = "SN9",
1391
+
.keepalive = false,
1392
+
.num_nodes = 2,
1393
+
.nodes = { &qnm_aggre1_noc,
1394
+
&qns_a1noc_snoc
1395
+
},
1396
+
};
1397
+
1398
+
static struct qcom_icc_bcm bcm_sn11 = {
1399
+
.name = "SN11",
1400
+
.keepalive = false,
1401
+
.num_nodes = 2,
1402
+
.nodes = { &qnm_aggre2_noc,
1403
+
&qns_a2noc_snoc
1404
+
},
1405
+
};
1406
+
1407
+
static struct qcom_icc_bcm bcm_sn12 = {
1408
+
.name = "SN12",
1409
+
.keepalive = false,
1410
+
.num_nodes = 2,
1411
+
.nodes = { &qxm_pimem,
1412
+
&xm_gic
1413
+
},
1414
+
};
1415
+
1416
+
static struct qcom_icc_bcm bcm_sn14 = {
1417
+
.name = "SN14",
1418
+
.keepalive = false,
1419
+
.num_nodes = 1,
1420
+
.nodes = { &qns_pcie_gemnoc },
1421
+
};
1422
+
1423
+
static struct qcom_icc_bcm bcm_sn15 = {
1424
+
.name = "SN15",
1425
+
.keepalive = false,
1426
+
.num_nodes = 1,
1427
+
.nodes = { &qnm_gemnoc },
1428
+
};
1429
+
1430
+
static struct qcom_icc_bcm * const aggre1_noc_bcms[] = {
1431
+
&bcm_cn0,
1432
+
&bcm_qup0,
1433
+
&bcm_sn9,
1434
+
};
1435
+
1436
+
static struct qcom_icc_node * const aggre1_noc_nodes[] = {
1437
+
[MASTER_A1NOC_CFG] = &qhm_a1noc_cfg,
1438
+
[MASTER_QUP_0] = &qhm_qup_center,
1439
+
[MASTER_TSIF] = &qhm_tsif,
1440
+
[MASTER_EMMC] = &xm_emmc,
1441
+
[MASTER_SDCC_2] = &xm_sdc2,
1442
+
[MASTER_SDCC_4] = &xm_sdc4,
1443
+
[MASTER_UFS_MEM] = &xm_ufs_mem,
1444
+
[A1NOC_SNOC_SLV] = &qns_a1noc_snoc,
1445
+
[SLAVE_SERVICE_A1NOC] = &srvc_aggre1_noc,
1446
+
};
1447
+
1448
+
static const struct qcom_icc_desc sm7150_aggre1_noc = {
1449
+
.nodes = aggre1_noc_nodes,
1450
+
.num_nodes = ARRAY_SIZE(aggre1_noc_nodes),
1451
+
.bcms = aggre1_noc_bcms,
1452
+
.num_bcms = ARRAY_SIZE(aggre1_noc_bcms),
1453
+
};
1454
+
1455
+
static struct qcom_icc_bcm * const aggre2_noc_bcms[] = {
1456
+
&bcm_ce0,
1457
+
&bcm_qup0,
1458
+
&bcm_sn11,
1459
+
&bcm_sn14,
1460
+
};
1461
+
1462
+
static struct qcom_icc_node * const aggre2_noc_nodes[] = {
1463
+
[MASTER_A2NOC_CFG] = &qhm_a2noc_cfg,
1464
+
[MASTER_QDSS_BAM] = &qhm_qdss_bam,
1465
+
[MASTER_QUP_1] = &qhm_qup_north,
1466
+
[MASTER_CNOC_A2NOC] = &qnm_cnoc,
1467
+
[MASTER_CRYPTO_CORE_0] = &qxm_crypto,
1468
+
[MASTER_IPA] = &qxm_ipa,
1469
+
[MASTER_PCIE] = &xm_pcie3_0,
1470
+
[MASTER_QDSS_ETR] = &xm_qdss_etr,
1471
+
[MASTER_USB3] = &xm_usb3_0,
1472
+
[A2NOC_SNOC_SLV] = &qns_a2noc_snoc,
1473
+
[SLAVE_ANOC_PCIE_GEM_NOC] = &qns_pcie_gemnoc,
1474
+
[SLAVE_SERVICE_A2NOC] = &srvc_aggre2_noc,
1475
+
};
1476
+
1477
+
static const struct qcom_icc_desc sm7150_aggre2_noc = {
1478
+
.nodes = aggre2_noc_nodes,
1479
+
.num_nodes = ARRAY_SIZE(aggre2_noc_nodes),
1480
+
.bcms = aggre2_noc_bcms,
1481
+
.num_bcms = ARRAY_SIZE(aggre2_noc_bcms),
1482
+
};
1483
+
1484
+
static struct qcom_icc_bcm * const camnoc_virt_bcms[] = {
1485
+
&bcm_mm1,
1486
+
};
1487
+
1488
+
static struct qcom_icc_node * const camnoc_virt_nodes[] = {
1489
+
[MASTER_CAMNOC_HF0_UNCOMP] = &qxm_camnoc_hf0_uncomp,
1490
+
[MASTER_CAMNOC_RT_UNCOMP] = &qxm_camnoc_rt_uncomp,
1491
+
[MASTER_CAMNOC_SF_UNCOMP] = &qxm_camnoc_sf_uncomp,
1492
+
[MASTER_CAMNOC_NRT_UNCOMP] = &qxm_camnoc_nrt_uncomp,
1493
+
[SLAVE_CAMNOC_UNCOMP] = &qns_camnoc_uncomp,
1494
+
};
1495
+
1496
+
static const struct qcom_icc_desc sm7150_camnoc_virt = {
1497
+
.nodes = camnoc_virt_nodes,
1498
+
.num_nodes = ARRAY_SIZE(camnoc_virt_nodes),
1499
+
.bcms = camnoc_virt_bcms,
1500
+
.num_bcms = ARRAY_SIZE(camnoc_virt_bcms),
1501
+
};
1502
+
1503
+
static struct qcom_icc_bcm * const compute_noc_bcms[] = {
1504
+
&bcm_sh10,
1505
+
&bcm_sh8,
1506
+
};
1507
+
1508
+
static struct qcom_icc_node * const compute_noc_nodes[] = {
1509
+
[MASTER_NPU] = &qnm_npu,
1510
+
[SLAVE_CDSP_GEM_NOC] = &qns_cdsp_gemnoc,
1511
+
};
1512
+
1513
+
static const struct qcom_icc_desc sm7150_compute_noc = {
1514
+
.nodes = compute_noc_nodes,
1515
+
.num_nodes = ARRAY_SIZE(compute_noc_nodes),
1516
+
.bcms = compute_noc_bcms,
1517
+
.num_bcms = ARRAY_SIZE(compute_noc_bcms),
1518
+
};
1519
+
1520
+
static struct qcom_icc_bcm * const config_noc_bcms[] = {
1521
+
&bcm_cn0,
1522
+
};
1523
+
1524
+
static struct qcom_icc_node * const config_noc_nodes[] = {
1525
+
[MASTER_SPDM] = &qhm_spdm,
1526
+
[SNOC_CNOC_MAS] = &qnm_snoc,
1527
+
[MASTER_QDSS_DAP] = &xm_qdss_dap,
1528
+
[SLAVE_A1NOC_CFG] = &qhs_a1_noc_cfg,
1529
+
[SLAVE_A2NOC_CFG] = &qhs_a2_noc_cfg,
1530
+
[SLAVE_AHB2PHY_NORTH] = &qhs_ahb2phy_north,
1531
+
[SLAVE_AHB2PHY_SOUTH] = &qhs_ahb2phy_south,
1532
+
[SLAVE_AHB2PHY_WEST] = &qhs_ahb2phy_west,
1533
+
[SLAVE_AOP] = &qhs_aop,
1534
+
[SLAVE_AOSS] = &qhs_aoss,
1535
+
[SLAVE_CAMERA_CFG] = &qhs_camera_cfg,
1536
+
[SLAVE_CAMERA_NRT_THROTTLE_CFG] = &qhs_camera_nrt_thrott_cfg,
1537
+
[SLAVE_CAMERA_RT_THROTTLE_CFG] = &qhs_camera_rt_throttle_cfg,
1538
+
[SLAVE_CLK_CTL] = &qhs_clk_ctl,
1539
+
[SLAVE_CDSP_CFG] = &qhs_compute_dsp_cfg,
1540
+
[SLAVE_RBCPR_CX_CFG] = &qhs_cpr_cx,
1541
+
[SLAVE_RBCPR_MX_CFG] = &qhs_cpr_mx,
1542
+
[SLAVE_CRYPTO_0_CFG] = &qhs_crypto0_cfg,
1543
+
[SLAVE_CNOC_DDRSS] = &qhs_ddrss_cfg,
1544
+
[SLAVE_DISPLAY_CFG] = &qhs_display_cfg,
1545
+
[SLAVE_DISPLAY_THROTTLE_CFG] = &qhs_display_throttle_cfg,
1546
+
[SLAVE_EMMC_CFG] = &qhs_emmc_cfg,
1547
+
[SLAVE_GLM] = &qhs_glm,
1548
+
[SLAVE_GRAPHICS_3D_CFG] = &qhs_gpuss_cfg,
1549
+
[SLAVE_IMEM_CFG] = &qhs_imem_cfg,
1550
+
[SLAVE_IPA_CFG] = &qhs_ipa,
1551
+
[SLAVE_CNOC_MNOC_CFG] = &qhs_mnoc_cfg,
1552
+
[SLAVE_PCIE_CFG] = &qhs_pcie_cfg,
1553
+
[SLAVE_PDM] = &qhs_pdm,
1554
+
[SLAVE_PIMEM_CFG] = &qhs_pimem_cfg,
1555
+
[SLAVE_PRNG] = &qhs_prng,
1556
+
[SLAVE_QDSS_CFG] = &qhs_qdss_cfg,
1557
+
[SLAVE_QUP_0] = &qhs_qupv3_center,
1558
+
[SLAVE_QUP_1] = &qhs_qupv3_north,
1559
+
[SLAVE_SDCC_2] = &qhs_sdc2,
1560
+
[SLAVE_SDCC_4] = &qhs_sdc4,
1561
+
[SLAVE_SNOC_CFG] = &qhs_snoc_cfg,
1562
+
[SLAVE_SPDM_WRAPPER] = &qhs_spdm,
1563
+
[SLAVE_TCSR] = &qhs_tcsr,
1564
+
[SLAVE_TLMM_NORTH] = &qhs_tlmm_north,
1565
+
[SLAVE_TLMM_SOUTH] = &qhs_tlmm_south,
1566
+
[SLAVE_TLMM_WEST] = &qhs_tlmm_west,
1567
+
[SLAVE_TSIF] = &qhs_tsif,
1568
+
[SLAVE_UFS_MEM_CFG] = &qhs_ufs_mem_cfg,
1569
+
[SLAVE_USB3] = &qhs_usb3_0,
1570
+
[SLAVE_VENUS_CFG] = &qhs_venus_cfg,
1571
+
[SLAVE_VENUS_CVP_THROTTLE_CFG] = &qhs_venus_cvp_throttle_cfg,
1572
+
[SLAVE_VENUS_THROTTLE_CFG] = &qhs_venus_throttle_cfg,
1573
+
[SLAVE_VSENSE_CTRL_CFG] = &qhs_vsense_ctrl_cfg,
1574
+
[SLAVE_CNOC_A2NOC] = &qns_cnoc_a2noc,
1575
+
[SLAVE_SERVICE_CNOC] = &srvc_cnoc,
1576
+
};
1577
+
1578
+
static const struct qcom_icc_desc sm7150_config_noc = {
1579
+
.nodes = config_noc_nodes,
1580
+
.num_nodes = ARRAY_SIZE(config_noc_nodes),
1581
+
.bcms = config_noc_bcms,
1582
+
.num_bcms = ARRAY_SIZE(config_noc_bcms),
1583
+
};
1584
+
1585
+
static struct qcom_icc_bcm * const dc_noc_bcms[] = {
1586
+
};
1587
+
1588
+
static struct qcom_icc_node * const dc_noc_nodes[] = {
1589
+
[MASTER_CNOC_DC_NOC] = &qhm_cnoc_dc_noc,
1590
+
[SLAVE_GEM_NOC_CFG] = &qhs_gemnoc,
1591
+
[SLAVE_LLCC_CFG] = &qhs_llcc,
1592
+
};
1593
+
1594
+
static const struct qcom_icc_desc sm7150_dc_noc = {
1595
+
.nodes = dc_noc_nodes,
1596
+
.num_nodes = ARRAY_SIZE(dc_noc_nodes),
1597
+
.bcms = dc_noc_bcms,
1598
+
.num_bcms = ARRAY_SIZE(dc_noc_bcms),
1599
+
};
1600
+
1601
+
static struct qcom_icc_bcm * const gem_noc_bcms[] = {
1602
+
&bcm_sh0,
1603
+
&bcm_sh2,
1604
+
&bcm_sh3,
1605
+
&bcm_sh5,
1606
+
};
1607
+
1608
+
static struct qcom_icc_node * const gem_noc_nodes[] = {
1609
+
[MASTER_AMPSS_M0] = &acm_apps,
1610
+
[MASTER_SYS_TCU] = &acm_sys_tcu,
1611
+
[MASTER_GEM_NOC_CFG] = &qhm_gemnoc_cfg,
1612
+
[MASTER_COMPUTE_NOC] = &qnm_cmpnoc,
1613
+
[MASTER_MNOC_HF_MEM_NOC] = &qnm_mnoc_hf,
1614
+
[MASTER_MNOC_SF_MEM_NOC] = &qnm_mnoc_sf,
1615
+
[MASTER_GEM_NOC_PCIE_SNOC] = &qnm_pcie,
1616
+
[MASTER_SNOC_GC_MEM_NOC] = &qnm_snoc_gc,
1617
+
[MASTER_SNOC_SF_MEM_NOC] = &qnm_snoc_sf,
1618
+
[MASTER_GRAPHICS_3D] = &qxm_gpu,
1619
+
[SLAVE_MSS_PROC_MS_MPU_CFG] = &qhs_mdsp_ms_mpu_cfg,
1620
+
[SLAVE_GEM_NOC_SNOC] = &qns_gem_noc_snoc,
1621
+
[SLAVE_LLCC] = &qns_llcc,
1622
+
[SLAVE_SERVICE_GEM_NOC] = &srvc_gemnoc,
1623
+
};
1624
+
1625
+
static const struct qcom_icc_desc sm7150_gem_noc = {
1626
+
.nodes = gem_noc_nodes,
1627
+
.num_nodes = ARRAY_SIZE(gem_noc_nodes),
1628
+
.bcms = gem_noc_bcms,
1629
+
.num_bcms = ARRAY_SIZE(gem_noc_bcms),
1630
+
};
1631
+
1632
+
static struct qcom_icc_bcm * const mc_virt_bcms[] = {
1633
+
&bcm_acv,
1634
+
&bcm_mc0,
1635
+
};
1636
+
1637
+
static struct qcom_icc_node * const mc_virt_nodes[] = {
1638
+
[MASTER_LLCC] = &llcc_mc,
1639
+
[SLAVE_EBI_CH0] = &ebi,
1640
+
};
1641
+
1642
+
static const struct qcom_icc_desc sm7150_mc_virt = {
1643
+
.nodes = mc_virt_nodes,
1644
+
.num_nodes = ARRAY_SIZE(mc_virt_nodes),
1645
+
.bcms = mc_virt_bcms,
1646
+
.num_bcms = ARRAY_SIZE(mc_virt_bcms),
1647
+
};
1648
+
1649
+
static struct qcom_icc_bcm * const mmss_noc_bcms[] = {
1650
+
&bcm_mm0,
1651
+
&bcm_mm1,
1652
+
&bcm_mm2,
1653
+
&bcm_mm3,
1654
+
};
1655
+
1656
+
static struct qcom_icc_node * const mmss_noc_nodes[] = {
1657
+
[MASTER_CNOC_MNOC_CFG] = &qhm_mnoc_cfg,
1658
+
[MASTER_CAMNOC_HF0] = &qxm_camnoc_hf,
1659
+
[MASTER_CAMNOC_NRT] = &qxm_camnoc_nrt,
1660
+
[MASTER_CAMNOC_RT] = &qxm_camnoc_rt,
1661
+
[MASTER_CAMNOC_SF] = &qxm_camnoc_sf,
1662
+
[MASTER_MDP_PORT0] = &qxm_mdp0,
1663
+
[MASTER_MDP_PORT1] = &qxm_mdp1,
1664
+
[MASTER_ROTATOR] = &qxm_rot,
1665
+
[MASTER_VIDEO_P0] = &qxm_venus0,
1666
+
[MASTER_VIDEO_P1] = &qxm_venus1,
1667
+
[MASTER_VIDEO_PROC] = &qxm_venus_arm9,
1668
+
[SLAVE_MNOC_SF_MEM_NOC] = &qns2_mem_noc,
1669
+
[SLAVE_MNOC_HF_MEM_NOC] = &qns_mem_noc_hf,
1670
+
[SLAVE_SERVICE_MNOC] = &srvc_mnoc,
1671
+
};
1672
+
1673
+
static const struct qcom_icc_desc sm7150_mmss_noc = {
1674
+
.nodes = mmss_noc_nodes,
1675
+
.num_nodes = ARRAY_SIZE(mmss_noc_nodes),
1676
+
.bcms = mmss_noc_bcms,
1677
+
.num_bcms = ARRAY_SIZE(mmss_noc_bcms),
1678
+
};
1679
+
1680
+
static struct qcom_icc_bcm * const system_noc_bcms[] = {
1681
+
&bcm_sn0,
1682
+
&bcm_sn1,
1683
+
&bcm_sn11,
1684
+
&bcm_sn12,
1685
+
&bcm_sn15,
1686
+
&bcm_sn2,
1687
+
&bcm_sn4,
1688
+
&bcm_sn9,
1689
+
};
1690
+
1691
+
static struct qcom_icc_node * const system_noc_nodes[] = {
1692
+
[MASTER_SNOC_CFG] = &qhm_snoc_cfg,
1693
+
[A1NOC_SNOC_MAS] = &qnm_aggre1_noc,
1694
+
[A2NOC_SNOC_MAS] = &qnm_aggre2_noc,
1695
+
[MASTER_GEM_NOC_SNOC] = &qnm_gemnoc,
1696
+
[MASTER_PIMEM] = &qxm_pimem,
1697
+
[MASTER_GIC] = &xm_gic,
1698
+
[SLAVE_APPSS] = &qhs_apss,
1699
+
[SNOC_CNOC_SLV] = &qns_cnoc,
1700
+
[SLAVE_SNOC_GEM_NOC_GC] = &qns_gemnoc_gc,
1701
+
[SLAVE_SNOC_GEM_NOC_SF] = &qns_gemnoc_sf,
1702
+
[SLAVE_OCIMEM] = &qxs_imem,
1703
+
[SLAVE_PIMEM] = &qxs_pimem,
1704
+
[SLAVE_SERVICE_SNOC] = &srvc_snoc,
1705
+
[SLAVE_QDSS_STM] = &xs_qdss_stm,
1706
+
[SLAVE_TCU] = &xs_sys_tcu_cfg,
1707
+
};
1708
+
1709
+
static const struct qcom_icc_desc sm7150_system_noc = {
1710
+
.nodes = system_noc_nodes,
1711
+
.num_nodes = ARRAY_SIZE(system_noc_nodes),
1712
+
.bcms = system_noc_bcms,
1713
+
.num_bcms = ARRAY_SIZE(system_noc_bcms),
1714
+
};
1715
+
1716
+
static const struct of_device_id qnoc_of_match[] = {
1717
+
{ .compatible = "qcom,sm7150-aggre1-noc", .data = &sm7150_aggre1_noc },
1718
+
{ .compatible = "qcom,sm7150-aggre2-noc", .data = &sm7150_aggre2_noc },
1719
+
{ .compatible = "qcom,sm7150-camnoc-virt", .data = &sm7150_camnoc_virt },
1720
+
{ .compatible = "qcom,sm7150-compute-noc", .data = &sm7150_compute_noc },
1721
+
{ .compatible = "qcom,sm7150-config-noc", .data = &sm7150_config_noc },
1722
+
{ .compatible = "qcom,sm7150-dc-noc", .data = &sm7150_dc_noc },
1723
+
{ .compatible = "qcom,sm7150-gem-noc", .data = &sm7150_gem_noc },
1724
+
{ .compatible = "qcom,sm7150-mc-virt", .data = &sm7150_mc_virt },
1725
+
{ .compatible = "qcom,sm7150-mmss-noc", .data = &sm7150_mmss_noc },
1726
+
{ .compatible = "qcom,sm7150-system-noc", .data = &sm7150_system_noc },
1727
+
{ }
1728
+
};
1729
+
MODULE_DEVICE_TABLE(of, qnoc_of_match);
1730
+
1731
+
static struct platform_driver qnoc_driver = {
1732
+
.probe = qcom_icc_rpmh_probe,
1733
+
.remove_new = qcom_icc_rpmh_remove,
1734
+
.driver = {
1735
+
.name = "qnoc-sm7150",
1736
+
.of_match_table = qnoc_of_match,
1737
+
.sync_state = icc_sync_state,
1738
+
},
1739
+
};
1740
+
1741
+
static int __init qnoc_driver_init(void)
1742
+
{
1743
+
return platform_driver_register(&qnoc_driver);
1744
+
}
1745
+
core_initcall(qnoc_driver_init);
1746
+
1747
+
static void __exit qnoc_driver_exit(void)
1748
+
{
1749
+
platform_driver_unregister(&qnoc_driver);
1750
+
}
1751
+
module_exit(qnoc_driver_exit);
1752
+
1753
+
MODULE_DESCRIPTION("Qualcomm SM7150 NoC driver");
1754
+
MODULE_LICENSE("GPL");
+140
drivers/interconnect/qcom/sm7150.h
+140
drivers/interconnect/qcom/sm7150.h
···
1
+
/* SPDX-License-Identifier: GPL-2.0-only */
2
+
/*
3
+
* Qualcomm #define SM7150 interconnect IDs
4
+
*
5
+
* Copyright (c) 2020, The Linux Foundation. All rights reserved.
6
+
* Copyright (c) 2024, Danila Tikhonov <danila@jiaxyga.com>
7
+
*/
8
+
9
+
#ifndef __DRIVERS_INTERCONNECT_QCOM_SM7150_H
10
+
#define __DRIVERS_INTERCONNECT_QCOM_SM7150_H
11
+
12
+
#define SM7150_A1NOC_SNOC_MAS 0
13
+
#define SM7150_A1NOC_SNOC_SLV 1
14
+
#define SM7150_A2NOC_SNOC_MAS 2
15
+
#define SM7150_A2NOC_SNOC_SLV 3
16
+
#define SM7150_MASTER_A1NOC_CFG 4
17
+
#define SM7150_MASTER_A2NOC_CFG 5
18
+
#define SM7150_MASTER_AMPSS_M0 6
19
+
#define SM7150_MASTER_CAMNOC_HF0 7
20
+
#define SM7150_MASTER_CAMNOC_HF0_UNCOMP 8
21
+
#define SM7150_MASTER_CAMNOC_NRT 9
22
+
#define SM7150_MASTER_CAMNOC_NRT_UNCOMP 10
23
+
#define SM7150_MASTER_CAMNOC_RT 11
24
+
#define SM7150_MASTER_CAMNOC_RT_UNCOMP 12
25
+
#define SM7150_MASTER_CAMNOC_SF 13
26
+
#define SM7150_MASTER_CAMNOC_SF_UNCOMP 14
27
+
#define SM7150_MASTER_CNOC_A2NOC 15
28
+
#define SM7150_MASTER_CNOC_DC_NOC 16
29
+
#define SM7150_MASTER_CNOC_MNOC_CFG 17
30
+
#define SM7150_MASTER_COMPUTE_NOC 18
31
+
#define SM7150_MASTER_CRYPTO_CORE_0 19
32
+
#define SM7150_MASTER_EMMC 20
33
+
#define SM7150_MASTER_GEM_NOC_CFG 21
34
+
#define SM7150_MASTER_GEM_NOC_PCIE_SNOC 22
35
+
#define SM7150_MASTER_GEM_NOC_SNOC 23
36
+
#define SM7150_MASTER_GIC 24
37
+
#define SM7150_MASTER_GRAPHICS_3D 25
38
+
#define SM7150_MASTER_IPA 26
39
+
#define SM7150_MASTER_LLCC 27
40
+
#define SM7150_MASTER_MDP_PORT0 28
41
+
#define SM7150_MASTER_MDP_PORT1 29
42
+
#define SM7150_MASTER_MNOC_HF_MEM_NOC 30
43
+
#define SM7150_MASTER_MNOC_SF_MEM_NOC 31
44
+
#define SM7150_MASTER_NPU 32
45
+
#define SM7150_MASTER_PCIE 33
46
+
#define SM7150_MASTER_PIMEM 34
47
+
#define SM7150_MASTER_QDSS_BAM 35
48
+
#define SM7150_MASTER_QDSS_DAP 36
49
+
#define SM7150_MASTER_QDSS_ETR 37
50
+
#define SM7150_MASTER_QUP_0 38
51
+
#define SM7150_MASTER_QUP_1 39
52
+
#define SM7150_MASTER_ROTATOR 40
53
+
#define SM7150_MASTER_SDCC_2 41
54
+
#define SM7150_MASTER_SDCC_4 42
55
+
#define SM7150_MASTER_SNOC_CFG 43
56
+
#define SM7150_MASTER_SNOC_GC_MEM_NOC 44
57
+
#define SM7150_MASTER_SNOC_SF_MEM_NOC 45
58
+
#define SM7150_MASTER_SPDM 46
59
+
#define SM7150_MASTER_SYS_TCU 47
60
+
#define SM7150_MASTER_TSIF 48
61
+
#define SM7150_MASTER_UFS_MEM 49
62
+
#define SM7150_MASTER_USB3 50
63
+
#define SM7150_MASTER_VIDEO_P0 51
64
+
#define SM7150_MASTER_VIDEO_P1 52
65
+
#define SM7150_MASTER_VIDEO_PROC 53
66
+
#define SM7150_SLAVE_A1NOC_CFG 54
67
+
#define SM7150_SLAVE_A2NOC_CFG 55
68
+
#define SM7150_SLAVE_AHB2PHY_NORTH 56
69
+
#define SM7150_SLAVE_AHB2PHY_SOUTH 57
70
+
#define SM7150_SLAVE_AHB2PHY_WEST 58
71
+
#define SM7150_SLAVE_ANOC_PCIE_GEM_NOC 59
72
+
#define SM7150_SLAVE_AOP 60
73
+
#define SM7150_SLAVE_AOSS 61
74
+
#define SM7150_SLAVE_APPSS 62
75
+
#define SM7150_SLAVE_CAMERA_CFG 63
76
+
#define SM7150_SLAVE_CAMERA_NRT_THROTTLE_CFG 64
77
+
#define SM7150_SLAVE_CAMERA_RT_THROTTLE_CFG 65
78
+
#define SM7150_SLAVE_CAMNOC_UNCOMP 66
79
+
#define SM7150_SLAVE_CDSP_CFG 67
80
+
#define SM7150_SLAVE_CDSP_GEM_NOC 68
81
+
#define SM7150_SLAVE_CLK_CTL 69
82
+
#define SM7150_SLAVE_CNOC_A2NOC 70
83
+
#define SM7150_SLAVE_CNOC_DDRSS 71
84
+
#define SM7150_SLAVE_CNOC_MNOC_CFG 72
85
+
#define SM7150_SLAVE_CRYPTO_0_CFG 73
86
+
#define SM7150_SLAVE_DISPLAY_CFG 74
87
+
#define SM7150_SLAVE_DISPLAY_THROTTLE_CFG 75
88
+
#define SM7150_SLAVE_EBI_CH0 76
89
+
#define SM7150_SLAVE_EMMC_CFG 77
90
+
#define SM7150_SLAVE_GEM_NOC_CFG 78
91
+
#define SM7150_SLAVE_GEM_NOC_SNOC 79
92
+
#define SM7150_SLAVE_GLM 80
93
+
#define SM7150_SLAVE_GRAPHICS_3D_CFG 81
94
+
#define SM7150_SLAVE_IMEM_CFG 82
95
+
#define SM7150_SLAVE_IPA_CFG 83
96
+
#define SM7150_SLAVE_LLCC 84
97
+
#define SM7150_SLAVE_LLCC_CFG 85
98
+
#define SM7150_SLAVE_MNOC_HF_MEM_NOC 86
99
+
#define SM7150_SLAVE_MNOC_SF_MEM_NOC 87
100
+
#define SM7150_SLAVE_MSS_PROC_MS_MPU_CFG 88
101
+
#define SM7150_SLAVE_OCIMEM 89
102
+
#define SM7150_SLAVE_PCIE_CFG 90
103
+
#define SM7150_SLAVE_PDM 91
104
+
#define SM7150_SLAVE_PIMEM 92
105
+
#define SM7150_SLAVE_PIMEM_CFG 93
106
+
#define SM7150_SLAVE_PRNG 94
107
+
#define SM7150_SLAVE_QDSS_CFG 95
108
+
#define SM7150_SLAVE_QDSS_STM 96
109
+
#define SM7150_SLAVE_QUP_0 97
110
+
#define SM7150_SLAVE_QUP_1 98
111
+
#define SM7150_SLAVE_RBCPR_CX_CFG 99
112
+
#define SM7150_SLAVE_RBCPR_MX_CFG 100
113
+
#define SM7150_SLAVE_SDCC_2 101
114
+
#define SM7150_SLAVE_SDCC_4 102
115
+
#define SM7150_SLAVE_SERVICE_A1NOC 103
116
+
#define SM7150_SLAVE_SERVICE_A2NOC 104
117
+
#define SM7150_SLAVE_SERVICE_CNOC 105
118
+
#define SM7150_SLAVE_SERVICE_GEM_NOC 106
119
+
#define SM7150_SLAVE_SERVICE_MNOC 107
120
+
#define SM7150_SLAVE_SERVICE_SNOC 108
121
+
#define SM7150_SLAVE_SNOC_CFG 109
122
+
#define SM7150_SLAVE_SNOC_GEM_NOC_GC 110
123
+
#define SM7150_SLAVE_SNOC_GEM_NOC_SF 111
124
+
#define SM7150_SLAVE_SPDM_WRAPPER 112
125
+
#define SM7150_SLAVE_TCSR 113
126
+
#define SM7150_SLAVE_TCU 114
127
+
#define SM7150_SLAVE_TLMM_NORTH 115
128
+
#define SM7150_SLAVE_TLMM_SOUTH 116
129
+
#define SM7150_SLAVE_TLMM_WEST 117
130
+
#define SM7150_SLAVE_TSIF 118
131
+
#define SM7150_SLAVE_UFS_MEM_CFG 119
132
+
#define SM7150_SLAVE_USB3 120
133
+
#define SM7150_SLAVE_VENUS_CFG 121
134
+
#define SM7150_SLAVE_VENUS_CVP_THROTTLE_CFG 122
135
+
#define SM7150_SLAVE_VENUS_THROTTLE_CFG 123
136
+
#define SM7150_SLAVE_VSENSE_CTRL_CFG 124
137
+
#define SM7150_SNOC_CNOC_MAS 125
138
+
#define SM7150_SNOC_CNOC_SLV 126
139
+
140
+
#endif
+1
-1
drivers/interconnect/qcom/sm8250.c
+1
-1
drivers/interconnect/qcom/sm8250.c
···
1673
1673
&bcm_qup0,
1674
1674
};
1675
1675
1676
-
static struct qcom_icc_node *qup_virt_nodes[] = {
1676
+
static struct qcom_icc_node * const qup_virt_nodes[] = {
1677
1677
[MASTER_QUP_CORE_0] = &qup0_core_master,
1678
1678
[MASTER_QUP_CORE_1] = &qup1_core_master,
1679
1679
[MASTER_QUP_CORE_2] = &qup2_core_master,
-574
drivers/interconnect/qcom/sm8550.c
-574
drivers/interconnect/qcom/sm8550.c
···
524
524
.links = { SM8550_SLAVE_SNOC_GEM_NOC_GC },
525
525
};
526
526
527
-
static struct qcom_icc_node qnm_mnoc_hf_disp = {
528
-
.name = "qnm_mnoc_hf_disp",
529
-
.id = SM8550_MASTER_MNOC_HF_MEM_NOC_DISP,
530
-
.channels = 2,
531
-
.buswidth = 32,
532
-
.num_links = 1,
533
-
.links = { SM8550_SLAVE_LLCC_DISP },
534
-
};
535
-
536
-
static struct qcom_icc_node qnm_pcie_disp = {
537
-
.name = "qnm_pcie_disp",
538
-
.id = SM8550_MASTER_ANOC_PCIE_GEM_NOC_DISP,
539
-
.channels = 1,
540
-
.buswidth = 16,
541
-
.num_links = 1,
542
-
.links = { SM8550_SLAVE_LLCC_DISP },
543
-
};
544
-
545
-
static struct qcom_icc_node llcc_mc_disp = {
546
-
.name = "llcc_mc_disp",
547
-
.id = SM8550_MASTER_LLCC_DISP,
548
-
.channels = 4,
549
-
.buswidth = 4,
550
-
.num_links = 1,
551
-
.links = { SM8550_SLAVE_EBI1_DISP },
552
-
};
553
-
554
-
static struct qcom_icc_node qnm_mdp_disp = {
555
-
.name = "qnm_mdp_disp",
556
-
.id = SM8550_MASTER_MDP_DISP,
557
-
.channels = 2,
558
-
.buswidth = 32,
559
-
.num_links = 1,
560
-
.links = { SM8550_SLAVE_MNOC_HF_MEM_NOC_DISP },
561
-
};
562
-
563
-
static struct qcom_icc_node qnm_mnoc_hf_cam_ife_0 = {
564
-
.name = "qnm_mnoc_hf_cam_ife_0",
565
-
.id = SM8550_MASTER_MNOC_HF_MEM_NOC_CAM_IFE_0,
566
-
.channels = 2,
567
-
.buswidth = 32,
568
-
.num_links = 1,
569
-
.links = { SM8550_SLAVE_LLCC_CAM_IFE_0 },
570
-
};
571
-
572
-
static struct qcom_icc_node qnm_mnoc_sf_cam_ife_0 = {
573
-
.name = "qnm_mnoc_sf_cam_ife_0",
574
-
.id = SM8550_MASTER_MNOC_SF_MEM_NOC_CAM_IFE_0,
575
-
.channels = 2,
576
-
.buswidth = 32,
577
-
.num_links = 1,
578
-
.links = { SM8550_SLAVE_LLCC_CAM_IFE_0 },
579
-
};
580
-
581
-
static struct qcom_icc_node qnm_pcie_cam_ife_0 = {
582
-
.name = "qnm_pcie_cam_ife_0",
583
-
.id = SM8550_MASTER_ANOC_PCIE_GEM_NOC_CAM_IFE_0,
584
-
.channels = 1,
585
-
.buswidth = 16,
586
-
.num_links = 1,
587
-
.links = { SM8550_SLAVE_LLCC_CAM_IFE_0 },
588
-
};
589
-
590
-
static struct qcom_icc_node llcc_mc_cam_ife_0 = {
591
-
.name = "llcc_mc_cam_ife_0",
592
-
.id = SM8550_MASTER_LLCC_CAM_IFE_0,
593
-
.channels = 4,
594
-
.buswidth = 4,
595
-
.num_links = 1,
596
-
.links = { SM8550_SLAVE_EBI1_CAM_IFE_0 },
597
-
};
598
-
599
-
static struct qcom_icc_node qnm_camnoc_hf_cam_ife_0 = {
600
-
.name = "qnm_camnoc_hf_cam_ife_0",
601
-
.id = SM8550_MASTER_CAMNOC_HF_CAM_IFE_0,
602
-
.channels = 2,
603
-
.buswidth = 32,
604
-
.num_links = 1,
605
-
.links = { SM8550_SLAVE_MNOC_HF_MEM_NOC_CAM_IFE_0 },
606
-
};
607
-
608
-
static struct qcom_icc_node qnm_camnoc_icp_cam_ife_0 = {
609
-
.name = "qnm_camnoc_icp_cam_ife_0",
610
-
.id = SM8550_MASTER_CAMNOC_ICP_CAM_IFE_0,
611
-
.channels = 1,
612
-
.buswidth = 8,
613
-
.num_links = 1,
614
-
.links = { SM8550_SLAVE_MNOC_SF_MEM_NOC_CAM_IFE_0 },
615
-
};
616
-
617
-
static struct qcom_icc_node qnm_camnoc_sf_cam_ife_0 = {
618
-
.name = "qnm_camnoc_sf_cam_ife_0",
619
-
.id = SM8550_MASTER_CAMNOC_SF_CAM_IFE_0,
620
-
.channels = 2,
621
-
.buswidth = 32,
622
-
.num_links = 1,
623
-
.links = { SM8550_SLAVE_MNOC_SF_MEM_NOC_CAM_IFE_0 },
624
-
};
625
-
626
-
static struct qcom_icc_node qnm_mnoc_hf_cam_ife_1 = {
627
-
.name = "qnm_mnoc_hf_cam_ife_1",
628
-
.id = SM8550_MASTER_MNOC_HF_MEM_NOC_CAM_IFE_1,
629
-
.channels = 2,
630
-
.buswidth = 32,
631
-
.num_links = 1,
632
-
.links = { SM8550_SLAVE_LLCC_CAM_IFE_1 },
633
-
};
634
-
635
-
static struct qcom_icc_node qnm_mnoc_sf_cam_ife_1 = {
636
-
.name = "qnm_mnoc_sf_cam_ife_1",
637
-
.id = SM8550_MASTER_MNOC_SF_MEM_NOC_CAM_IFE_1,
638
-
.channels = 2,
639
-
.buswidth = 32,
640
-
.num_links = 1,
641
-
.links = { SM8550_SLAVE_LLCC_CAM_IFE_1 },
642
-
};
643
-
644
-
static struct qcom_icc_node qnm_pcie_cam_ife_1 = {
645
-
.name = "qnm_pcie_cam_ife_1",
646
-
.id = SM8550_MASTER_ANOC_PCIE_GEM_NOC_CAM_IFE_1,
647
-
.channels = 1,
648
-
.buswidth = 16,
649
-
.num_links = 1,
650
-
.links = { SM8550_SLAVE_LLCC_CAM_IFE_1 },
651
-
};
652
-
653
-
static struct qcom_icc_node llcc_mc_cam_ife_1 = {
654
-
.name = "llcc_mc_cam_ife_1",
655
-
.id = SM8550_MASTER_LLCC_CAM_IFE_1,
656
-
.channels = 4,
657
-
.buswidth = 4,
658
-
.num_links = 1,
659
-
.links = { SM8550_SLAVE_EBI1_CAM_IFE_1 },
660
-
};
661
-
662
-
static struct qcom_icc_node qnm_camnoc_hf_cam_ife_1 = {
663
-
.name = "qnm_camnoc_hf_cam_ife_1",
664
-
.id = SM8550_MASTER_CAMNOC_HF_CAM_IFE_1,
665
-
.channels = 2,
666
-
.buswidth = 32,
667
-
.num_links = 1,
668
-
.links = { SM8550_SLAVE_MNOC_HF_MEM_NOC_CAM_IFE_1 },
669
-
};
670
-
671
-
static struct qcom_icc_node qnm_camnoc_icp_cam_ife_1 = {
672
-
.name = "qnm_camnoc_icp_cam_ife_1",
673
-
.id = SM8550_MASTER_CAMNOC_ICP_CAM_IFE_1,
674
-
.channels = 1,
675
-
.buswidth = 8,
676
-
.num_links = 1,
677
-
.links = { SM8550_SLAVE_MNOC_SF_MEM_NOC_CAM_IFE_1 },
678
-
};
679
-
680
-
static struct qcom_icc_node qnm_camnoc_sf_cam_ife_1 = {
681
-
.name = "qnm_camnoc_sf_cam_ife_1",
682
-
.id = SM8550_MASTER_CAMNOC_SF_CAM_IFE_1,
683
-
.channels = 2,
684
-
.buswidth = 32,
685
-
.num_links = 1,
686
-
.links = { SM8550_SLAVE_MNOC_SF_MEM_NOC_CAM_IFE_1 },
687
-
};
688
-
689
-
static struct qcom_icc_node qnm_mnoc_hf_cam_ife_2 = {
690
-
.name = "qnm_mnoc_hf_cam_ife_2",
691
-
.id = SM8550_MASTER_MNOC_HF_MEM_NOC_CAM_IFE_2,
692
-
.channels = 2,
693
-
.buswidth = 32,
694
-
.num_links = 1,
695
-
.links = { SM8550_SLAVE_LLCC_CAM_IFE_2 },
696
-
};
697
-
698
-
static struct qcom_icc_node qnm_mnoc_sf_cam_ife_2 = {
699
-
.name = "qnm_mnoc_sf_cam_ife_2",
700
-
.id = SM8550_MASTER_MNOC_SF_MEM_NOC_CAM_IFE_2,
701
-
.channels = 2,
702
-
.buswidth = 32,
703
-
.num_links = 1,
704
-
.links = { SM8550_SLAVE_LLCC_CAM_IFE_2 },
705
-
};
706
-
707
-
static struct qcom_icc_node qnm_pcie_cam_ife_2 = {
708
-
.name = "qnm_pcie_cam_ife_2",
709
-
.id = SM8550_MASTER_ANOC_PCIE_GEM_NOC_CAM_IFE_2,
710
-
.channels = 1,
711
-
.buswidth = 16,
712
-
.num_links = 1,
713
-
.links = { SM8550_SLAVE_LLCC_CAM_IFE_2 },
714
-
};
715
-
716
-
static struct qcom_icc_node llcc_mc_cam_ife_2 = {
717
-
.name = "llcc_mc_cam_ife_2",
718
-
.id = SM8550_MASTER_LLCC_CAM_IFE_2,
719
-
.channels = 4,
720
-
.buswidth = 4,
721
-
.num_links = 1,
722
-
.links = { SM8550_SLAVE_EBI1_CAM_IFE_2 },
723
-
};
724
-
725
-
static struct qcom_icc_node qnm_camnoc_hf_cam_ife_2 = {
726
-
.name = "qnm_camnoc_hf_cam_ife_2",
727
-
.id = SM8550_MASTER_CAMNOC_HF_CAM_IFE_2,
728
-
.channels = 2,
729
-
.buswidth = 32,
730
-
.num_links = 1,
731
-
.links = { SM8550_SLAVE_MNOC_HF_MEM_NOC_CAM_IFE_2 },
732
-
};
733
-
734
-
static struct qcom_icc_node qnm_camnoc_icp_cam_ife_2 = {
735
-
.name = "qnm_camnoc_icp_cam_ife_2",
736
-
.id = SM8550_MASTER_CAMNOC_ICP_CAM_IFE_2,
737
-
.channels = 1,
738
-
.buswidth = 8,
739
-
.num_links = 1,
740
-
.links = { SM8550_SLAVE_MNOC_SF_MEM_NOC_CAM_IFE_2 },
741
-
};
742
-
743
-
static struct qcom_icc_node qnm_camnoc_sf_cam_ife_2 = {
744
-
.name = "qnm_camnoc_sf_cam_ife_2",
745
-
.id = SM8550_MASTER_CAMNOC_SF_CAM_IFE_2,
746
-
.channels = 2,
747
-
.buswidth = 32,
748
-
.num_links = 1,
749
-
.links = { SM8550_SLAVE_MNOC_SF_MEM_NOC_CAM_IFE_2 },
750
-
};
751
-
752
527
static struct qcom_icc_node qns_a1noc_snoc = {
753
528
.name = "qns_a1noc_snoc",
754
529
.id = SM8550_SLAVE_A1NOC_SNOC,
···
1117
1342
.links = { SM8550_MASTER_SNOC_SF_MEM_NOC },
1118
1343
};
1119
1344
1120
-
static struct qcom_icc_node qns_llcc_disp = {
1121
-
.name = "qns_llcc_disp",
1122
-
.id = SM8550_SLAVE_LLCC_DISP,
1123
-
.channels = 4,
1124
-
.buswidth = 16,
1125
-
.num_links = 1,
1126
-
.links = { SM8550_MASTER_LLCC_DISP },
1127
-
};
1128
-
1129
-
static struct qcom_icc_node ebi_disp = {
1130
-
.name = "ebi_disp",
1131
-
.id = SM8550_SLAVE_EBI1_DISP,
1132
-
.channels = 4,
1133
-
.buswidth = 4,
1134
-
.num_links = 0,
1135
-
};
1136
-
1137
-
static struct qcom_icc_node qns_mem_noc_hf_disp = {
1138
-
.name = "qns_mem_noc_hf_disp",
1139
-
.id = SM8550_SLAVE_MNOC_HF_MEM_NOC_DISP,
1140
-
.channels = 2,
1141
-
.buswidth = 32,
1142
-
.num_links = 1,
1143
-
.links = { SM8550_MASTER_MNOC_HF_MEM_NOC_DISP },
1144
-
};
1145
-
1146
-
static struct qcom_icc_node qns_llcc_cam_ife_0 = {
1147
-
.name = "qns_llcc_cam_ife_0",
1148
-
.id = SM8550_SLAVE_LLCC_CAM_IFE_0,
1149
-
.channels = 4,
1150
-
.buswidth = 16,
1151
-
.num_links = 1,
1152
-
.links = { SM8550_MASTER_LLCC_CAM_IFE_0 },
1153
-
};
1154
-
1155
-
static struct qcom_icc_node ebi_cam_ife_0 = {
1156
-
.name = "ebi_cam_ife_0",
1157
-
.id = SM8550_SLAVE_EBI1_CAM_IFE_0,
1158
-
.channels = 4,
1159
-
.buswidth = 4,
1160
-
.num_links = 0,
1161
-
};
1162
-
1163
-
static struct qcom_icc_node qns_mem_noc_hf_cam_ife_0 = {
1164
-
.name = "qns_mem_noc_hf_cam_ife_0",
1165
-
.id = SM8550_SLAVE_MNOC_HF_MEM_NOC_CAM_IFE_0,
1166
-
.channels = 2,
1167
-
.buswidth = 32,
1168
-
.num_links = 1,
1169
-
.links = { SM8550_MASTER_MNOC_HF_MEM_NOC_CAM_IFE_0 },
1170
-
};
1171
-
1172
-
static struct qcom_icc_node qns_mem_noc_sf_cam_ife_0 = {
1173
-
.name = "qns_mem_noc_sf_cam_ife_0",
1174
-
.id = SM8550_SLAVE_MNOC_SF_MEM_NOC_CAM_IFE_0,
1175
-
.channels = 2,
1176
-
.buswidth = 32,
1177
-
.num_links = 1,
1178
-
.links = { SM8550_MASTER_MNOC_SF_MEM_NOC_CAM_IFE_0 },
1179
-
};
1180
-
1181
-
static struct qcom_icc_node qns_llcc_cam_ife_1 = {
1182
-
.name = "qns_llcc_cam_ife_1",
1183
-
.id = SM8550_SLAVE_LLCC_CAM_IFE_1,
1184
-
.channels = 4,
1185
-
.buswidth = 16,
1186
-
.num_links = 1,
1187
-
.links = { SM8550_MASTER_LLCC_CAM_IFE_1 },
1188
-
};
1189
-
1190
-
static struct qcom_icc_node ebi_cam_ife_1 = {
1191
-
.name = "ebi_cam_ife_1",
1192
-
.id = SM8550_SLAVE_EBI1_CAM_IFE_1,
1193
-
.channels = 4,
1194
-
.buswidth = 4,
1195
-
.num_links = 0,
1196
-
};
1197
-
1198
-
static struct qcom_icc_node qns_mem_noc_hf_cam_ife_1 = {
1199
-
.name = "qns_mem_noc_hf_cam_ife_1",
1200
-
.id = SM8550_SLAVE_MNOC_HF_MEM_NOC_CAM_IFE_1,
1201
-
.channels = 2,
1202
-
.buswidth = 32,
1203
-
.num_links = 1,
1204
-
.links = { SM8550_MASTER_MNOC_HF_MEM_NOC_CAM_IFE_1 },
1205
-
};
1206
-
1207
-
static struct qcom_icc_node qns_mem_noc_sf_cam_ife_1 = {
1208
-
.name = "qns_mem_noc_sf_cam_ife_1",
1209
-
.id = SM8550_SLAVE_MNOC_SF_MEM_NOC_CAM_IFE_1,
1210
-
.channels = 2,
1211
-
.buswidth = 32,
1212
-
.num_links = 1,
1213
-
.links = { SM8550_MASTER_MNOC_SF_MEM_NOC_CAM_IFE_1 },
1214
-
};
1215
-
1216
-
static struct qcom_icc_node qns_llcc_cam_ife_2 = {
1217
-
.name = "qns_llcc_cam_ife_2",
1218
-
.id = SM8550_SLAVE_LLCC_CAM_IFE_2,
1219
-
.channels = 4,
1220
-
.buswidth = 16,
1221
-
.num_links = 1,
1222
-
.links = { SM8550_MASTER_LLCC_CAM_IFE_2 },
1223
-
};
1224
-
1225
-
static struct qcom_icc_node ebi_cam_ife_2 = {
1226
-
.name = "ebi_cam_ife_2",
1227
-
.id = SM8550_SLAVE_EBI1_CAM_IFE_2,
1228
-
.channels = 4,
1229
-
.buswidth = 4,
1230
-
.num_links = 0,
1231
-
};
1232
-
1233
-
static struct qcom_icc_node qns_mem_noc_hf_cam_ife_2 = {
1234
-
.name = "qns_mem_noc_hf_cam_ife_2",
1235
-
.id = SM8550_SLAVE_MNOC_HF_MEM_NOC_CAM_IFE_2,
1236
-
.channels = 2,
1237
-
.buswidth = 32,
1238
-
.num_links = 1,
1239
-
.links = { SM8550_MASTER_MNOC_HF_MEM_NOC_CAM_IFE_2 },
1240
-
};
1241
-
1242
-
static struct qcom_icc_node qns_mem_noc_sf_cam_ife_2 = {
1243
-
.name = "qns_mem_noc_sf_cam_ife_2",
1244
-
.id = SM8550_SLAVE_MNOC_SF_MEM_NOC_CAM_IFE_2,
1245
-
.channels = 2,
1246
-
.buswidth = 32,
1247
-
.num_links = 1,
1248
-
.links = { SM8550_MASTER_MNOC_SF_MEM_NOC_CAM_IFE_2 },
1249
-
};
1250
-
1251
1345
static struct qcom_icc_bcm bcm_acv = {
1252
1346
.name = "ACV",
1253
1347
.enable_mask = 0x8,
···
1283
1639
.nodes = { &qns_pcie_mem_noc },
1284
1640
};
1285
1641
1286
-
static struct qcom_icc_bcm bcm_acv_disp = {
1287
-
.name = "ACV",
1288
-
.enable_mask = 0x1,
1289
-
.num_nodes = 1,
1290
-
.nodes = { &ebi_disp },
1291
-
};
1292
-
1293
-
static struct qcom_icc_bcm bcm_mc0_disp = {
1294
-
.name = "MC0",
1295
-
.num_nodes = 1,
1296
-
.nodes = { &ebi_disp },
1297
-
};
1298
-
1299
-
static struct qcom_icc_bcm bcm_mm0_disp = {
1300
-
.name = "MM0",
1301
-
.num_nodes = 1,
1302
-
.nodes = { &qns_mem_noc_hf_disp },
1303
-
};
1304
-
1305
-
static struct qcom_icc_bcm bcm_sh0_disp = {
1306
-
.name = "SH0",
1307
-
.num_nodes = 1,
1308
-
.nodes = { &qns_llcc_disp },
1309
-
};
1310
-
1311
-
static struct qcom_icc_bcm bcm_sh1_disp = {
1312
-
.name = "SH1",
1313
-
.enable_mask = 0x1,
1314
-
.num_nodes = 2,
1315
-
.nodes = { &qnm_mnoc_hf_disp, &qnm_pcie_disp },
1316
-
};
1317
-
1318
-
static struct qcom_icc_bcm bcm_acv_cam_ife_0 = {
1319
-
.name = "ACV",
1320
-
.enable_mask = 0x0,
1321
-
.num_nodes = 1,
1322
-
.nodes = { &ebi_cam_ife_0 },
1323
-
};
1324
-
1325
-
static struct qcom_icc_bcm bcm_mc0_cam_ife_0 = {
1326
-
.name = "MC0",
1327
-
.num_nodes = 1,
1328
-
.nodes = { &ebi_cam_ife_0 },
1329
-
};
1330
-
1331
-
static struct qcom_icc_bcm bcm_mm0_cam_ife_0 = {
1332
-
.name = "MM0",
1333
-
.num_nodes = 1,
1334
-
.nodes = { &qns_mem_noc_hf_cam_ife_0 },
1335
-
};
1336
-
1337
-
static struct qcom_icc_bcm bcm_mm1_cam_ife_0 = {
1338
-
.name = "MM1",
1339
-
.enable_mask = 0x1,
1340
-
.num_nodes = 4,
1341
-
.nodes = { &qnm_camnoc_hf_cam_ife_0, &qnm_camnoc_icp_cam_ife_0,
1342
-
&qnm_camnoc_sf_cam_ife_0, &qns_mem_noc_sf_cam_ife_0 },
1343
-
};
1344
-
1345
-
static struct qcom_icc_bcm bcm_sh0_cam_ife_0 = {
1346
-
.name = "SH0",
1347
-
.num_nodes = 1,
1348
-
.nodes = { &qns_llcc_cam_ife_0 },
1349
-
};
1350
-
1351
-
static struct qcom_icc_bcm bcm_sh1_cam_ife_0 = {
1352
-
.name = "SH1",
1353
-
.enable_mask = 0x1,
1354
-
.num_nodes = 3,
1355
-
.nodes = { &qnm_mnoc_hf_cam_ife_0, &qnm_mnoc_sf_cam_ife_0,
1356
-
&qnm_pcie_cam_ife_0 },
1357
-
};
1358
-
1359
-
static struct qcom_icc_bcm bcm_acv_cam_ife_1 = {
1360
-
.name = "ACV",
1361
-
.enable_mask = 0x0,
1362
-
.num_nodes = 1,
1363
-
.nodes = { &ebi_cam_ife_1 },
1364
-
};
1365
-
1366
-
static struct qcom_icc_bcm bcm_mc0_cam_ife_1 = {
1367
-
.name = "MC0",
1368
-
.num_nodes = 1,
1369
-
.nodes = { &ebi_cam_ife_1 },
1370
-
};
1371
-
1372
-
static struct qcom_icc_bcm bcm_mm0_cam_ife_1 = {
1373
-
.name = "MM0",
1374
-
.num_nodes = 1,
1375
-
.nodes = { &qns_mem_noc_hf_cam_ife_1 },
1376
-
};
1377
-
1378
-
static struct qcom_icc_bcm bcm_mm1_cam_ife_1 = {
1379
-
.name = "MM1",
1380
-
.enable_mask = 0x1,
1381
-
.num_nodes = 4,
1382
-
.nodes = { &qnm_camnoc_hf_cam_ife_1, &qnm_camnoc_icp_cam_ife_1,
1383
-
&qnm_camnoc_sf_cam_ife_1, &qns_mem_noc_sf_cam_ife_1 },
1384
-
};
1385
-
1386
-
static struct qcom_icc_bcm bcm_sh0_cam_ife_1 = {
1387
-
.name = "SH0",
1388
-
.num_nodes = 1,
1389
-
.nodes = { &qns_llcc_cam_ife_1 },
1390
-
};
1391
-
1392
-
static struct qcom_icc_bcm bcm_sh1_cam_ife_1 = {
1393
-
.name = "SH1",
1394
-
.enable_mask = 0x1,
1395
-
.num_nodes = 3,
1396
-
.nodes = { &qnm_mnoc_hf_cam_ife_1, &qnm_mnoc_sf_cam_ife_1,
1397
-
&qnm_pcie_cam_ife_1 },
1398
-
};
1399
-
1400
-
static struct qcom_icc_bcm bcm_acv_cam_ife_2 = {
1401
-
.name = "ACV",
1402
-
.enable_mask = 0x0,
1403
-
.num_nodes = 1,
1404
-
.nodes = { &ebi_cam_ife_2 },
1405
-
};
1406
-
1407
-
static struct qcom_icc_bcm bcm_mc0_cam_ife_2 = {
1408
-
.name = "MC0",
1409
-
.num_nodes = 1,
1410
-
.nodes = { &ebi_cam_ife_2 },
1411
-
};
1412
-
1413
-
static struct qcom_icc_bcm bcm_mm0_cam_ife_2 = {
1414
-
.name = "MM0",
1415
-
.num_nodes = 1,
1416
-
.nodes = { &qns_mem_noc_hf_cam_ife_2 },
1417
-
};
1418
-
1419
-
static struct qcom_icc_bcm bcm_mm1_cam_ife_2 = {
1420
-
.name = "MM1",
1421
-
.enable_mask = 0x1,
1422
-
.num_nodes = 4,
1423
-
.nodes = { &qnm_camnoc_hf_cam_ife_2, &qnm_camnoc_icp_cam_ife_2,
1424
-
&qnm_camnoc_sf_cam_ife_2, &qns_mem_noc_sf_cam_ife_2 },
1425
-
};
1426
-
1427
-
static struct qcom_icc_bcm bcm_sh0_cam_ife_2 = {
1428
-
.name = "SH0",
1429
-
.num_nodes = 1,
1430
-
.nodes = { &qns_llcc_cam_ife_2 },
1431
-
};
1432
-
1433
-
static struct qcom_icc_bcm bcm_sh1_cam_ife_2 = {
1434
-
.name = "SH1",
1435
-
.enable_mask = 0x1,
1436
-
.num_nodes = 3,
1437
-
.nodes = { &qnm_mnoc_hf_cam_ife_2, &qnm_mnoc_sf_cam_ife_2,
1438
-
&qnm_pcie_cam_ife_2 },
1439
-
};
1440
-
1441
1642
static struct qcom_icc_bcm * const aggre1_noc_bcms[] = {
1442
1643
};
1443
1644
···
1434
1945
static struct qcom_icc_bcm * const gem_noc_bcms[] = {
1435
1946
&bcm_sh0,
1436
1947
&bcm_sh1,
1437
-
&bcm_sh0_disp,
1438
-
&bcm_sh1_disp,
1439
-
&bcm_sh0_cam_ife_0,
1440
-
&bcm_sh1_cam_ife_0,
1441
-
&bcm_sh0_cam_ife_1,
1442
-
&bcm_sh1_cam_ife_1,
1443
-
&bcm_sh0_cam_ife_2,
1444
-
&bcm_sh1_cam_ife_2,
1445
1948
};
1446
1949
1447
1950
static struct qcom_icc_node * const gem_noc_nodes[] = {
···
1452
1971
[SLAVE_GEM_NOC_CNOC] = &qns_gem_noc_cnoc,
1453
1972
[SLAVE_LLCC] = &qns_llcc,
1454
1973
[SLAVE_MEM_NOC_PCIE_SNOC] = &qns_pcie,
1455
-
[MASTER_MNOC_HF_MEM_NOC_DISP] = &qnm_mnoc_hf_disp,
1456
-
[MASTER_ANOC_PCIE_GEM_NOC_DISP] = &qnm_pcie_disp,
1457
-
[SLAVE_LLCC_DISP] = &qns_llcc_disp,
1458
-
[MASTER_MNOC_HF_MEM_NOC_CAM_IFE_0] = &qnm_mnoc_hf_cam_ife_0,
1459
-
[MASTER_MNOC_SF_MEM_NOC_CAM_IFE_0] = &qnm_mnoc_sf_cam_ife_0,
1460
-
[MASTER_ANOC_PCIE_GEM_NOC_CAM_IFE_0] = &qnm_pcie_cam_ife_0,
1461
-
[SLAVE_LLCC_CAM_IFE_0] = &qns_llcc_cam_ife_0,
1462
-
[MASTER_MNOC_HF_MEM_NOC_CAM_IFE_1] = &qnm_mnoc_hf_cam_ife_1,
1463
-
[MASTER_MNOC_SF_MEM_NOC_CAM_IFE_1] = &qnm_mnoc_sf_cam_ife_1,
1464
-
[MASTER_ANOC_PCIE_GEM_NOC_CAM_IFE_1] = &qnm_pcie_cam_ife_1,
1465
-
[SLAVE_LLCC_CAM_IFE_1] = &qns_llcc_cam_ife_1,
1466
-
[MASTER_MNOC_HF_MEM_NOC_CAM_IFE_2] = &qnm_mnoc_hf_cam_ife_2,
1467
-
[MASTER_MNOC_SF_MEM_NOC_CAM_IFE_2] = &qnm_mnoc_sf_cam_ife_2,
1468
-
[MASTER_ANOC_PCIE_GEM_NOC_CAM_IFE_2] = &qnm_pcie_cam_ife_2,
1469
-
[SLAVE_LLCC_CAM_IFE_2] = &qns_llcc_cam_ife_2,
1470
1974
};
1471
1975
1472
1976
static const struct qcom_icc_desc sm8550_gem_noc = {
···
1510
2044
static struct qcom_icc_bcm * const mc_virt_bcms[] = {
1511
2045
&bcm_acv,
1512
2046
&bcm_mc0,
1513
-
&bcm_acv_disp,
1514
-
&bcm_mc0_disp,
1515
-
&bcm_acv_cam_ife_0,
1516
-
&bcm_mc0_cam_ife_0,
1517
-
&bcm_acv_cam_ife_1,
1518
-
&bcm_mc0_cam_ife_1,
1519
-
&bcm_acv_cam_ife_2,
1520
-
&bcm_mc0_cam_ife_2,
1521
2047
};
1522
2048
1523
2049
static struct qcom_icc_node * const mc_virt_nodes[] = {
1524
2050
[MASTER_LLCC] = &llcc_mc,
1525
2051
[SLAVE_EBI1] = &ebi,
1526
-
[MASTER_LLCC_DISP] = &llcc_mc_disp,
1527
-
[SLAVE_EBI1_DISP] = &ebi_disp,
1528
-
[MASTER_LLCC_CAM_IFE_0] = &llcc_mc_cam_ife_0,
1529
-
[SLAVE_EBI1_CAM_IFE_0] = &ebi_cam_ife_0,
1530
-
[MASTER_LLCC_CAM_IFE_1] = &llcc_mc_cam_ife_1,
1531
-
[SLAVE_EBI1_CAM_IFE_1] = &ebi_cam_ife_1,
1532
-
[MASTER_LLCC_CAM_IFE_2] = &llcc_mc_cam_ife_2,
1533
-
[SLAVE_EBI1_CAM_IFE_2] = &ebi_cam_ife_2,
1534
2052
};
1535
2053
1536
2054
static const struct qcom_icc_desc sm8550_mc_virt = {
···
1527
2077
static struct qcom_icc_bcm * const mmss_noc_bcms[] = {
1528
2078
&bcm_mm0,
1529
2079
&bcm_mm1,
1530
-
&bcm_mm0_disp,
1531
-
&bcm_mm0_cam_ife_0,
1532
-
&bcm_mm1_cam_ife_0,
1533
-
&bcm_mm0_cam_ife_1,
1534
-
&bcm_mm1_cam_ife_1,
1535
-
&bcm_mm0_cam_ife_2,
1536
-
&bcm_mm1_cam_ife_2,
1537
2080
};
1538
2081
1539
2082
static struct qcom_icc_node * const mmss_noc_nodes[] = {
···
1543
2100
[SLAVE_MNOC_HF_MEM_NOC] = &qns_mem_noc_hf,
1544
2101
[SLAVE_MNOC_SF_MEM_NOC] = &qns_mem_noc_sf,
1545
2102
[SLAVE_SERVICE_MNOC] = &srvc_mnoc,
1546
-
[MASTER_MDP_DISP] = &qnm_mdp_disp,
1547
-
[SLAVE_MNOC_HF_MEM_NOC_DISP] = &qns_mem_noc_hf_disp,
1548
-
[MASTER_CAMNOC_HF_CAM_IFE_0] = &qnm_camnoc_hf_cam_ife_0,
1549
-
[MASTER_CAMNOC_ICP_CAM_IFE_0] = &qnm_camnoc_icp_cam_ife_0,
1550
-
[MASTER_CAMNOC_SF_CAM_IFE_0] = &qnm_camnoc_sf_cam_ife_0,
1551
-
[SLAVE_MNOC_HF_MEM_NOC_CAM_IFE_0] = &qns_mem_noc_hf_cam_ife_0,
1552
-
[SLAVE_MNOC_SF_MEM_NOC_CAM_IFE_0] = &qns_mem_noc_sf_cam_ife_0,
1553
-
[MASTER_CAMNOC_HF_CAM_IFE_1] = &qnm_camnoc_hf_cam_ife_1,
1554
-
[MASTER_CAMNOC_ICP_CAM_IFE_1] = &qnm_camnoc_icp_cam_ife_1,
1555
-
[MASTER_CAMNOC_SF_CAM_IFE_1] = &qnm_camnoc_sf_cam_ife_1,
1556
-
[SLAVE_MNOC_HF_MEM_NOC_CAM_IFE_1] = &qns_mem_noc_hf_cam_ife_1,
1557
-
[SLAVE_MNOC_SF_MEM_NOC_CAM_IFE_1] = &qns_mem_noc_sf_cam_ife_1,
1558
-
[MASTER_CAMNOC_HF_CAM_IFE_2] = &qnm_camnoc_hf_cam_ife_2,
1559
-
[MASTER_CAMNOC_ICP_CAM_IFE_2] = &qnm_camnoc_icp_cam_ife_2,
1560
-
[MASTER_CAMNOC_SF_CAM_IFE_2] = &qnm_camnoc_sf_cam_ife_2,
1561
-
[SLAVE_MNOC_HF_MEM_NOC_CAM_IFE_2] = &qns_mem_noc_hf_cam_ife_2,
1562
-
[SLAVE_MNOC_SF_MEM_NOC_CAM_IFE_2] = &qns_mem_noc_sf_cam_ife_2,
1563
2103
};
1564
2104
1565
2105
static const struct qcom_icc_desc sm8550_mmss_noc = {
+122
-162
drivers/interconnect/qcom/sm8550.h
+122
-162
drivers/interconnect/qcom/sm8550.h
···
12
12
#define SM8550_MASTER_A1NOC_SNOC 0
13
13
#define SM8550_MASTER_A2NOC_SNOC 1
14
14
#define SM8550_MASTER_ANOC_PCIE_GEM_NOC 2
15
-
#define SM8550_MASTER_ANOC_PCIE_GEM_NOC_CAM_IFE_0 3
16
-
#define SM8550_MASTER_ANOC_PCIE_GEM_NOC_CAM_IFE_1 4
17
-
#define SM8550_MASTER_ANOC_PCIE_GEM_NOC_CAM_IFE_2 5
18
-
#define SM8550_MASTER_ANOC_PCIE_GEM_NOC_DISP 6
19
-
#define SM8550_MASTER_APPSS_PROC 7
20
-
#define SM8550_MASTER_CAMNOC_HF 8
21
-
#define SM8550_MASTER_CAMNOC_HF_CAM_IFE_0 9
22
-
#define SM8550_MASTER_CAMNOC_HF_CAM_IFE_1 10
23
-
#define SM8550_MASTER_CAMNOC_HF_CAM_IFE_2 11
24
-
#define SM8550_MASTER_CAMNOC_ICP 12
25
-
#define SM8550_MASTER_CAMNOC_ICP_CAM_IFE_0 13
26
-
#define SM8550_MASTER_CAMNOC_ICP_CAM_IFE_1 14
27
-
#define SM8550_MASTER_CAMNOC_ICP_CAM_IFE_2 15
28
-
#define SM8550_MASTER_CAMNOC_SF 16
29
-
#define SM8550_MASTER_CAMNOC_SF_CAM_IFE_0 17
30
-
#define SM8550_MASTER_CAMNOC_SF_CAM_IFE_1 18
31
-
#define SM8550_MASTER_CAMNOC_SF_CAM_IFE_2 19
32
-
#define SM8550_MASTER_CDSP_HCP 20
33
-
#define SM8550_MASTER_CDSP_PROC 21
34
-
#define SM8550_MASTER_CNOC_CFG 22
35
-
#define SM8550_MASTER_CNOC_MNOC_CFG 23
36
-
#define SM8550_MASTER_COMPUTE_NOC 24
37
-
#define SM8550_MASTER_CRYPTO 25
38
-
#define SM8550_MASTER_GEM_NOC_CNOC 26
39
-
#define SM8550_MASTER_GEM_NOC_PCIE_SNOC 27
40
-
#define SM8550_MASTER_GFX3D 28
41
-
#define SM8550_MASTER_GIC 29
42
-
#define SM8550_MASTER_GIC_AHB 30
43
-
#define SM8550_MASTER_GPU_TCU 31
44
-
#define SM8550_MASTER_IPA 32
45
-
#define SM8550_MASTER_LLCC 33
46
-
#define SM8550_MASTER_LLCC_CAM_IFE_0 34
47
-
#define SM8550_MASTER_LLCC_CAM_IFE_1 35
48
-
#define SM8550_MASTER_LLCC_CAM_IFE_2 36
49
-
#define SM8550_MASTER_LLCC_DISP 37
50
-
#define SM8550_MASTER_LPASS_GEM_NOC 38
51
-
#define SM8550_MASTER_LPASS_LPINOC 39
52
-
#define SM8550_MASTER_LPASS_PROC 40
53
-
#define SM8550_MASTER_LPIAON_NOC 41
54
-
#define SM8550_MASTER_MDP 42
55
-
#define SM8550_MASTER_MDP_DISP 43
56
-
#define SM8550_MASTER_MNOC_HF_MEM_NOC 44
57
-
#define SM8550_MASTER_MNOC_HF_MEM_NOC_CAM_IFE_0 45
58
-
#define SM8550_MASTER_MNOC_HF_MEM_NOC_CAM_IFE_1 46
59
-
#define SM8550_MASTER_MNOC_HF_MEM_NOC_CAM_IFE_2 47
60
-
#define SM8550_MASTER_MNOC_HF_MEM_NOC_DISP 48
61
-
#define SM8550_MASTER_MNOC_SF_MEM_NOC 49
62
-
#define SM8550_MASTER_MNOC_SF_MEM_NOC_CAM_IFE_0 50
63
-
#define SM8550_MASTER_MNOC_SF_MEM_NOC_CAM_IFE_1 51
64
-
#define SM8550_MASTER_MNOC_SF_MEM_NOC_CAM_IFE_2 52
65
-
#define SM8550_MASTER_MSS_PROC 53
66
-
#define SM8550_MASTER_PCIE_0 54
67
-
#define SM8550_MASTER_PCIE_1 55
68
-
#define SM8550_MASTER_PCIE_ANOC_CFG 56
69
-
#define SM8550_MASTER_QDSS_BAM 57
70
-
#define SM8550_MASTER_QDSS_ETR 58
71
-
#define SM8550_MASTER_QDSS_ETR_1 59
72
-
#define SM8550_MASTER_QSPI_0 60
73
-
#define SM8550_MASTER_QUP_1 61
74
-
#define SM8550_MASTER_QUP_2 62
75
-
#define SM8550_MASTER_QUP_CORE_0 63
76
-
#define SM8550_MASTER_QUP_CORE_1 64
77
-
#define SM8550_MASTER_QUP_CORE_2 65
78
-
#define SM8550_MASTER_SDCC_2 66
79
-
#define SM8550_MASTER_SDCC_4 67
80
-
#define SM8550_MASTER_SNOC_GC_MEM_NOC 68
81
-
#define SM8550_MASTER_SNOC_SF_MEM_NOC 69
82
-
#define SM8550_MASTER_SP 70
83
-
#define SM8550_MASTER_SYS_TCU 71
84
-
#define SM8550_MASTER_UFS_MEM 72
85
-
#define SM8550_MASTER_USB3_0 73
86
-
#define SM8550_MASTER_VIDEO 74
87
-
#define SM8550_MASTER_VIDEO_CV_PROC 75
88
-
#define SM8550_MASTER_VIDEO_PROC 76
89
-
#define SM8550_MASTER_VIDEO_V_PROC 77
90
-
#define SM8550_SLAVE_A1NOC_SNOC 78
91
-
#define SM8550_SLAVE_A2NOC_SNOC 79
92
-
#define SM8550_SLAVE_AHB2PHY_NORTH 80
93
-
#define SM8550_SLAVE_AHB2PHY_SOUTH 81
94
-
#define SM8550_SLAVE_ANOC_PCIE_GEM_NOC 82
95
-
#define SM8550_SLAVE_AOSS 83
96
-
#define SM8550_SLAVE_APPSS 84
97
-
#define SM8550_SLAVE_BOOT_IMEM 85
98
-
#define SM8550_SLAVE_CAMERA_CFG 86
99
-
#define SM8550_SLAVE_CDSP_MEM_NOC 87
100
-
#define SM8550_SLAVE_CLK_CTL 88
101
-
#define SM8550_SLAVE_CNOC_CFG 89
102
-
#define SM8550_SLAVE_CNOC_MNOC_CFG 90
103
-
#define SM8550_SLAVE_CNOC_MSS 91
104
-
#define SM8550_SLAVE_CPR_NSPCX 92
105
-
#define SM8550_SLAVE_CRYPTO_0_CFG 93
106
-
#define SM8550_SLAVE_CX_RDPM 94
107
-
#define SM8550_SLAVE_DDRSS_CFG 95
108
-
#define SM8550_SLAVE_DISPLAY_CFG 96
109
-
#define SM8550_SLAVE_EBI1 97
110
-
#define SM8550_SLAVE_EBI1_CAM_IFE_0 98
111
-
#define SM8550_SLAVE_EBI1_CAM_IFE_1 99
112
-
#define SM8550_SLAVE_EBI1_CAM_IFE_2 100
113
-
#define SM8550_SLAVE_EBI1_DISP 101
114
-
#define SM8550_SLAVE_GEM_NOC_CNOC 102
115
-
#define SM8550_SLAVE_GFX3D_CFG 103
116
-
#define SM8550_SLAVE_I2C 104
117
-
#define SM8550_SLAVE_IMEM 105
118
-
#define SM8550_SLAVE_IMEM_CFG 106
119
-
#define SM8550_SLAVE_IPA_CFG 107
120
-
#define SM8550_SLAVE_IPC_ROUTER_CFG 108
121
-
#define SM8550_SLAVE_LLCC 109
122
-
#define SM8550_SLAVE_LLCC_CAM_IFE_0 110
123
-
#define SM8550_SLAVE_LLCC_CAM_IFE_1 111
124
-
#define SM8550_SLAVE_LLCC_CAM_IFE_2 112
125
-
#define SM8550_SLAVE_LLCC_DISP 113
126
-
#define SM8550_SLAVE_LPASS_GEM_NOC 114
127
-
#define SM8550_SLAVE_LPASS_QTB_CFG 115
128
-
#define SM8550_SLAVE_LPIAON_NOC_LPASS_AG_NOC 116
129
-
#define SM8550_SLAVE_LPICX_NOC_LPIAON_NOC 117
130
-
#define SM8550_SLAVE_MEM_NOC_PCIE_SNOC 118
131
-
#define SM8550_SLAVE_MNOC_HF_MEM_NOC 119
132
-
#define SM8550_SLAVE_MNOC_HF_MEM_NOC_CAM_IFE_0 120
133
-
#define SM8550_SLAVE_MNOC_HF_MEM_NOC_CAM_IFE_1 121
134
-
#define SM8550_SLAVE_MNOC_HF_MEM_NOC_CAM_IFE_2 122
135
-
#define SM8550_SLAVE_MNOC_HF_MEM_NOC_DISP 123
136
-
#define SM8550_SLAVE_MNOC_SF_MEM_NOC 124
137
-
#define SM8550_SLAVE_MNOC_SF_MEM_NOC_CAM_IFE_0 125
138
-
#define SM8550_SLAVE_MNOC_SF_MEM_NOC_CAM_IFE_1 126
139
-
#define SM8550_SLAVE_MNOC_SF_MEM_NOC_CAM_IFE_2 127
140
-
#define SM8550_SLAVE_MX_RDPM 128
141
-
#define SM8550_SLAVE_NSP_QTB_CFG 129
142
-
#define SM8550_SLAVE_PCIE_0 130
143
-
#define SM8550_SLAVE_PCIE_0_CFG 131
144
-
#define SM8550_SLAVE_PCIE_1 132
145
-
#define SM8550_SLAVE_PCIE_1_CFG 133
146
-
#define SM8550_SLAVE_PCIE_ANOC_CFG 134
147
-
#define SM8550_SLAVE_PDM 135
148
-
#define SM8550_SLAVE_PIMEM_CFG 136
149
-
#define SM8550_SLAVE_PRNG 137
150
-
#define SM8550_SLAVE_QDSS_CFG 138
151
-
#define SM8550_SLAVE_QDSS_STM 139
152
-
#define SM8550_SLAVE_QSPI_0 140
153
-
#define SM8550_SLAVE_QUP_1 141
154
-
#define SM8550_SLAVE_QUP_2 142
155
-
#define SM8550_SLAVE_QUP_CORE_0 143
156
-
#define SM8550_SLAVE_QUP_CORE_1 144
157
-
#define SM8550_SLAVE_QUP_CORE_2 145
158
-
#define SM8550_SLAVE_RBCPR_CX_CFG 146
159
-
#define SM8550_SLAVE_RBCPR_MMCX_CFG 147
160
-
#define SM8550_SLAVE_RBCPR_MXA_CFG 148
161
-
#define SM8550_SLAVE_RBCPR_MXC_CFG 149
162
-
#define SM8550_SLAVE_SDCC_2 150
163
-
#define SM8550_SLAVE_SDCC_4 151
164
-
#define SM8550_SLAVE_SERVICE_MNOC 152
165
-
#define SM8550_SLAVE_SERVICE_PCIE_ANOC 153
166
-
#define SM8550_SLAVE_SNOC_GEM_NOC_GC 154
167
-
#define SM8550_SLAVE_SNOC_GEM_NOC_SF 155
168
-
#define SM8550_SLAVE_SPSS_CFG 156
169
-
#define SM8550_SLAVE_TCSR 157
170
-
#define SM8550_SLAVE_TCU 158
171
-
#define SM8550_SLAVE_TLMM 159
172
-
#define SM8550_SLAVE_TME_CFG 160
173
-
#define SM8550_SLAVE_UFS_MEM_CFG 161
174
-
#define SM8550_SLAVE_USB3_0 162
175
-
#define SM8550_SLAVE_VENUS_CFG 163
176
-
#define SM8550_SLAVE_VSENSE_CTRL_CFG 164
15
+
#define SM8550_MASTER_APPSS_PROC 3
16
+
#define SM8550_MASTER_CAMNOC_HF 4
17
+
#define SM8550_MASTER_CAMNOC_ICP 5
18
+
#define SM8550_MASTER_CAMNOC_SF 6
19
+
#define SM8550_MASTER_CDSP_HCP 7
20
+
#define SM8550_MASTER_CDSP_PROC 8
21
+
#define SM8550_MASTER_CNOC_CFG 9
22
+
#define SM8550_MASTER_CNOC_MNOC_CFG 10
23
+
#define SM8550_MASTER_COMPUTE_NOC 11
24
+
#define SM8550_MASTER_CRYPTO 12
25
+
#define SM8550_MASTER_GEM_NOC_CNOC 13
26
+
#define SM8550_MASTER_GEM_NOC_PCIE_SNOC 14
27
+
#define SM8550_MASTER_GFX3D 15
28
+
#define SM8550_MASTER_GIC 16
29
+
#define SM8550_MASTER_GIC_AHB 17
30
+
#define SM8550_MASTER_GPU_TCU 18
31
+
#define SM8550_MASTER_IPA 19
32
+
#define SM8550_MASTER_LLCC 20
33
+
#define SM8550_MASTER_LPASS_GEM_NOC 21
34
+
#define SM8550_MASTER_LPASS_LPINOC 22
35
+
#define SM8550_MASTER_LPASS_PROC 23
36
+
#define SM8550_MASTER_LPIAON_NOC 24
37
+
#define SM8550_MASTER_MDP 25
38
+
#define SM8550_MASTER_MNOC_HF_MEM_NOC 26
39
+
#define SM8550_MASTER_MNOC_SF_MEM_NOC 27
40
+
#define SM8550_MASTER_MSS_PROC 28
41
+
#define SM8550_MASTER_PCIE_0 29
42
+
#define SM8550_MASTER_PCIE_1 30
43
+
#define SM8550_MASTER_PCIE_ANOC_CFG 31
44
+
#define SM8550_MASTER_QDSS_BAM 32
45
+
#define SM8550_MASTER_QDSS_ETR 33
46
+
#define SM8550_MASTER_QDSS_ETR_1 34
47
+
#define SM8550_MASTER_QSPI_0 35
48
+
#define SM8550_MASTER_QUP_1 36
49
+
#define SM8550_MASTER_QUP_2 37
50
+
#define SM8550_MASTER_QUP_CORE_0 38
51
+
#define SM8550_MASTER_QUP_CORE_1 39
52
+
#define SM8550_MASTER_QUP_CORE_2 40
53
+
#define SM8550_MASTER_SDCC_2 41
54
+
#define SM8550_MASTER_SDCC_4 42
55
+
#define SM8550_MASTER_SNOC_GC_MEM_NOC 43
56
+
#define SM8550_MASTER_SNOC_SF_MEM_NOC 44
57
+
#define SM8550_MASTER_SP 45
58
+
#define SM8550_MASTER_SYS_TCU 46
59
+
#define SM8550_MASTER_UFS_MEM 47
60
+
#define SM8550_MASTER_USB3_0 48
61
+
#define SM8550_MASTER_VIDEO 49
62
+
#define SM8550_MASTER_VIDEO_CV_PROC 50
63
+
#define SM8550_MASTER_VIDEO_PROC 51
64
+
#define SM8550_MASTER_VIDEO_V_PROC 52
65
+
#define SM8550_SLAVE_A1NOC_SNOC 53
66
+
#define SM8550_SLAVE_A2NOC_SNOC 54
67
+
#define SM8550_SLAVE_AHB2PHY_NORTH 55
68
+
#define SM8550_SLAVE_AHB2PHY_SOUTH 56
69
+
#define SM8550_SLAVE_ANOC_PCIE_GEM_NOC 57
70
+
#define SM8550_SLAVE_AOSS 58
71
+
#define SM8550_SLAVE_APPSS 59
72
+
#define SM8550_SLAVE_BOOT_IMEM 60
73
+
#define SM8550_SLAVE_CAMERA_CFG 61
74
+
#define SM8550_SLAVE_CDSP_MEM_NOC 62
75
+
#define SM8550_SLAVE_CLK_CTL 63
76
+
#define SM8550_SLAVE_CNOC_CFG 64
77
+
#define SM8550_SLAVE_CNOC_MNOC_CFG 65
78
+
#define SM8550_SLAVE_CNOC_MSS 66
79
+
#define SM8550_SLAVE_CPR_NSPCX 67
80
+
#define SM8550_SLAVE_CRYPTO_0_CFG 68
81
+
#define SM8550_SLAVE_CX_RDPM 69
82
+
#define SM8550_SLAVE_DDRSS_CFG 70
83
+
#define SM8550_SLAVE_DISPLAY_CFG 71
84
+
#define SM8550_SLAVE_EBI1 72
85
+
#define SM8550_SLAVE_GEM_NOC_CNOC 73
86
+
#define SM8550_SLAVE_GFX3D_CFG 74
87
+
#define SM8550_SLAVE_I2C 75
88
+
#define SM8550_SLAVE_IMEM 76
89
+
#define SM8550_SLAVE_IMEM_CFG 77
90
+
#define SM8550_SLAVE_IPA_CFG 78
91
+
#define SM8550_SLAVE_IPC_ROUTER_CFG 79
92
+
#define SM8550_SLAVE_LLCC 80
93
+
#define SM8550_SLAVE_LPASS_GEM_NOC 81
94
+
#define SM8550_SLAVE_LPASS_QTB_CFG 82
95
+
#define SM8550_SLAVE_LPIAON_NOC_LPASS_AG_NOC 83
96
+
#define SM8550_SLAVE_LPICX_NOC_LPIAON_NOC 84
97
+
#define SM8550_SLAVE_MEM_NOC_PCIE_SNOC 85
98
+
#define SM8550_SLAVE_MNOC_HF_MEM_NOC 86
99
+
#define SM8550_SLAVE_MNOC_SF_MEM_NOC 87
100
+
#define SM8550_SLAVE_MX_RDPM 88
101
+
#define SM8550_SLAVE_NSP_QTB_CFG 89
102
+
#define SM8550_SLAVE_PCIE_0 90
103
+
#define SM8550_SLAVE_PCIE_0_CFG 91
104
+
#define SM8550_SLAVE_PCIE_1 92
105
+
#define SM8550_SLAVE_PCIE_1_CFG 93
106
+
#define SM8550_SLAVE_PCIE_ANOC_CFG 94
107
+
#define SM8550_SLAVE_PDM 95
108
+
#define SM8550_SLAVE_PIMEM_CFG 96
109
+
#define SM8550_SLAVE_PRNG 97
110
+
#define SM8550_SLAVE_QDSS_CFG 98
111
+
#define SM8550_SLAVE_QDSS_STM 99
112
+
#define SM8550_SLAVE_QSPI_0 100
113
+
#define SM8550_SLAVE_QUP_1 101
114
+
#define SM8550_SLAVE_QUP_2 102
115
+
#define SM8550_SLAVE_QUP_CORE_0 103
116
+
#define SM8550_SLAVE_QUP_CORE_1 104
117
+
#define SM8550_SLAVE_QUP_CORE_2 105
118
+
#define SM8550_SLAVE_RBCPR_CX_CFG 106
119
+
#define SM8550_SLAVE_RBCPR_MMCX_CFG 107
120
+
#define SM8550_SLAVE_RBCPR_MXA_CFG 108
121
+
#define SM8550_SLAVE_RBCPR_MXC_CFG 109
122
+
#define SM8550_SLAVE_SDCC_2 110
123
+
#define SM8550_SLAVE_SDCC_4 111
124
+
#define SM8550_SLAVE_SERVICE_MNOC 112
125
+
#define SM8550_SLAVE_SERVICE_PCIE_ANOC 113
126
+
#define SM8550_SLAVE_SNOC_GEM_NOC_GC 114
127
+
#define SM8550_SLAVE_SNOC_GEM_NOC_SF 115
128
+
#define SM8550_SLAVE_SPSS_CFG 116
129
+
#define SM8550_SLAVE_TCSR 117
130
+
#define SM8550_SLAVE_TCU 118
131
+
#define SM8550_SLAVE_TLMM 119
132
+
#define SM8550_SLAVE_TME_CFG 120
133
+
#define SM8550_SLAVE_UFS_MEM_CFG 121
134
+
#define SM8550_SLAVE_USB3_0 122
135
+
#define SM8550_SLAVE_VENUS_CFG 123
136
+
#define SM8550_SLAVE_VSENSE_CTRL_CFG 124
177
137
178
138
#endif
+6
-321
drivers/interconnect/qcom/x1e80100.c
+6
-321
drivers/interconnect/qcom/x1e80100.c
···
670
670
.links = { X1E80100_SLAVE_AGGRE_USB_SOUTH },
671
671
};
672
672
673
-
static struct qcom_icc_node qnm_mnoc_hf_disp = {
674
-
.name = "qnm_mnoc_hf_disp",
675
-
.id = X1E80100_MASTER_MNOC_HF_MEM_NOC_DISP,
676
-
.channels = 2,
677
-
.buswidth = 32,
678
-
.num_links = 1,
679
-
.links = { X1E80100_SLAVE_LLCC_DISP },
680
-
};
681
-
682
-
static struct qcom_icc_node qnm_pcie_disp = {
683
-
.name = "qnm_pcie_disp",
684
-
.id = X1E80100_MASTER_ANOC_PCIE_GEM_NOC_DISP,
685
-
.channels = 1,
686
-
.buswidth = 64,
687
-
.num_links = 1,
688
-
.links = { X1E80100_SLAVE_LLCC_DISP },
689
-
};
690
-
691
-
static struct qcom_icc_node llcc_mc_disp = {
692
-
.name = "llcc_mc_disp",
693
-
.id = X1E80100_MASTER_LLCC_DISP,
694
-
.channels = 8,
695
-
.buswidth = 4,
696
-
.num_links = 1,
697
-
.links = { X1E80100_SLAVE_EBI1_DISP },
698
-
};
699
-
700
-
static struct qcom_icc_node qnm_mdp_disp = {
701
-
.name = "qnm_mdp_disp",
702
-
.id = X1E80100_MASTER_MDP_DISP,
703
-
.channels = 2,
704
-
.buswidth = 32,
705
-
.num_links = 1,
706
-
.links = { X1E80100_SLAVE_MNOC_HF_MEM_NOC_DISP },
707
-
};
708
-
709
-
static struct qcom_icc_node qnm_pcie_pcie = {
710
-
.name = "qnm_pcie_pcie",
711
-
.id = X1E80100_MASTER_ANOC_PCIE_GEM_NOC_PCIE,
712
-
.channels = 1,
713
-
.buswidth = 64,
714
-
.num_links = 1,
715
-
.links = { X1E80100_SLAVE_LLCC_PCIE },
716
-
};
717
-
718
-
static struct qcom_icc_node llcc_mc_pcie = {
719
-
.name = "llcc_mc_pcie",
720
-
.id = X1E80100_MASTER_LLCC_PCIE,
721
-
.channels = 8,
722
-
.buswidth = 4,
723
-
.num_links = 1,
724
-
.links = { X1E80100_SLAVE_EBI1_PCIE },
725
-
};
726
-
727
-
static struct qcom_icc_node qnm_pcie_north_gem_noc_pcie = {
728
-
.name = "qnm_pcie_north_gem_noc_pcie",
729
-
.id = X1E80100_MASTER_PCIE_NORTH_PCIE,
730
-
.channels = 1,
731
-
.buswidth = 64,
732
-
.num_links = 1,
733
-
.links = { X1E80100_SLAVE_ANOC_PCIE_GEM_NOC_PCIE },
734
-
};
735
-
736
-
static struct qcom_icc_node qnm_pcie_south_gem_noc_pcie = {
737
-
.name = "qnm_pcie_south_gem_noc_pcie",
738
-
.id = X1E80100_MASTER_PCIE_SOUTH_PCIE,
739
-
.channels = 1,
740
-
.buswidth = 64,
741
-
.num_links = 1,
742
-
.links = { X1E80100_SLAVE_ANOC_PCIE_GEM_NOC_PCIE },
743
-
};
744
-
745
-
static struct qcom_icc_node xm_pcie_3_pcie = {
746
-
.name = "xm_pcie_3_pcie",
747
-
.id = X1E80100_MASTER_PCIE_3_PCIE,
748
-
.channels = 1,
749
-
.buswidth = 64,
750
-
.num_links = 1,
751
-
.links = { X1E80100_SLAVE_PCIE_NORTH_PCIE },
752
-
};
753
-
754
-
static struct qcom_icc_node xm_pcie_4_pcie = {
755
-
.name = "xm_pcie_4_pcie",
756
-
.id = X1E80100_MASTER_PCIE_4_PCIE,
757
-
.channels = 1,
758
-
.buswidth = 8,
759
-
.num_links = 1,
760
-
.links = { X1E80100_SLAVE_PCIE_NORTH_PCIE },
761
-
};
762
-
763
-
static struct qcom_icc_node xm_pcie_5_pcie = {
764
-
.name = "xm_pcie_5_pcie",
765
-
.id = X1E80100_MASTER_PCIE_5_PCIE,
766
-
.channels = 1,
767
-
.buswidth = 8,
768
-
.num_links = 1,
769
-
.links = { X1E80100_SLAVE_PCIE_NORTH_PCIE },
770
-
};
771
-
772
-
static struct qcom_icc_node xm_pcie_0_pcie = {
773
-
.name = "xm_pcie_0_pcie",
774
-
.id = X1E80100_MASTER_PCIE_0_PCIE,
775
-
.channels = 1,
776
-
.buswidth = 16,
777
-
.num_links = 1,
778
-
.links = { X1E80100_SLAVE_PCIE_SOUTH_PCIE },
779
-
};
780
-
781
-
static struct qcom_icc_node xm_pcie_1_pcie = {
782
-
.name = "xm_pcie_1_pcie",
783
-
.id = X1E80100_MASTER_PCIE_1_PCIE,
784
-
.channels = 1,
785
-
.buswidth = 16,
786
-
.num_links = 1,
787
-
.links = { X1E80100_SLAVE_PCIE_SOUTH_PCIE },
788
-
};
789
-
790
-
static struct qcom_icc_node xm_pcie_2_pcie = {
791
-
.name = "xm_pcie_2_pcie",
792
-
.id = X1E80100_MASTER_PCIE_2_PCIE,
793
-
.channels = 1,
794
-
.buswidth = 16,
795
-
.num_links = 1,
796
-
.links = { X1E80100_SLAVE_PCIE_SOUTH_PCIE },
797
-
};
798
-
799
-
static struct qcom_icc_node xm_pcie_6a_pcie = {
800
-
.name = "xm_pcie_6a_pcie",
801
-
.id = X1E80100_MASTER_PCIE_6A_PCIE,
802
-
.channels = 1,
803
-
.buswidth = 32,
804
-
.num_links = 1,
805
-
.links = { X1E80100_SLAVE_PCIE_SOUTH_PCIE },
806
-
};
807
-
808
-
static struct qcom_icc_node xm_pcie_6b_pcie = {
809
-
.name = "xm_pcie_6b_pcie",
810
-
.id = X1E80100_MASTER_PCIE_6B_PCIE,
811
-
.channels = 1,
812
-
.buswidth = 16,
813
-
.num_links = 1,
814
-
.links = { X1E80100_SLAVE_PCIE_SOUTH_PCIE },
815
-
};
816
-
817
673
static struct qcom_icc_node qns_a1noc_snoc = {
818
674
.name = "qns_a1noc_snoc",
819
675
.id = X1E80100_SLAVE_A1NOC_SNOC,
···
1370
1514
.links = { X1E80100_MASTER_AGGRE_USB_SOUTH },
1371
1515
};
1372
1516
1373
-
static struct qcom_icc_node qns_llcc_disp = {
1374
-
.name = "qns_llcc_disp",
1375
-
.id = X1E80100_SLAVE_LLCC_DISP,
1376
-
.channels = 8,
1377
-
.buswidth = 16,
1378
-
.num_links = 1,
1379
-
.links = { X1E80100_MASTER_LLCC_DISP },
1380
-
};
1381
-
1382
-
static struct qcom_icc_node ebi_disp = {
1383
-
.name = "ebi_disp",
1384
-
.id = X1E80100_SLAVE_EBI1_DISP,
1385
-
.channels = 8,
1386
-
.buswidth = 4,
1387
-
.num_links = 0,
1388
-
};
1389
-
1390
-
static struct qcom_icc_node qns_mem_noc_hf_disp = {
1391
-
.name = "qns_mem_noc_hf_disp",
1392
-
.id = X1E80100_SLAVE_MNOC_HF_MEM_NOC_DISP,
1393
-
.channels = 2,
1394
-
.buswidth = 32,
1395
-
.num_links = 1,
1396
-
.links = { X1E80100_MASTER_MNOC_HF_MEM_NOC_DISP },
1397
-
};
1398
-
1399
-
static struct qcom_icc_node qns_llcc_pcie = {
1400
-
.name = "qns_llcc_pcie",
1401
-
.id = X1E80100_SLAVE_LLCC_PCIE,
1402
-
.channels = 8,
1403
-
.buswidth = 16,
1404
-
.num_links = 1,
1405
-
.links = { X1E80100_MASTER_LLCC_PCIE },
1406
-
};
1407
-
1408
-
static struct qcom_icc_node ebi_pcie = {
1409
-
.name = "ebi_pcie",
1410
-
.id = X1E80100_SLAVE_EBI1_PCIE,
1411
-
.channels = 8,
1412
-
.buswidth = 4,
1413
-
.num_links = 0,
1414
-
};
1415
-
1416
-
static struct qcom_icc_node qns_pcie_mem_noc_pcie = {
1417
-
.name = "qns_pcie_mem_noc_pcie",
1418
-
.id = X1E80100_SLAVE_ANOC_PCIE_GEM_NOC_PCIE,
1419
-
.channels = 1,
1420
-
.buswidth = 64,
1421
-
.num_links = 1,
1422
-
.links = { X1E80100_MASTER_ANOC_PCIE_GEM_NOC_PCIE },
1423
-
};
1424
-
1425
-
static struct qcom_icc_node qns_pcie_north_gem_noc_pcie = {
1426
-
.name = "qns_pcie_north_gem_noc_pcie",
1427
-
.id = X1E80100_SLAVE_PCIE_NORTH_PCIE,
1428
-
.channels = 1,
1429
-
.buswidth = 64,
1430
-
.num_links = 1,
1431
-
.links = { X1E80100_MASTER_PCIE_NORTH_PCIE },
1432
-
};
1433
-
1434
-
static struct qcom_icc_node qns_pcie_south_gem_noc_pcie = {
1435
-
.name = "qns_pcie_south_gem_noc_pcie",
1436
-
.id = X1E80100_SLAVE_PCIE_SOUTH_PCIE,
1437
-
.channels = 1,
1438
-
.buswidth = 64,
1439
-
.num_links = 1,
1440
-
.links = { X1E80100_MASTER_PCIE_SOUTH_PCIE },
1441
-
};
1442
-
1443
1517
static struct qcom_icc_bcm bcm_acv = {
1444
1518
.name = "ACV",
1445
1519
.enable_mask = BIT(3),
···
1542
1756
.nodes = { &qnm_usb_anoc },
1543
1757
};
1544
1758
1545
-
static struct qcom_icc_bcm bcm_acv_disp = {
1546
-
.name = "ACV",
1547
-
.num_nodes = 1,
1548
-
.nodes = { &ebi_disp },
1549
-
};
1550
-
1551
-
static struct qcom_icc_bcm bcm_mc0_disp = {
1552
-
.name = "MC0",
1553
-
.num_nodes = 1,
1554
-
.nodes = { &ebi_disp },
1555
-
};
1556
-
1557
-
static struct qcom_icc_bcm bcm_mm0_disp = {
1558
-
.name = "MM0",
1559
-
.num_nodes = 1,
1560
-
.nodes = { &qns_mem_noc_hf_disp },
1561
-
};
1562
-
1563
-
static struct qcom_icc_bcm bcm_mm1_disp = {
1564
-
.name = "MM1",
1565
-
.num_nodes = 1,
1566
-
.nodes = { &qnm_mdp_disp },
1567
-
};
1568
-
1569
-
static struct qcom_icc_bcm bcm_sh0_disp = {
1570
-
.name = "SH0",
1571
-
.num_nodes = 1,
1572
-
.nodes = { &qns_llcc_disp },
1573
-
};
1574
-
1575
-
static struct qcom_icc_bcm bcm_sh1_disp = {
1576
-
.name = "SH1",
1577
-
.num_nodes = 2,
1578
-
.nodes = { &qnm_mnoc_hf_disp, &qnm_pcie_disp },
1579
-
};
1580
-
1581
-
static struct qcom_icc_bcm bcm_acv_pcie = {
1582
-
.name = "ACV",
1583
-
.num_nodes = 1,
1584
-
.nodes = { &ebi_pcie },
1585
-
};
1586
-
1587
-
static struct qcom_icc_bcm bcm_mc0_pcie = {
1588
-
.name = "MC0",
1589
-
.num_nodes = 1,
1590
-
.nodes = { &ebi_pcie },
1591
-
};
1592
-
1593
-
static struct qcom_icc_bcm bcm_pc0_pcie = {
1594
-
.name = "PC0",
1595
-
.num_nodes = 1,
1596
-
.nodes = { &qns_pcie_mem_noc_pcie },
1597
-
};
1598
-
1599
-
static struct qcom_icc_bcm bcm_sh0_pcie = {
1600
-
.name = "SH0",
1601
-
.num_nodes = 1,
1602
-
.nodes = { &qns_llcc_pcie },
1603
-
};
1604
-
1605
-
static struct qcom_icc_bcm bcm_sh1_pcie = {
1606
-
.name = "SH1",
1607
-
.num_nodes = 1,
1608
-
.nodes = { &qnm_pcie_pcie },
1609
-
};
1610
-
1611
-
static struct qcom_icc_bcm *aggre1_noc_bcms[] = {
1759
+
static struct qcom_icc_bcm * const aggre1_noc_bcms[] = {
1612
1760
};
1613
1761
1614
1762
static struct qcom_icc_node * const aggre1_noc_nodes[] = {
···
1703
1983
static struct qcom_icc_bcm * const gem_noc_bcms[] = {
1704
1984
&bcm_sh0,
1705
1985
&bcm_sh1,
1706
-
&bcm_sh0_disp,
1707
-
&bcm_sh1_disp,
1708
-
&bcm_sh0_pcie,
1709
-
&bcm_sh1_pcie,
1710
1986
};
1711
1987
1712
1988
static struct qcom_icc_node * const gem_noc_nodes[] = {
···
1721
2005
[SLAVE_GEM_NOC_CNOC] = &qns_gem_noc_cnoc,
1722
2006
[SLAVE_LLCC] = &qns_llcc,
1723
2007
[SLAVE_MEM_NOC_PCIE_SNOC] = &qns_pcie,
1724
-
[MASTER_MNOC_HF_MEM_NOC_DISP] = &qnm_mnoc_hf_disp,
1725
-
[MASTER_ANOC_PCIE_GEM_NOC_DISP] = &qnm_pcie_disp,
1726
-
[SLAVE_LLCC_DISP] = &qns_llcc_disp,
1727
-
[MASTER_ANOC_PCIE_GEM_NOC_PCIE] = &qnm_pcie_pcie,
1728
-
[SLAVE_LLCC_PCIE] = &qns_llcc_pcie,
1729
2008
};
1730
2009
1731
2010
static const struct qcom_icc_desc x1e80100_gem_noc = {
···
1730
2019
.num_bcms = ARRAY_SIZE(gem_noc_bcms),
1731
2020
};
1732
2021
1733
-
static struct qcom_icc_bcm *lpass_ag_noc_bcms[] = {
2022
+
static struct qcom_icc_bcm * const lpass_ag_noc_bcms[] = {
1734
2023
};
1735
2024
1736
2025
static struct qcom_icc_node * const lpass_ag_noc_nodes[] = {
···
1779
2068
static struct qcom_icc_bcm * const mc_virt_bcms[] = {
1780
2069
&bcm_acv,
1781
2070
&bcm_mc0,
1782
-
&bcm_acv_disp,
1783
-
&bcm_mc0_disp,
1784
-
&bcm_acv_pcie,
1785
-
&bcm_mc0_pcie,
1786
2071
};
1787
2072
1788
2073
static struct qcom_icc_node * const mc_virt_nodes[] = {
1789
2074
[MASTER_LLCC] = &llcc_mc,
1790
2075
[SLAVE_EBI1] = &ebi,
1791
-
[MASTER_LLCC_DISP] = &llcc_mc_disp,
1792
-
[SLAVE_EBI1_DISP] = &ebi_disp,
1793
-
[MASTER_LLCC_PCIE] = &llcc_mc_pcie,
1794
-
[SLAVE_EBI1_PCIE] = &ebi_pcie,
1795
2076
};
1796
2077
1797
2078
static const struct qcom_icc_desc x1e80100_mc_virt = {
···
1796
2093
static struct qcom_icc_bcm * const mmss_noc_bcms[] = {
1797
2094
&bcm_mm0,
1798
2095
&bcm_mm1,
1799
-
&bcm_mm0_disp,
1800
-
&bcm_mm1_disp,
1801
2096
};
1802
2097
1803
2098
static struct qcom_icc_node * const mmss_noc_nodes[] = {
···
1812
2111
[SLAVE_MNOC_HF_MEM_NOC] = &qns_mem_noc_hf,
1813
2112
[SLAVE_MNOC_SF_MEM_NOC] = &qns_mem_noc_sf,
1814
2113
[SLAVE_SERVICE_MNOC] = &srvc_mnoc,
1815
-
[MASTER_MDP_DISP] = &qnm_mdp_disp,
1816
-
[SLAVE_MNOC_HF_MEM_NOC_DISP] = &qns_mem_noc_hf_disp,
1817
2114
};
1818
2115
1819
2116
static const struct qcom_icc_desc x1e80100_mmss_noc = {
···
1839
2140
1840
2141
static struct qcom_icc_bcm * const pcie_center_anoc_bcms[] = {
1841
2142
&bcm_pc0,
1842
-
&bcm_pc0_pcie,
1843
2143
};
1844
2144
1845
2145
static struct qcom_icc_node * const pcie_center_anoc_nodes[] = {
1846
2146
[MASTER_PCIE_NORTH] = &qnm_pcie_north_gem_noc,
1847
2147
[MASTER_PCIE_SOUTH] = &qnm_pcie_south_gem_noc,
1848
2148
[SLAVE_ANOC_PCIE_GEM_NOC] = &qns_pcie_mem_noc,
1849
-
[MASTER_PCIE_NORTH_PCIE] = &qnm_pcie_north_gem_noc_pcie,
1850
-
[MASTER_PCIE_SOUTH_PCIE] = &qnm_pcie_south_gem_noc_pcie,
1851
-
[SLAVE_ANOC_PCIE_GEM_NOC_PCIE] = &qns_pcie_mem_noc_pcie,
1852
2149
};
1853
2150
1854
2151
static const struct qcom_icc_desc x1e80100_pcie_center_anoc = {
···
1862
2167
[MASTER_PCIE_4] = &xm_pcie_4,
1863
2168
[MASTER_PCIE_5] = &xm_pcie_5,
1864
2169
[SLAVE_PCIE_NORTH] = &qns_pcie_north_gem_noc,
1865
-
[MASTER_PCIE_3_PCIE] = &xm_pcie_3_pcie,
1866
-
[MASTER_PCIE_4_PCIE] = &xm_pcie_4_pcie,
1867
-
[MASTER_PCIE_5_PCIE] = &xm_pcie_5_pcie,
1868
-
[SLAVE_PCIE_NORTH_PCIE] = &qns_pcie_north_gem_noc_pcie,
1869
2170
};
1870
2171
1871
2172
static const struct qcom_icc_desc x1e80100_pcie_north_anoc = {
···
1871
2180
.num_bcms = ARRAY_SIZE(pcie_north_anoc_bcms),
1872
2181
};
1873
2182
1874
-
static struct qcom_icc_bcm *pcie_south_anoc_bcms[] = {
2183
+
static struct qcom_icc_bcm * const pcie_south_anoc_bcms[] = {
1875
2184
};
1876
2185
1877
2186
static struct qcom_icc_node * const pcie_south_anoc_nodes[] = {
···
1881
2190
[MASTER_PCIE_6A] = &xm_pcie_6a,
1882
2191
[MASTER_PCIE_6B] = &xm_pcie_6b,
1883
2192
[SLAVE_PCIE_SOUTH] = &qns_pcie_south_gem_noc,
1884
-
[MASTER_PCIE_0_PCIE] = &xm_pcie_0_pcie,
1885
-
[MASTER_PCIE_1_PCIE] = &xm_pcie_1_pcie,
1886
-
[MASTER_PCIE_2_PCIE] = &xm_pcie_2_pcie,
1887
-
[MASTER_PCIE_6A_PCIE] = &xm_pcie_6a_pcie,
1888
-
[MASTER_PCIE_6B_PCIE] = &xm_pcie_6b_pcie,
1889
-
[SLAVE_PCIE_SOUTH_PCIE] = &qns_pcie_south_gem_noc_pcie,
1890
2193
};
1891
2194
1892
2195
static const struct qcom_icc_desc x1e80100_pcie_south_anoc = {
···
1890
2205
.num_bcms = ARRAY_SIZE(pcie_south_anoc_bcms),
1891
2206
};
1892
2207
1893
-
static struct qcom_icc_bcm *system_noc_bcms[] = {
2208
+
static struct qcom_icc_bcm * const system_noc_bcms[] = {
1894
2209
&bcm_sn0,
1895
2210
&bcm_sn2,
1896
2211
&bcm_sn3,
···
1928
2243
.num_bcms = ARRAY_SIZE(usb_center_anoc_bcms),
1929
2244
};
1930
2245
1931
-
static struct qcom_icc_bcm *usb_north_anoc_bcms[] = {
2246
+
static struct qcom_icc_bcm * const usb_north_anoc_bcms[] = {
1932
2247
};
1933
2248
1934
2249
static struct qcom_icc_node * const usb_north_anoc_nodes[] = {
···
1944
2259
.num_bcms = ARRAY_SIZE(usb_north_anoc_bcms),
1945
2260
};
1946
2261
1947
-
static struct qcom_icc_bcm *usb_south_anoc_bcms[] = {
2262
+
static struct qcom_icc_bcm * const usb_south_anoc_bcms[] = {
1948
2263
};
1949
2264
1950
2265
static struct qcom_icc_node * const usb_south_anoc_nodes[] = {
+1
-1
drivers/interconnect/samsung/exynos.c
+1
-1
drivers/interconnect/samsung/exynos.c
+1
-1
drivers/memory/tegra/mc.c
+1
-1
drivers/memory/tegra/mc.c
···
755
755
[6] = "SMMU translation error",
756
756
};
757
757
758
-
struct icc_node *tegra_mc_icc_xlate(struct of_phandle_args *spec, void *data)
758
+
struct icc_node *tegra_mc_icc_xlate(const struct of_phandle_args *spec, void *data)
759
759
{
760
760
struct tegra_mc *mc = icc_provider_to_tegra_mc(data);
761
761
struct icc_node *node;
+1
-1
drivers/memory/tegra/tegra124-emc.c
+1
-1
drivers/memory/tegra/tegra124-emc.c
···
1285
1285
}
1286
1286
1287
1287
static struct icc_node_data *
1288
-
emc_of_icc_xlate_extended(struct of_phandle_args *spec, void *data)
1288
+
emc_of_icc_xlate_extended(const struct of_phandle_args *spec, void *data)
1289
1289
{
1290
1290
struct icc_provider *provider = data;
1291
1291
struct icc_node_data *ndata;
+1
-1
drivers/memory/tegra/tegra124.c
+1
-1
drivers/memory/tegra/tegra124.c
···
1170
1170
}
1171
1171
1172
1172
static struct icc_node_data *
1173
-
tegra124_mc_of_icc_xlate_extended(struct of_phandle_args *spec, void *data)
1173
+
tegra124_mc_of_icc_xlate_extended(const struct of_phandle_args *spec, void *data)
1174
1174
{
1175
1175
struct tegra_mc *mc = icc_provider_to_tegra_mc(data);
1176
1176
const struct tegra_mc_client *client;
+1
-1
drivers/memory/tegra/tegra186-emc.c
+1
-1
drivers/memory/tegra/tegra186-emc.c
+1
-1
drivers/memory/tegra/tegra20-emc.c
+1
-1
drivers/memory/tegra/tegra20-emc.c
···
950
950
}
951
951
952
952
static struct icc_node_data *
953
-
emc_of_icc_xlate_extended(struct of_phandle_args *spec, void *data)
953
+
emc_of_icc_xlate_extended(const struct of_phandle_args *spec, void *data)
954
954
{
955
955
struct icc_provider *provider = data;
956
956
struct icc_node_data *ndata;
+1
-1
drivers/memory/tegra/tegra20.c
+1
-1
drivers/memory/tegra/tegra20.c
···
390
390
}
391
391
392
392
static struct icc_node_data *
393
-
tegra20_mc_of_icc_xlate_extended(struct of_phandle_args *spec, void *data)
393
+
tegra20_mc_of_icc_xlate_extended(const struct of_phandle_args *spec, void *data)
394
394
{
395
395
struct tegra_mc *mc = icc_provider_to_tegra_mc(data);
396
396
unsigned int i, idx = spec->args[0];
+1
-1
drivers/memory/tegra/tegra30-emc.c
+1
-1
drivers/memory/tegra/tegra30-emc.c
···
1468
1468
}
1469
1469
1470
1470
static struct icc_node_data *
1471
-
emc_of_icc_xlate_extended(struct of_phandle_args *spec, void *data)
1471
+
emc_of_icc_xlate_extended(const struct of_phandle_args *spec, void *data)
1472
1472
{
1473
1473
struct icc_provider *provider = data;
1474
1474
struct icc_node_data *ndata;
+1
-1
drivers/memory/tegra/tegra30.c
+1
-1
drivers/memory/tegra/tegra30.c
···
1332
1332
}
1333
1333
1334
1334
static struct icc_node_data *
1335
-
tegra30_mc_of_icc_xlate_extended(struct of_phandle_args *spec, void *data)
1335
+
tegra30_mc_of_icc_xlate_extended(const struct of_phandle_args *spec, void *data)
1336
1336
{
1337
1337
struct tegra_mc *mc = icc_provider_to_tegra_mc(data);
1338
1338
const struct tegra_mc_client *client;
+93
include/dt-bindings/interconnect/qcom,msm8909.h
+93
include/dt-bindings/interconnect/qcom,msm8909.h
···
1
+
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
2
+
/*
3
+
* Qualcomm MSM8909 interconnect IDs
4
+
*/
5
+
6
+
#ifndef __DT_BINDINGS_INTERCONNECT_QCOM_MSM8909_H
7
+
#define __DT_BINDINGS_INTERCONNECT_QCOM_MSM8909_H
8
+
9
+
/* BIMC fabric */
10
+
#define MAS_APPS_PROC 0
11
+
#define MAS_OXILI 1
12
+
#define MAS_SNOC_BIMC_0 2
13
+
#define MAS_SNOC_BIMC_1 3
14
+
#define MAS_TCU_0 4
15
+
#define MAS_TCU_1 5
16
+
#define SLV_EBI 6
17
+
#define SLV_BIMC_SNOC 7
18
+
19
+
/* PCNOC fabric */
20
+
#define MAS_AUDIO 0
21
+
#define MAS_SPDM 1
22
+
#define MAS_DEHR 2
23
+
#define MAS_QPIC 3
24
+
#define MAS_BLSP_1 4
25
+
#define MAS_USB_HS 5
26
+
#define MAS_CRYPTO 6
27
+
#define MAS_SDCC_1 7
28
+
#define MAS_SDCC_2 8
29
+
#define MAS_SNOC_PCNOC 9
30
+
#define PCNOC_M_0 10
31
+
#define PCNOC_M_1 11
32
+
#define PCNOC_INT_0 12
33
+
#define PCNOC_INT_1 13
34
+
#define PCNOC_S_0 14
35
+
#define PCNOC_S_1 15
36
+
#define PCNOC_S_2 16
37
+
#define PCNOC_S_3 17
38
+
#define PCNOC_S_4 18
39
+
#define PCNOC_S_5 19
40
+
#define PCNOC_S_7 20
41
+
#define SLV_TCSR 21
42
+
#define SLV_SDCC_1 22
43
+
#define SLV_BLSP_1 23
44
+
#define SLV_CRYPTO_0_CFG 24
45
+
#define SLV_MESSAGE_RAM 25
46
+
#define SLV_PDM 26
47
+
#define SLV_PRNG 27
48
+
#define SLV_USB_HS 28
49
+
#define SLV_QPIC 29
50
+
#define SLV_SPDM 30
51
+
#define SLV_SDCC_2 31
52
+
#define SLV_AUDIO 32
53
+
#define SLV_DEHR_CFG 33
54
+
#define SLV_SNOC_CFG 34
55
+
#define SLV_QDSS_CFG 35
56
+
#define SLV_USB_PHY 36
57
+
#define SLV_CAMERA_SS_CFG 37
58
+
#define SLV_DISP_SS_CFG 38
59
+
#define SLV_VENUS_CFG 39
60
+
#define SLV_TLMM 40
61
+
#define SLV_GPU_CFG 41
62
+
#define SLV_IMEM_CFG 42
63
+
#define SLV_BIMC_CFG 43
64
+
#define SLV_PMIC_ARB 44
65
+
#define SLV_TCU 45
66
+
#define SLV_PCNOC_SNOC 46
67
+
68
+
/* SNOC fabric */
69
+
#define MAS_QDSS_BAM 0
70
+
#define MAS_BIMC_SNOC 1
71
+
#define MAS_MDP 2
72
+
#define MAS_PCNOC_SNOC 3
73
+
#define MAS_VENUS 4
74
+
#define MAS_VFE 5
75
+
#define MAS_QDSS_ETR 6
76
+
#define MM_INT_0 7
77
+
#define MM_INT_1 8
78
+
#define MM_INT_2 9
79
+
#define MM_INT_BIMC 10
80
+
#define QDSS_INT 11
81
+
#define SNOC_INT_0 12
82
+
#define SNOC_INT_1 13
83
+
#define SNOC_INT_BIMC 14
84
+
#define SLV_KPSS_AHB 15
85
+
#define SLV_SNOC_BIMC_0 16
86
+
#define SLV_SNOC_BIMC_1 17
87
+
#define SLV_IMEM 18
88
+
#define SLV_SNOC_PCNOC 19
89
+
#define SLV_QDSS_STM 20
90
+
#define SLV_CATS_0 21
91
+
#define SLV_CATS_1 22
92
+
93
+
#endif /* __DT_BINDINGS_INTERCONNECT_QCOM_MSM8909_H */
+150
include/dt-bindings/interconnect/qcom,sm7150-rpmh.h
+150
include/dt-bindings/interconnect/qcom,sm7150-rpmh.h
···
1
+
/* SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause */
2
+
/*
3
+
* Qualcomm SM7150 interconnect IDs
4
+
*
5
+
* Copyright (c) 2020, The Linux Foundation. All rights reserved.
6
+
* Copyright (c) 2024, Danila Tikhonov <danila@jiaxyga.com>
7
+
*/
8
+
9
+
#ifndef __DT_BINDINGS_INTERCONNECT_QCOM_SM7150_H
10
+
#define __DT_BINDINGS_INTERCONNECT_QCOM_SM7150_H
11
+
12
+
#define MASTER_A1NOC_CFG 0
13
+
#define MASTER_QUP_0 1
14
+
#define MASTER_TSIF 2
15
+
#define MASTER_EMMC 3
16
+
#define MASTER_SDCC_2 4
17
+
#define MASTER_SDCC_4 5
18
+
#define MASTER_UFS_MEM 6
19
+
#define A1NOC_SNOC_SLV 7
20
+
#define SLAVE_SERVICE_A1NOC 8
21
+
22
+
#define MASTER_A2NOC_CFG 0
23
+
#define MASTER_QDSS_BAM 1
24
+
#define MASTER_QUP_1 2
25
+
#define MASTER_CNOC_A2NOC 3
26
+
#define MASTER_CRYPTO_CORE_0 4
27
+
#define MASTER_IPA 5
28
+
#define MASTER_PCIE 6
29
+
#define MASTER_QDSS_ETR 7
30
+
#define MASTER_USB3 8
31
+
#define A2NOC_SNOC_SLV 9
32
+
#define SLAVE_ANOC_PCIE_GEM_NOC 10
33
+
#define SLAVE_SERVICE_A2NOC 11
34
+
35
+
#define MASTER_CAMNOC_HF0_UNCOMP 0
36
+
#define MASTER_CAMNOC_RT_UNCOMP 1
37
+
#define MASTER_CAMNOC_SF_UNCOMP 2
38
+
#define MASTER_CAMNOC_NRT_UNCOMP 3
39
+
#define SLAVE_CAMNOC_UNCOMP 4
40
+
41
+
#define MASTER_NPU 0
42
+
#define SLAVE_CDSP_GEM_NOC 1
43
+
44
+
#define MASTER_SPDM 0
45
+
#define SNOC_CNOC_MAS 1
46
+
#define MASTER_QDSS_DAP 2
47
+
#define SLAVE_A1NOC_CFG 3
48
+
#define SLAVE_A2NOC_CFG 4
49
+
#define SLAVE_AHB2PHY_NORTH 5
50
+
#define SLAVE_AHB2PHY_SOUTH 6
51
+
#define SLAVE_AHB2PHY_WEST 7
52
+
#define SLAVE_AOP 8
53
+
#define SLAVE_AOSS 9
54
+
#define SLAVE_CAMERA_CFG 10
55
+
#define SLAVE_CAMERA_NRT_THROTTLE_CFG 11
56
+
#define SLAVE_CAMERA_RT_THROTTLE_CFG 12
57
+
#define SLAVE_CLK_CTL 13
58
+
#define SLAVE_CDSP_CFG 14
59
+
#define SLAVE_RBCPR_CX_CFG 15
60
+
#define SLAVE_RBCPR_MX_CFG 16
61
+
#define SLAVE_CRYPTO_0_CFG 17
62
+
#define SLAVE_CNOC_DDRSS 18
63
+
#define SLAVE_DISPLAY_CFG 19
64
+
#define SLAVE_DISPLAY_THROTTLE_CFG 20
65
+
#define SLAVE_EMMC_CFG 21
66
+
#define SLAVE_GLM 22
67
+
#define SLAVE_GRAPHICS_3D_CFG 23
68
+
#define SLAVE_IMEM_CFG 24
69
+
#define SLAVE_IPA_CFG 25
70
+
#define SLAVE_CNOC_MNOC_CFG 26
71
+
#define SLAVE_PCIE_CFG 27
72
+
#define SLAVE_PDM 28
73
+
#define SLAVE_PIMEM_CFG 29
74
+
#define SLAVE_PRNG 30
75
+
#define SLAVE_QDSS_CFG 31
76
+
#define SLAVE_QUP_0 32
77
+
#define SLAVE_QUP_1 33
78
+
#define SLAVE_SDCC_2 34
79
+
#define SLAVE_SDCC_4 35
80
+
#define SLAVE_SNOC_CFG 36
81
+
#define SLAVE_SPDM_WRAPPER 37
82
+
#define SLAVE_TCSR 38
83
+
#define SLAVE_TLMM_NORTH 39
84
+
#define SLAVE_TLMM_SOUTH 40
85
+
#define SLAVE_TLMM_WEST 41
86
+
#define SLAVE_TSIF 42
87
+
#define SLAVE_UFS_MEM_CFG 43
88
+
#define SLAVE_USB3 44
89
+
#define SLAVE_VENUS_CFG 45
90
+
#define SLAVE_VENUS_CVP_THROTTLE_CFG 46
91
+
#define SLAVE_VENUS_THROTTLE_CFG 47
92
+
#define SLAVE_VSENSE_CTRL_CFG 48
93
+
#define SLAVE_CNOC_A2NOC 49
94
+
#define SLAVE_SERVICE_CNOC 50
95
+
96
+
#define MASTER_CNOC_DC_NOC 0
97
+
#define SLAVE_GEM_NOC_CFG 1
98
+
#define SLAVE_LLCC_CFG 2
99
+
100
+
#define MASTER_AMPSS_M0 0
101
+
#define MASTER_SYS_TCU 1
102
+
#define MASTER_GEM_NOC_CFG 2
103
+
#define MASTER_COMPUTE_NOC 3
104
+
#define MASTER_MNOC_HF_MEM_NOC 4
105
+
#define MASTER_MNOC_SF_MEM_NOC 5
106
+
#define MASTER_GEM_NOC_PCIE_SNOC 6
107
+
#define MASTER_SNOC_GC_MEM_NOC 7
108
+
#define MASTER_SNOC_SF_MEM_NOC 8
109
+
#define MASTER_GRAPHICS_3D 9
110
+
#define SLAVE_MSS_PROC_MS_MPU_CFG 10
111
+
#define SLAVE_GEM_NOC_SNOC 11
112
+
#define SLAVE_LLCC 12
113
+
#define SLAVE_SERVICE_GEM_NOC 13
114
+
115
+
116
+
#define MASTER_LLCC 0
117
+
#define SLAVE_EBI_CH0 1
118
+
119
+
#define MASTER_CNOC_MNOC_CFG 0
120
+
#define MASTER_CAMNOC_HF0 1
121
+
#define MASTER_CAMNOC_NRT 2
122
+
#define MASTER_CAMNOC_RT 3
123
+
#define MASTER_CAMNOC_SF 4
124
+
#define MASTER_MDP_PORT0 5
125
+
#define MASTER_MDP_PORT1 6
126
+
#define MASTER_ROTATOR 7
127
+
#define MASTER_VIDEO_P0 8
128
+
#define MASTER_VIDEO_P1 9
129
+
#define MASTER_VIDEO_PROC 10
130
+
#define SLAVE_MNOC_SF_MEM_NOC 11
131
+
#define SLAVE_MNOC_HF_MEM_NOC 12
132
+
#define SLAVE_SERVICE_MNOC 13
133
+
134
+
#define MASTER_SNOC_CFG 0
135
+
#define A1NOC_SNOC_MAS 1
136
+
#define A2NOC_SNOC_MAS 2
137
+
#define MASTER_GEM_NOC_SNOC 3
138
+
#define MASTER_PIMEM 4
139
+
#define MASTER_GIC 5
140
+
#define SLAVE_APPSS 6
141
+
#define SNOC_CNOC_SLV 7
142
+
#define SLAVE_SNOC_GEM_NOC_GC 8
143
+
#define SLAVE_SNOC_GEM_NOC_SF 9
144
+
#define SLAVE_OCIMEM 10
145
+
#define SLAVE_PIMEM 11
146
+
#define SLAVE_SERVICE_SNOC 12
147
+
#define SLAVE_QDSS_STM 13
148
+
#define SLAVE_TCU 14
149
+
150
+
#endif
-24
include/dt-bindings/interconnect/qcom,x1e80100-rpmh.h
-24
include/dt-bindings/interconnect/qcom,x1e80100-rpmh.h
···
112
112
#define SLAVE_GEM_NOC_CNOC 12
113
113
#define SLAVE_LLCC 13
114
114
#define SLAVE_MEM_NOC_PCIE_SNOC 14
115
-
#define MASTER_MNOC_HF_MEM_NOC_DISP 15
116
-
#define MASTER_ANOC_PCIE_GEM_NOC_DISP 16
117
-
#define SLAVE_LLCC_DISP 17
118
-
#define MASTER_ANOC_PCIE_GEM_NOC_PCIE 18
119
-
#define SLAVE_LLCC_PCIE 19
120
115
121
116
#define MASTER_LPIAON_NOC 0
122
117
#define SLAVE_LPASS_GEM_NOC 1
···
124
129
125
130
#define MASTER_LLCC 0
126
131
#define SLAVE_EBI1 1
127
-
#define MASTER_LLCC_DISP 2
128
-
#define SLAVE_EBI1_DISP 3
129
-
#define MASTER_LLCC_PCIE 4
130
-
#define SLAVE_EBI1_PCIE 5
131
132
132
133
#define MASTER_AV1_ENC 0
133
134
#define MASTER_CAMNOC_HF 1
···
138
147
#define SLAVE_MNOC_HF_MEM_NOC 10
139
148
#define SLAVE_MNOC_SF_MEM_NOC 11
140
149
#define SLAVE_SERVICE_MNOC 12
141
-
#define MASTER_MDP_DISP 13
142
-
#define SLAVE_MNOC_HF_MEM_NOC_DISP 14
143
150
144
151
#define MASTER_CDSP_PROC 0
145
152
#define SLAVE_CDSP_MEM_NOC 1
···
145
156
#define MASTER_PCIE_NORTH 0
146
157
#define MASTER_PCIE_SOUTH 1
147
158
#define SLAVE_ANOC_PCIE_GEM_NOC 2
148
-
#define MASTER_PCIE_NORTH_PCIE 3
149
-
#define MASTER_PCIE_SOUTH_PCIE 4
150
-
#define SLAVE_ANOC_PCIE_GEM_NOC_PCIE 5
151
159
152
160
#define MASTER_PCIE_3 0
153
161
#define MASTER_PCIE_4 1
154
162
#define MASTER_PCIE_5 2
155
163
#define SLAVE_PCIE_NORTH 3
156
-
#define MASTER_PCIE_3_PCIE 4
157
-
#define MASTER_PCIE_4_PCIE 5
158
-
#define MASTER_PCIE_5_PCIE 6
159
-
#define SLAVE_PCIE_NORTH_PCIE 7
160
164
161
165
#define MASTER_PCIE_0 0
162
166
#define MASTER_PCIE_1 1
···
157
175
#define MASTER_PCIE_6A 3
158
176
#define MASTER_PCIE_6B 4
159
177
#define SLAVE_PCIE_SOUTH 5
160
-
#define MASTER_PCIE_0_PCIE 6
161
-
#define MASTER_PCIE_1_PCIE 7
162
-
#define MASTER_PCIE_2_PCIE 8
163
-
#define MASTER_PCIE_6A_PCIE 9
164
-
#define MASTER_PCIE_6B_PCIE 10
165
-
#define SLAVE_PCIE_SOUTH_PCIE 11
166
178
167
179
#define MASTER_A1NOC_SNOC 0
168
180
#define MASTER_A2NOC_SNOC 1
+6
-5
include/linux/interconnect-provider.h
+6
-5
include/linux/interconnect-provider.h
···
36
36
struct icc_node *nodes[] __counted_by(num_nodes);
37
37
};
38
38
39
-
struct icc_node *of_icc_xlate_onecell(struct of_phandle_args *spec,
39
+
struct icc_node *of_icc_xlate_onecell(const struct of_phandle_args *spec,
40
40
void *data);
41
41
42
42
/**
···
65
65
u32 peak_bw, u32 *agg_avg, u32 *agg_peak);
66
66
void (*pre_aggregate)(struct icc_node *node);
67
67
int (*get_bw)(struct icc_node *node, u32 *avg, u32 *peak);
68
-
struct icc_node* (*xlate)(struct of_phandle_args *spec, void *data);
69
-
struct icc_node_data* (*xlate_extended)(struct of_phandle_args *spec, void *data);
68
+
struct icc_node* (*xlate)(const struct of_phandle_args *spec, void *data);
69
+
struct icc_node_data* (*xlate_extended)(const struct of_phandle_args *spec,
70
+
void *data);
70
71
struct device *dev;
71
72
int users;
72
73
bool inter_set;
···
125
124
void icc_provider_init(struct icc_provider *provider);
126
125
int icc_provider_register(struct icc_provider *provider);
127
126
void icc_provider_deregister(struct icc_provider *provider);
128
-
struct icc_node_data *of_icc_get_from_provider(struct of_phandle_args *spec);
127
+
struct icc_node_data *of_icc_get_from_provider(const struct of_phandle_args *spec);
129
128
void icc_sync_state(struct device *dev);
130
129
131
130
#else
···
172
171
173
172
static inline void icc_provider_deregister(struct icc_provider *provider) { }
174
173
175
-
static inline struct icc_node_data *of_icc_get_from_provider(struct of_phandle_args *spec)
174
+
static inline struct icc_node_data *of_icc_get_from_provider(const struct of_phandle_args *spec)
176
175
{
177
176
return ERR_PTR(-ENOTSUPP);
178
177
}
+4
-3
include/soc/tegra/mc.h
+4
-3
include/soc/tegra/mc.h
···
146
146
int (*set)(struct icc_node *src, struct icc_node *dst);
147
147
int (*aggregate)(struct icc_node *node, u32 tag, u32 avg_bw,
148
148
u32 peak_bw, u32 *agg_avg, u32 *agg_peak);
149
-
struct icc_node* (*xlate)(struct of_phandle_args *spec, void *data);
150
-
struct icc_node_data *(*xlate_extended)(struct of_phandle_args *spec,
149
+
struct icc_node* (*xlate)(const struct of_phandle_args *spec, void *data);
150
+
struct icc_node_data *(*xlate_extended)(const struct of_phandle_args *spec,
151
151
void *data);
152
152
int (*get_bw)(struct icc_node *node, u32 *avg, u32 *peak);
153
153
};
154
154
155
-
struct icc_node *tegra_mc_icc_xlate(struct of_phandle_args *spec, void *data);
155
+
struct icc_node *tegra_mc_icc_xlate(const struct of_phandle_args *spec,
156
+
void *data);
156
157
extern const struct tegra_mc_icc_ops tegra_mc_icc_ops;
157
158
158
159
struct tegra_mc_ops {