r8169: simplify rtl_writephy_batch and rtl_ephy_init

Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git

kernel os linux

Make both functions macros to allow omitting the ARRAY_SIZE(x) argument.

Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com>
Signed-off-by: David S. Miller <davem@davemloft.net>

authored by

Heiner Kallweit and committed by

David S. Miller 7 years ago 1791ad50 0e5ef5a2

+52 -48

1 changed file

expand all

drivers

net

ethernet

realtek

r8169.c

+52 -48

drivers/net/ethernet/realtek/r8169.c

··· 2280 2280 u16 val; 2281 2281 }; 2282 2282 2283 - static void rtl_writephy_batch(struct rtl8169_private *tp, 2284 - const struct phy_reg *regs, int len) 2283 + static void __rtl_writephy_batch(struct rtl8169_private *tp, 2284 + const struct phy_reg *regs, int len) 2285 2285 { 2286 2286 while (len-- > 0) { 2287 2287 rtl_writephy(tp, regs->reg, regs->val); 2288 2288 regs++; 2289 2289 } 2290 2290 } 2291 + 2292 + #define rtl_writephy_batch(tp, a) __rtl_writephy_batch(tp, a, ARRAY_SIZE(a)) 2291 2293 2292 2294 #define PHY_READ 0x00000000 2293 2295 #define PHY_DATA_OR 0x10000000 ··· 2642 2640 { 0x00, 0x9200 } 2643 2641 }; 2644 2642 2645 - rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); 2643 + rtl_writephy_batch(tp, phy_reg_init); 2646 2644 } 2647 2645 2648 2646 static void rtl8169sb_hw_phy_config(struct rtl8169_private *tp) ··· 2653 2651 { 0x1f, 0x0000 } 2654 2652 }; 2655 2653 2656 - rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); 2654 + rtl_writephy_batch(tp, phy_reg_init); 2657 2655 } 2658 2656 2659 2657 static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp) ··· 2711 2709 { 0x1f, 0x0000 } 2712 2710 }; 2713 2711 2714 - rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); 2712 + rtl_writephy_batch(tp, phy_reg_init); 2715 2713 2716 2714 rtl8169scd_hw_phy_config_quirk(tp); 2717 2715 } ··· 2766 2764 { 0x1f, 0x0000 } 2767 2765 }; 2768 2766 2769 - rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); 2767 + rtl_writephy_batch(tp, phy_reg_init); 2770 2768 } 2771 2769 2772 2770 static void rtl8168bb_hw_phy_config(struct rtl8169_private *tp) ··· 2779 2777 rtl_writephy(tp, 0x1f, 0x0001); 2780 2778 rtl_patchphy(tp, 0x16, 1 << 0); 2781 2779 2782 - rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); 2780 + rtl_writephy_batch(tp, phy_reg_init); 2783 2781 } 2784 2782 2785 2783 static void rtl8168bef_hw_phy_config(struct rtl8169_private *tp) ··· 2790 2788 { 0x1f, 0x0000 } 2791 2789 }; 2792 2790 2793 - rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); 2791 + rtl_writephy_batch(tp, phy_reg_init); 2794 2792 } 2795 2793 2796 2794 static void rtl8168cp_1_hw_phy_config(struct rtl8169_private *tp) ··· 2803 2801 { 0x1f, 0x0000 } 2804 2802 }; 2805 2803 2806 - rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); 2804 + rtl_writephy_batch(tp, phy_reg_init); 2807 2805 } 2808 2806 2809 2807 static void rtl8168cp_2_hw_phy_config(struct rtl8169_private *tp) ··· 2818 2816 rtl_patchphy(tp, 0x14, 1 << 5); 2819 2817 rtl_patchphy(tp, 0x0d, 1 << 5); 2820 2818 2821 - rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); 2819 + rtl_writephy_batch(tp, phy_reg_init); 2822 2820 } 2823 2821 2824 2822 static void rtl8168c_1_hw_phy_config(struct rtl8169_private *tp) ··· 2843 2841 { 0x09, 0x0000 } 2844 2842 }; 2845 2843 2846 - rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); 2844 + rtl_writephy_batch(tp, phy_reg_init); 2847 2845 2848 2846 rtl_patchphy(tp, 0x14, 1 << 5); 2849 2847 rtl_patchphy(tp, 0x0d, 1 << 5); ··· 2870 2868 { 0x1f, 0x0000 } 2871 2869 }; 2872 2870 2873 - rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); 2871 + rtl_writephy_batch(tp, phy_reg_init); 2874 2872 2875 2873 rtl_patchphy(tp, 0x16, 1 << 0); 2876 2874 rtl_patchphy(tp, 0x14, 1 << 5); ··· 2892 2890 { 0x1f, 0x0000 } 2893 2891 }; 2894 2892 2895 - rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); 2893 + rtl_writephy_batch(tp, phy_reg_init); 2896 2894 2897 2895 rtl_patchphy(tp, 0x16, 1 << 0); 2898 2896 rtl_patchphy(tp, 0x14, 1 << 5); ··· 2948 2946 { 0x0d, 0xf880 } 2949 2947 }; 2950 2948 2951 - rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0)); 2949 + rtl_writephy_batch(tp, phy_reg_init_0); 2952 2950 2953 2951 /* 2954 2952 * Rx Error Issue ··· 2969 2967 }; 2970 2968 int val; 2971 2969 2972 - rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); 2970 + rtl_writephy_batch(tp, phy_reg_init); 2973 2971 2974 2972 val = rtl_readphy(tp, 0x0d); 2975 2973 ··· 2995 2993 { 0x06, 0x6662 } 2996 2994 }; 2997 2995 2998 - rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); 2996 + rtl_writephy_batch(tp, phy_reg_init); 2999 2997 } 3000 2998 3001 2999 /* RSET couple improve */ ··· 3059 3057 { 0x0d, 0xf880 } 3060 3058 }; 3061 3059 3062 - rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0)); 3060 + rtl_writephy_batch(tp, phy_reg_init_0); 3063 3061 3064 3062 if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) { 3065 3063 static const struct phy_reg phy_reg_init[] = { ··· 3073 3071 }; 3074 3072 int val; 3075 3073 3076 - rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); 3074 + rtl_writephy_batch(tp, phy_reg_init); 3077 3075 3078 3076 val = rtl_readphy(tp, 0x0d); 3079 3077 if ((val & 0x00ff) != 0x006c) { ··· 3098 3096 { 0x06, 0x2642 } 3099 3097 }; 3100 3098 3101 - rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); 3099 + rtl_writephy_batch(tp, phy_reg_init); 3102 3100 } 3103 3101 3104 3102 /* Fine tune PLL performance */ ··· 3176 3174 { 0x1f, 0x0000 } 3177 3175 }; 3178 3176 3179 - rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); 3177 + rtl_writephy_batch(tp, phy_reg_init); 3180 3178 } 3181 3179 3182 3180 static void rtl8168d_4_hw_phy_config(struct rtl8169_private *tp) ··· 3191 3189 { 0x1f, 0x0000 } 3192 3190 }; 3193 3191 3194 - rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); 3192 + rtl_writephy_batch(tp, phy_reg_init); 3195 3193 rtl_patchphy(tp, 0x0d, 1 << 5); 3196 3194 } 3197 3195 ··· 3227 3225 3228 3226 rtl_apply_firmware(tp); 3229 3227 3230 - rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); 3228 + rtl_writephy_batch(tp, phy_reg_init); 3231 3229 3232 3230 /* DCO enable for 10M IDLE Power */ 3233 3231 rtl_writephy(tp, 0x1f, 0x0007); ··· 3313 3311 3314 3312 rtl_apply_firmware(tp); 3315 3313 3316 - rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); 3314 + rtl_writephy_batch(tp, phy_reg_init); 3317 3315 3318 3316 /* For 4-corner performance improve */ 3319 3317 rtl_writephy(tp, 0x1f, 0x0005); ··· 3422 3420 3423 3421 rtl_apply_firmware(tp); 3424 3422 3425 - rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); 3423 + rtl_writephy_batch(tp, phy_reg_init); 3426 3424 3427 3425 rtl8168f_hw_phy_config(tp); 3428 3426 ··· 3488 3486 rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000); 3489 3487 rtl_writephy(tp, 0x1f, 0x0000); 3490 3488 3491 - rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); 3489 + rtl_writephy_batch(tp, phy_reg_init); 3492 3490 3493 3491 /* Modify green table for giga */ 3494 3492 rtl_writephy(tp, 0x1f, 0x0005); ··· 3908 3906 rtl_patchphy(tp, 0x19, 1 << 13); 3909 3907 rtl_patchphy(tp, 0x10, 1 << 15); 3910 3908 3911 - rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); 3909 + rtl_writephy_batch(tp, phy_reg_init); 3912 3910 } 3913 3911 3914 3912 static void rtl8105e_hw_phy_config(struct rtl8169_private *tp) ··· 3934 3932 3935 3933 rtl_apply_firmware(tp); 3936 3934 3937 - rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); 3935 + rtl_writephy_batch(tp, phy_reg_init); 3938 3936 } 3939 3937 3940 3938 static void rtl8402_hw_phy_config(struct rtl8169_private *tp) ··· 3971 3969 rtl_apply_firmware(tp); 3972 3970 3973 3971 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000); 3974 - rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); 3972 + rtl_writephy_batch(tp, phy_reg_init); 3975 3973 3976 3974 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000); 3977 3975 } ··· 4707 4705 u16 bits; 4708 4706 }; 4709 4707 4710 - static void rtl_ephy_init(struct rtl8169_private *tp, const struct ephy_info *e, 4711 - int len) 4708 + static void __rtl_ephy_init(struct rtl8169_private *tp, 4709 + const struct ephy_info *e, int len) 4712 4710 { 4713 4711 u16 w; 4714 4712 ··· 4718 4716 e++; 4719 4717 } 4720 4718 } 4719 + 4720 + #define rtl_ephy_init(tp, a) __rtl_ephy_init(tp, a, ARRAY_SIZE(a)) 4721 4721 4722 4722 static void rtl_disable_clock_request(struct rtl8169_private *tp) 4723 4723 { ··· 4801 4797 4802 4798 rtl_set_def_aspm_entry_latency(tp); 4803 4799 4804 - rtl_ephy_init(tp, e_info_8168cp, ARRAY_SIZE(e_info_8168cp)); 4800 + rtl_ephy_init(tp, e_info_8168cp); 4805 4801 4806 4802 __rtl_hw_start_8168cp(tp); 4807 4803 } ··· 4849 4845 4850 4846 RTL_W8(tp, DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2); 4851 4847 4852 - rtl_ephy_init(tp, e_info_8168c_1, ARRAY_SIZE(e_info_8168c_1)); 4848 + rtl_ephy_init(tp, e_info_8168c_1); 4853 4849 4854 4850 __rtl_hw_start_8168cp(tp); 4855 4851 } ··· 4863 4859 4864 4860 rtl_set_def_aspm_entry_latency(tp); 4865 4861 4866 - rtl_ephy_init(tp, e_info_8168c_2, ARRAY_SIZE(e_info_8168c_2)); 4862 + rtl_ephy_init(tp, e_info_8168c_2); 4867 4863 4868 4864 __rtl_hw_start_8168cp(tp); 4869 4865 } ··· 4921 4917 4922 4918 RTL_W8(tp, MaxTxPacketSize, TxPacketMax); 4923 4919 4924 - rtl_ephy_init(tp, e_info_8168d_4, ARRAY_SIZE(e_info_8168d_4)); 4920 + rtl_ephy_init(tp, e_info_8168d_4); 4925 4921 4926 4922 rtl_enable_clock_request(tp); 4927 4923 } ··· 4946 4942 4947 4943 rtl_set_def_aspm_entry_latency(tp); 4948 4944 4949 - rtl_ephy_init(tp, e_info_8168e_1, ARRAY_SIZE(e_info_8168e_1)); 4945 + rtl_ephy_init(tp, e_info_8168e_1); 4950 4946 4951 4947 if (tp->dev->mtu <= ETH_DATA_LEN) 4952 4948 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B); ··· 4971 4967 4972 4968 rtl_set_def_aspm_entry_latency(tp); 4973 4969 4974 - rtl_ephy_init(tp, e_info_8168e_2, ARRAY_SIZE(e_info_8168e_2)); 4970 + rtl_ephy_init(tp, e_info_8168e_2); 4975 4971 4976 4972 if (tp->dev->mtu <= ETH_DATA_LEN) 4977 4973 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B); ··· 5042 5038 5043 5039 rtl_hw_start_8168f(tp); 5044 5040 5045 - rtl_ephy_init(tp, e_info_8168f_1, ARRAY_SIZE(e_info_8168f_1)); 5041 + rtl_ephy_init(tp, e_info_8168f_1); 5046 5042 5047 5043 rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00); 5048 5044 ··· 5062 5058 rtl_hw_start_8168f(tp); 5063 5059 rtl_pcie_state_l2l3_disable(tp); 5064 5060 5065 - rtl_ephy_init(tp, e_info_8168f_1, ARRAY_SIZE(e_info_8168f_1)); 5061 + rtl_ephy_init(tp, e_info_8168f_1); 5066 5062 5067 5063 rtl_eri_set_bits(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00); 5068 5064 } ··· 5111 5107 5112 5108 /* disable aspm and clock request before access ephy */ 5113 5109 rtl_hw_aspm_clkreq_enable(tp, false); 5114 - rtl_ephy_init(tp, e_info_8168g_1, ARRAY_SIZE(e_info_8168g_1)); 5110 + rtl_ephy_init(tp, e_info_8168g_1); 5115 5111 rtl_hw_aspm_clkreq_enable(tp, true); 5116 5112 } 5117 5113 ··· 5129 5125 /* disable aspm and clock request before access ephy */ 5130 5126 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~ClkReqEn); 5131 5127 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~ASPM_en); 5132 - rtl_ephy_init(tp, e_info_8168g_2, ARRAY_SIZE(e_info_8168g_2)); 5128 + rtl_ephy_init(tp, e_info_8168g_2); 5133 5129 } 5134 5130 5135 5131 static void rtl_hw_start_8411_2(struct rtl8169_private *tp) ··· 5146 5142 5147 5143 /* disable aspm and clock request before access ephy */ 5148 5144 rtl_hw_aspm_clkreq_enable(tp, false); 5149 - rtl_ephy_init(tp, e_info_8411_2, ARRAY_SIZE(e_info_8411_2)); 5145 + rtl_ephy_init(tp, e_info_8411_2); 5150 5146 rtl_hw_aspm_clkreq_enable(tp, true); 5151 5147 } 5152 5148 ··· 5165 5161 5166 5162 /* disable aspm and clock request before access ephy */ 5167 5163 rtl_hw_aspm_clkreq_enable(tp, false); 5168 - rtl_ephy_init(tp, e_info_8168h_1, ARRAY_SIZE(e_info_8168h_1)); 5164 + rtl_ephy_init(tp, e_info_8168h_1); 5169 5165 5170 5166 rtl_eri_write(tp, 0xc8, ERIAR_MASK_0101, 0x00080002); 5171 5167 rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, 0x38); ··· 5295 5291 5296 5292 /* disable aspm and clock request before access ephy */ 5297 5293 rtl_hw_aspm_clkreq_enable(tp, false); 5298 - rtl_ephy_init(tp, e_info_8168ep_1, ARRAY_SIZE(e_info_8168ep_1)); 5294 + rtl_ephy_init(tp, e_info_8168ep_1); 5299 5295 5300 5296 rtl_hw_start_8168ep(tp); 5301 5297 ··· 5312 5308 5313 5309 /* disable aspm and clock request before access ephy */ 5314 5310 rtl_hw_aspm_clkreq_enable(tp, false); 5315 - rtl_ephy_init(tp, e_info_8168ep_2, ARRAY_SIZE(e_info_8168ep_2)); 5311 + rtl_ephy_init(tp, e_info_8168ep_2); 5316 5312 5317 5313 rtl_hw_start_8168ep(tp); 5318 5314 ··· 5334 5330 5335 5331 /* disable aspm and clock request before access ephy */ 5336 5332 rtl_hw_aspm_clkreq_enable(tp, false); 5337 - rtl_ephy_init(tp, e_info_8168ep_3, ARRAY_SIZE(e_info_8168ep_3)); 5333 + rtl_ephy_init(tp, e_info_8168ep_3); 5338 5334 5339 5335 rtl_hw_start_8168ep(tp); 5340 5336 ··· 5385 5381 if ((cfg1 & LEDS0) && (cfg1 & LEDS1)) 5386 5382 RTL_W8(tp, Config1, cfg1 & ~LEDS0); 5387 5383 5388 - rtl_ephy_init(tp, e_info_8102e_1, ARRAY_SIZE(e_info_8102e_1)); 5384 + rtl_ephy_init(tp, e_info_8102e_1); 5389 5385 } 5390 5386 5391 5387 static void rtl_hw_start_8102e_2(struct rtl8169_private *tp) ··· 5427 5423 RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET); 5428 5424 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN); 5429 5425 5430 - rtl_ephy_init(tp, e_info_8105e_1, ARRAY_SIZE(e_info_8105e_1)); 5426 + rtl_ephy_init(tp, e_info_8105e_1); 5431 5427 5432 5428 rtl_pcie_state_l2l3_disable(tp); 5433 5429 } ··· 5452 5448 5453 5449 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); 5454 5450 5455 - rtl_ephy_init(tp, e_info_8402, ARRAY_SIZE(e_info_8402)); 5451 + rtl_ephy_init(tp, e_info_8402); 5456 5452 5457 5453 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B); 5458 5454