tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'soundwire-streaming' of git://git.kernel.org/pub/scm/linux/kernel/git/vkoul/soundwire into char-misc-next
Vinod writes:
soundwire streaming
This contains:
- Support for SoundWire Streaming
- Documentation updates for streaming
- Cadence and Intel driver updates for streaming
- ASoC API for programming soundwire stream
+3634
-15
+65
Documentation/driver-api/soundwire/error_handling.rst
+65
Documentation/driver-api/soundwire/error_handling.rst
···
1
+
========================
2
+
SoundWire Error Handling
3
+
========================
4
+
5
+
The SoundWire PHY was designed with care and errors on the bus are going to
6
+
be very unlikely, and if they happen it should be limited to single bit
7
+
errors. Examples of this design can be found in the synchronization
8
+
mechanism (sync loss after two errors) and short CRCs used for the Bulk
9
+
Register Access.
10
+
11
+
The errors can be detected with multiple mechanisms:
12
+
13
+
1. Bus clash or parity errors: This mechanism relies on low-level detectors
14
+
that are independent of the payload and usages, and they cover both control
15
+
and audio data. The current implementation only logs such errors.
16
+
Improvements could be invalidating an entire programming sequence and
17
+
restarting from a known position. In the case of such errors outside of a
18
+
control/command sequence, there is no concealment or recovery for audio
19
+
data enabled by the SoundWire protocol, the location of the error will also
20
+
impact its audibility (most-significant bits will be more impacted in PCM),
21
+
and after a number of such errors are detected the bus might be reset. Note
22
+
that bus clashes due to programming errors (two streams using the same bit
23
+
slots) or electrical issues during the transmit/receive transition cannot
24
+
be distinguished, although a recurring bus clash when audio is enabled is a
25
+
indication of a bus allocation issue. The interrupt mechanism can also help
26
+
identify Slaves which detected a Bus Clash or a Parity Error, but they may
27
+
not be responsible for the errors so resetting them individually is not a
28
+
viable recovery strategy.
29
+
30
+
2. Command status: Each command is associated with a status, which only
31
+
covers transmission of the data between devices. The ACK status indicates
32
+
that the command was received and will be executed by the end of the
33
+
current frame. A NAK indicates that the command was in error and will not
34
+
be applied. In case of a bad programming (command sent to non-existent
35
+
Slave or to a non-implemented register) or electrical issue, no response
36
+
signals the command was ignored. Some Master implementations allow for a
37
+
command to be retransmitted several times. If the retransmission fails,
38
+
backtracking and restarting the entire programming sequence might be a
39
+
solution. Alternatively some implementations might directly issue a bus
40
+
reset and re-enumerate all devices.
41
+
42
+
3. Timeouts: In a number of cases such as ChannelPrepare or
43
+
ClockStopPrepare, the bus driver is supposed to poll a register field until
44
+
it transitions to a NotFinished value of zero. The MIPI SoundWire spec 1.1
45
+
does not define timeouts but the MIPI SoundWire DisCo document adds
46
+
recommendation on timeouts. If such configurations do not complete, the
47
+
driver will return a -ETIMEOUT. Such timeouts are symptoms of a faulty
48
+
Slave device and are likely impossible to recover from.
49
+
50
+
Errors during global reconfiguration sequences are extremely difficult to
51
+
handle:
52
+
53
+
1. BankSwitch: An error during the last command issuing a BankSwitch is
54
+
difficult to backtrack from. Retransmitting the Bank Switch command may be
55
+
possible in a single segment setup, but this can lead to synchronization
56
+
problems when enabling multiple bus segments (a command with side effects
57
+
such as frame reconfiguration would be handled at different times). A global
58
+
hard-reset might be the best solution.
59
+
60
+
Note that SoundWire does not provide a mechanism to detect illegal values
61
+
written in valid registers. In a number of cases the standard even mentions
62
+
that the Slave might behave in implementation-defined ways. The bus
63
+
implementation does not provide a recovery mechanism for such errors, Slave
64
+
or Master driver implementers are responsible for writing valid values in
65
+
valid registers and implement additional range checking if needed.
+3
Documentation/driver-api/soundwire/index.rst
+3
Documentation/driver-api/soundwire/index.rst
+106
Documentation/driver-api/soundwire/locking.rst
+106
Documentation/driver-api/soundwire/locking.rst
···
1
+
=================
2
+
SoundWire Locking
3
+
=================
4
+
5
+
This document explains locking mechanism of the SoundWire Bus. Bus uses
6
+
following locks in order to avoid race conditions in Bus operations on
7
+
shared resources.
8
+
9
+
- Bus lock
10
+
11
+
- Message lock
12
+
13
+
Bus lock
14
+
========
15
+
16
+
SoundWire Bus lock is a mutex and is part of Bus data structure
17
+
(sdw_bus) which is used for every Bus instance. This lock is used to
18
+
serialize each of the following operations(s) within SoundWire Bus instance.
19
+
20
+
- Addition and removal of Slave(s), changing Slave status.
21
+
22
+
- Prepare, Enable, Disable and De-prepare stream operations.
23
+
24
+
- Access of Stream data structure.
25
+
26
+
Message lock
27
+
============
28
+
29
+
SoundWire message transfer lock. This mutex is part of
30
+
Bus data structure (sdw_bus). This lock is used to serialize the message
31
+
transfers (read/write) within a SoundWire Bus instance.
32
+
33
+
Below examples show how locks are acquired.
34
+
35
+
Example 1
36
+
---------
37
+
38
+
Message transfer.
39
+
40
+
1. For every message transfer
41
+
42
+
a. Acquire Message lock.
43
+
44
+
b. Transfer message (Read/Write) to Slave1 or broadcast message on
45
+
Bus in case of bank switch.
46
+
47
+
c. Release Message lock ::
48
+
49
+
+----------+ +---------+
50
+
| | | |
51
+
| Bus | | Master |
52
+
| | | Driver |
53
+
| | | |
54
+
+----+-----+ +----+----+
55
+
| |
56
+
| bus->ops->xfer_msg() |
57
+
<-------------------------------+ a. Acquire Message lock
58
+
| | b. Transfer message
59
+
| |
60
+
+-------------------------------> c. Release Message lock
61
+
| return success/error | d. Return success/error
62
+
| |
63
+
+ +
64
+
65
+
Example 2
66
+
---------
67
+
68
+
Prepare operation.
69
+
70
+
1. Acquire lock for Bus instance associated with Master 1.
71
+
72
+
2. For every message transfer in Prepare operation
73
+
74
+
a. Acquire Message lock.
75
+
76
+
b. Transfer message (Read/Write) to Slave1 or broadcast message on
77
+
Bus in case of bank switch.
78
+
79
+
c. Release Message lock.
80
+
81
+
3. Release lock for Bus instance associated with Master 1 ::
82
+
83
+
+----------+ +---------+
84
+
| | | |
85
+
| Bus | | Master |
86
+
| | | Driver |
87
+
| | | |
88
+
+----+-----+ +----+----+
89
+
| |
90
+
| sdw_prepare_stream() |
91
+
<-------------------------------+ 1. Acquire bus lock
92
+
| | 2. Perform stream prepare
93
+
| |
94
+
| |
95
+
| bus->ops->xfer_msg() |
96
+
<-------------------------------+ a. Acquire Message lock
97
+
| | b. Transfer message
98
+
| |
99
+
+-------------------------------> c. Release Message lock
100
+
| return success/error | d. Return success/error
101
+
| |
102
+
| |
103
+
| return success/error | 3. Release bus lock
104
+
+-------------------------------> 4. Return success/error
105
+
| |
106
+
+ +
+372
Documentation/driver-api/soundwire/stream.rst
+372
Documentation/driver-api/soundwire/stream.rst
···
1
+
=========================
2
+
Audio Stream in SoundWire
3
+
=========================
4
+
5
+
An audio stream is a logical or virtual connection created between
6
+
7
+
(1) System memory buffer(s) and Codec(s)
8
+
9
+
(2) DSP memory buffer(s) and Codec(s)
10
+
11
+
(3) FIFO(s) and Codec(s)
12
+
13
+
(4) Codec(s) and Codec(s)
14
+
15
+
which is typically driven by a DMA(s) channel through the data link. An
16
+
audio stream contains one or more channels of data. All channels within
17
+
stream must have same sample rate and same sample size.
18
+
19
+
Assume a stream with two channels (Left & Right) is opened using SoundWire
20
+
interface. Below are some ways a stream can be represented in SoundWire.
21
+
22
+
Stream Sample in memory (System memory, DSP memory or FIFOs) ::
23
+
24
+
-------------------------
25
+
| L | R | L | R | L | R |
26
+
-------------------------
27
+
28
+
Example 1: Stereo Stream with L and R channels is rendered from Master to
29
+
Slave. Both Master and Slave is using single port. ::
30
+
31
+
+---------------+ Clock Signal +---------------+
32
+
| Master +----------------------------------+ Slave |
33
+
| Interface | | Interface |
34
+
| | | 1 |
35
+
| | Data Signal | |
36
+
| L + R +----------------------------------+ L + R |
37
+
| (Data) | Data Direction | (Data) |
38
+
+---------------+ +-----------------------> +---------------+
39
+
40
+
41
+
Example 2: Stereo Stream with L and R channels is captured from Slave to
42
+
Master. Both Master and Slave is using single port. ::
43
+
44
+
45
+
+---------------+ Clock Signal +---------------+
46
+
| Master +----------------------------------+ Slave |
47
+
| Interface | | Interface |
48
+
| | | 1 |
49
+
| | Data Signal | |
50
+
| L + R +----------------------------------+ L + R |
51
+
| (Data) | Data Direction | (Data) |
52
+
+---------------+ <-----------------------+ +---------------+
53
+
54
+
55
+
Example 3: Stereo Stream with L and R channels is rendered by Master. Each
56
+
of the L and R channel is received by two different Slaves. Master and both
57
+
Slaves are using single port. ::
58
+
59
+
+---------------+ Clock Signal +---------------+
60
+
| Master +---------+------------------------+ Slave |
61
+
| Interface | | | Interface |
62
+
| | | | 1 |
63
+
| | | Data Signal | |
64
+
| L + R +---+------------------------------+ L |
65
+
| (Data) | | | Data Direction | (Data) |
66
+
+---------------+ | | +-------------> +---------------+
67
+
| |
68
+
| |
69
+
| | +---------------+
70
+
| +----------------------> | Slave |
71
+
| | Interface |
72
+
| | 2 |
73
+
| | |
74
+
+----------------------------> | R |
75
+
| (Data) |
76
+
+---------------+
77
+
78
+
79
+
Example 4: Stereo Stream with L and R channel is rendered by two different
80
+
Ports of the Master and is received by only single Port of the Slave
81
+
interface. ::
82
+
83
+
+--------------------+
84
+
| |
85
+
| +--------------+ +----------------+
86
+
| | || | |
87
+
| | Data Port || L Channel | |
88
+
| | 1 |------------+ | |
89
+
| | L Channel || | +-----+----+ |
90
+
| | (Data) || | L + R Channel || Data | |
91
+
| Master +----------+ | +---+---------> || Port | |
92
+
| Interface | | || 1 | |
93
+
| +--------------+ | || | |
94
+
| | || | +----------+ |
95
+
| | Data Port |------------+ | |
96
+
| | 2 || R Channel | Slave |
97
+
| | R Channel || | Interface |
98
+
| | (Data) || | 1 |
99
+
| +--------------+ Clock Signal | L + R |
100
+
| +---------------------------> | (Data) |
101
+
+--------------------+ | |
102
+
+----------------+
103
+
104
+
SoundWire Stream Management flow
105
+
================================
106
+
107
+
Stream definitions
108
+
------------------
109
+
110
+
(1) Current stream: This is classified as the stream on which operation has
111
+
to be performed like prepare, enable, disable, de-prepare etc.
112
+
113
+
(2) Active stream: This is classified as the stream which is already active
114
+
on Bus other than current stream. There can be multiple active streams
115
+
on the Bus.
116
+
117
+
SoundWire Bus manages stream operations for each stream getting
118
+
rendered/captured on the SoundWire Bus. This section explains Bus operations
119
+
done for each of the stream allocated/released on Bus. Following are the
120
+
stream states maintained by the Bus for each of the audio stream.
121
+
122
+
123
+
SoundWire stream states
124
+
-----------------------
125
+
126
+
Below shows the SoundWire stream states and state transition diagram. ::
127
+
128
+
+-----------+ +------------+ +----------+ +----------+
129
+
| ALLOCATED +---->| CONFIGURED +---->| PREPARED +---->| ENABLED |
130
+
| STATE | | STATE | | STATE | | STATE |
131
+
+-----------+ +------------+ +----------+ +----+-----+
132
+
^
133
+
|
134
+
|
135
+
v
136
+
+----------+ +------------+ +----+-----+
137
+
| RELEASED |<----------+ DEPREPARED |<-------+ DISABLED |
138
+
| STATE | | STATE | | STATE |
139
+
+----------+ +------------+ +----------+
140
+
141
+
NOTE: State transition between prepare and deprepare is supported in Spec
142
+
but not in the software (subsystem)
143
+
144
+
NOTE2: Stream state transition checks need to be handled by caller
145
+
framework, for example ALSA/ASoC. No checks for stream transition exist in
146
+
SoundWire subsystem.
147
+
148
+
Stream State Operations
149
+
-----------------------
150
+
151
+
Below section explains the operations done by the Bus on Master(s) and
152
+
Slave(s) as part of stream state transitions.
153
+
154
+
SDW_STREAM_ALLOCATED
155
+
~~~~~~~~~~~~~~~~~~~~
156
+
157
+
Allocation state for stream. This is the entry state
158
+
of the stream. Operations performed before entering in this state:
159
+
160
+
(1) A stream runtime is allocated for the stream. This stream
161
+
runtime is used as a reference for all the operations performed
162
+
on the stream.
163
+
164
+
(2) The resources required for holding stream runtime information are
165
+
allocated and initialized. This holds all stream related information
166
+
such as stream type (PCM/PDM) and parameters, Master and Slave
167
+
interface associated with the stream, stream state etc.
168
+
169
+
After all above operations are successful, stream state is set to
170
+
``SDW_STREAM_ALLOCATED``.
171
+
172
+
Bus implements below API for allocate a stream which needs to be called once
173
+
per stream. From ASoC DPCM framework, this stream state maybe linked to
174
+
.startup() operation.
175
+
176
+
.. code-block:: c
177
+
int sdw_alloc_stream(char * stream_name);
178
+
179
+
180
+
SDW_STREAM_CONFIGURED
181
+
~~~~~~~~~~~~~~~~~~~~~
182
+
183
+
Configuration state of stream. Operations performed before entering in
184
+
this state:
185
+
186
+
(1) The resources allocated for stream information in SDW_STREAM_ALLOCATED
187
+
state are updated here. This includes stream parameters, Master(s)
188
+
and Slave(s) runtime information associated with current stream.
189
+
190
+
(2) All the Master(s) and Slave(s) associated with current stream provide
191
+
the port information to Bus which includes port numbers allocated by
192
+
Master(s) and Slave(s) for current stream and their channel mask.
193
+
194
+
After all above operations are successful, stream state is set to
195
+
``SDW_STREAM_CONFIGURED``.
196
+
197
+
Bus implements below APIs for CONFIG state which needs to be called by
198
+
the respective Master(s) and Slave(s) associated with stream. These APIs can
199
+
only be invoked once by respective Master(s) and Slave(s). From ASoC DPCM
200
+
framework, this stream state is linked to .hw_params() operation.
201
+
202
+
.. code-block:: c
203
+
int sdw_stream_add_master(struct sdw_bus * bus,
204
+
struct sdw_stream_config * stream_config,
205
+
struct sdw_ports_config * ports_config,
206
+
struct sdw_stream_runtime * stream);
207
+
208
+
int sdw_stream_add_slave(struct sdw_slave * slave,
209
+
struct sdw_stream_config * stream_config,
210
+
struct sdw_ports_config * ports_config,
211
+
struct sdw_stream_runtime * stream);
212
+
213
+
214
+
SDW_STREAM_PREPARED
215
+
~~~~~~~~~~~~~~~~~~~
216
+
217
+
Prepare state of stream. Operations performed before entering in this state:
218
+
219
+
(1) Bus parameters such as bandwidth, frame shape, clock frequency,
220
+
are computed based on current stream as well as already active
221
+
stream(s) on Bus. Re-computation is required to accommodate current
222
+
stream on the Bus.
223
+
224
+
(2) Transport and port parameters of all Master(s) and Slave(s) port(s) are
225
+
computed for the current as well as already active stream based on frame
226
+
shape and clock frequency computed in step 1.
227
+
228
+
(3) Computed Bus and transport parameters are programmed in Master(s) and
229
+
Slave(s) registers. The banked registers programming is done on the
230
+
alternate bank (bank currently unused). Port(s) are enabled for the
231
+
already active stream(s) on the alternate bank (bank currently unused).
232
+
This is done in order to not disrupt already active stream(s).
233
+
234
+
(4) Once all the values are programmed, Bus initiates switch to alternate
235
+
bank where all new values programmed gets into effect.
236
+
237
+
(5) Ports of Master(s) and Slave(s) for current stream are prepared by
238
+
programming PrepareCtrl register.
239
+
240
+
After all above operations are successful, stream state is set to
241
+
``SDW_STREAM_PREPARED``.
242
+
243
+
Bus implements below API for PREPARE state which needs to be called once per
244
+
stream. From ASoC DPCM framework, this stream state is linked to
245
+
.prepare() operation.
246
+
247
+
.. code-block:: c
248
+
int sdw_prepare_stream(struct sdw_stream_runtime * stream);
249
+
250
+
251
+
SDW_STREAM_ENABLED
252
+
~~~~~~~~~~~~~~~~~~
253
+
254
+
Enable state of stream. The data port(s) are enabled upon entering this state.
255
+
Operations performed before entering in this state:
256
+
257
+
(1) All the values computed in SDW_STREAM_PREPARED state are programmed
258
+
in alternate bank (bank currently unused). It includes programming of
259
+
already active stream(s) as well.
260
+
261
+
(2) All the Master(s) and Slave(s) port(s) for the current stream are
262
+
enabled on alternate bank (bank currently unused) by programming
263
+
ChannelEn register.
264
+
265
+
(3) Once all the values are programmed, Bus initiates switch to alternate
266
+
bank where all new values programmed gets into effect and port(s)
267
+
associated with current stream are enabled.
268
+
269
+
After all above operations are successful, stream state is set to
270
+
``SDW_STREAM_ENABLED``.
271
+
272
+
Bus implements below API for ENABLE state which needs to be called once per
273
+
stream. From ASoC DPCM framework, this stream state is linked to
274
+
.trigger() start operation.
275
+
276
+
.. code-block:: c
277
+
int sdw_enable_stream(struct sdw_stream_runtime * stream);
278
+
279
+
SDW_STREAM_DISABLED
280
+
~~~~~~~~~~~~~~~~~~~
281
+
282
+
Disable state of stream. The data port(s) are disabled upon exiting this state.
283
+
Operations performed before entering in this state:
284
+
285
+
(1) All the Master(s) and Slave(s) port(s) for the current stream are
286
+
disabled on alternate bank (bank currently unused) by programming
287
+
ChannelEn register.
288
+
289
+
(2) All the current configuration of Bus and active stream(s) are programmed
290
+
into alternate bank (bank currently unused).
291
+
292
+
(3) Once all the values are programmed, Bus initiates switch to alternate
293
+
bank where all new values programmed gets into effect and port(s) associated
294
+
with current stream are disabled.
295
+
296
+
After all above operations are successful, stream state is set to
297
+
``SDW_STREAM_DISABLED``.
298
+
299
+
Bus implements below API for DISABLED state which needs to be called once
300
+
per stream. From ASoC DPCM framework, this stream state is linked to
301
+
.trigger() stop operation.
302
+
303
+
.. code-block:: c
304
+
int sdw_disable_stream(struct sdw_stream_runtime * stream);
305
+
306
+
307
+
SDW_STREAM_DEPREPARED
308
+
~~~~~~~~~~~~~~~~~~~~~
309
+
310
+
De-prepare state of stream. Operations performed before entering in this
311
+
state:
312
+
313
+
(1) All the port(s) of Master(s) and Slave(s) for current stream are
314
+
de-prepared by programming PrepareCtrl register.
315
+
316
+
(2) The payload bandwidth of current stream is reduced from the total
317
+
bandwidth requirement of bus and new parameters calculated and
318
+
applied by performing bank switch etc.
319
+
320
+
After all above operations are successful, stream state is set to
321
+
``SDW_STREAM_DEPREPARED``.
322
+
323
+
Bus implements below API for DEPREPARED state which needs to be called once
324
+
per stream. From ASoC DPCM framework, this stream state is linked to
325
+
.trigger() stop operation.
326
+
327
+
.. code-block:: c
328
+
int sdw_deprepare_stream(struct sdw_stream_runtime * stream);
329
+
330
+
331
+
SDW_STREAM_RELEASED
332
+
~~~~~~~~~~~~~~~~~~~
333
+
334
+
Release state of stream. Operations performed before entering in this state:
335
+
336
+
(1) Release port resources for all Master(s) and Slave(s) port(s)
337
+
associated with current stream.
338
+
339
+
(2) Release Master(s) and Slave(s) runtime resources associated with
340
+
current stream.
341
+
342
+
(3) Release stream runtime resources associated with current stream.
343
+
344
+
After all above operations are successful, stream state is set to
345
+
``SDW_STREAM_RELEASED``.
346
+
347
+
Bus implements below APIs for RELEASE state which needs to be called by
348
+
all the Master(s) and Slave(s) associated with stream. From ASoC DPCM
349
+
framework, this stream state is linked to .hw_free() operation.
350
+
351
+
.. code-block:: c
352
+
int sdw_stream_remove_master(struct sdw_bus * bus,
353
+
struct sdw_stream_runtime * stream);
354
+
int sdw_stream_remove_slave(struct sdw_slave * slave,
355
+
struct sdw_stream_runtime * stream);
356
+
357
+
358
+
The .shutdown() ASoC DPCM operation calls below Bus API to release
359
+
stream assigned as part of ALLOCATED state.
360
+
361
+
In .shutdown() the data structure maintaining stream state are freed up.
362
+
363
+
.. code-block:: c
364
+
void sdw_release_stream(struct sdw_stream_runtime * stream);
365
+
366
+
Not Supported
367
+
=============
368
+
369
+
1. A single port with multiple channels supported cannot be used between two
370
+
streams or across stream. For example a port with 4 channels cannot be used
371
+
to handle 2 independent stereo streams even though it's possible in theory
372
+
in SoundWire.
+1
-1
MAINTAINERS
+1
-1
MAINTAINERS
···
13115
13115
F: sound/
13116
13116
13117
13117
SOUND - COMPRESSED AUDIO
13118
-
M: Vinod Koul <vinod.koul@intel.com>
13118
+
M: Vinod Koul <vkoul@kernel.org>
13119
13119
L: alsa-devel@alsa-project.org (moderated for non-subscribers)
13120
13120
T: git git://git.kernel.org/pub/scm/linux/kernel/git/tiwai/sound.git
13121
13121
S: Supported
+1
-1
drivers/soundwire/Kconfig
+1
-1
drivers/soundwire/Kconfig
+1
-1
drivers/soundwire/Makefile
+1
-1
drivers/soundwire/Makefile
+43
drivers/soundwire/bus.c
+43
drivers/soundwire/bus.c
···
17
17
*/
18
18
int sdw_add_bus_master(struct sdw_bus *bus)
19
19
{
20
+
struct sdw_master_prop *prop = NULL;
20
21
int ret;
21
22
22
23
if (!bus->dev) {
···
33
32
mutex_init(&bus->msg_lock);
34
33
mutex_init(&bus->bus_lock);
35
34
INIT_LIST_HEAD(&bus->slaves);
35
+
INIT_LIST_HEAD(&bus->m_rt_list);
36
36
37
37
if (bus->ops->read_prop) {
38
38
ret = bus->ops->read_prop(bus);
···
78
76
dev_err(bus->dev, "Finding slaves failed:%d\n", ret);
79
77
return ret;
80
78
}
79
+
80
+
/*
81
+
* Initialize clock values based on Master properties. The max
82
+
* frequency is read from max_freq property. Current assumption
83
+
* is that the bus will start at highest clock frequency when
84
+
* powered on.
85
+
*
86
+
* Default active bank will be 0 as out of reset the Slaves have
87
+
* to start with bank 0 (Table 40 of Spec)
88
+
*/
89
+
prop = &bus->prop;
90
+
bus->params.max_dr_freq = prop->max_freq * SDW_DOUBLE_RATE_FACTOR;
91
+
bus->params.curr_dr_freq = bus->params.max_dr_freq;
92
+
bus->params.curr_bank = SDW_BANK0;
93
+
bus->params.next_bank = SDW_BANK1;
81
94
82
95
return 0;
83
96
}
···
591
574
mutex_lock(&slave->bus->bus_lock);
592
575
slave->status = status;
593
576
mutex_unlock(&slave->bus->bus_lock);
577
+
}
578
+
579
+
int sdw_configure_dpn_intr(struct sdw_slave *slave,
580
+
int port, bool enable, int mask)
581
+
{
582
+
u32 addr;
583
+
int ret;
584
+
u8 val = 0;
585
+
586
+
addr = SDW_DPN_INTMASK(port);
587
+
588
+
/* Set/Clear port ready interrupt mask */
589
+
if (enable) {
590
+
val |= mask;
591
+
val |= SDW_DPN_INT_PORT_READY;
592
+
} else {
593
+
val &= ~(mask);
594
+
val &= ~SDW_DPN_INT_PORT_READY;
595
+
}
596
+
597
+
ret = sdw_update(slave, addr, (mask | SDW_DPN_INT_PORT_READY), val);
598
+
if (ret < 0)
599
+
dev_err(slave->bus->dev,
600
+
"SDW_DPN_INTMASK write failed:%d", val);
601
+
602
+
return ret;
594
603
}
595
604
596
605
static int sdw_initialize_slave(struct sdw_slave *slave)
+72
drivers/soundwire/bus.h
+72
drivers/soundwire/bus.h
···
45
45
bool page;
46
46
};
47
47
48
+
#define SDW_DOUBLE_RATE_FACTOR 2
49
+
50
+
extern int rows[SDW_FRAME_ROWS];
51
+
extern int cols[SDW_FRAME_COLS];
52
+
53
+
/**
54
+
* sdw_port_runtime: Runtime port parameters for Master or Slave
55
+
*
56
+
* @num: Port number. For audio streams, valid port number ranges from
57
+
* [1,14]
58
+
* @ch_mask: Channel mask
59
+
* @transport_params: Transport parameters
60
+
* @port_params: Port parameters
61
+
* @port_node: List node for Master or Slave port_list
62
+
*
63
+
* SoundWire spec has no mention of ports for Master interface but the
64
+
* concept is logically extended.
65
+
*/
66
+
struct sdw_port_runtime {
67
+
int num;
68
+
int ch_mask;
69
+
struct sdw_transport_params transport_params;
70
+
struct sdw_port_params port_params;
71
+
struct list_head port_node;
72
+
};
73
+
74
+
/**
75
+
* sdw_slave_runtime: Runtime Stream parameters for Slave
76
+
*
77
+
* @slave: Slave handle
78
+
* @direction: Data direction for Slave
79
+
* @ch_count: Number of channels handled by the Slave for
80
+
* this stream
81
+
* @m_rt_node: sdw_master_runtime list node
82
+
* @port_list: List of Slave Ports configured for this stream
83
+
*/
84
+
struct sdw_slave_runtime {
85
+
struct sdw_slave *slave;
86
+
enum sdw_data_direction direction;
87
+
unsigned int ch_count;
88
+
struct list_head m_rt_node;
89
+
struct list_head port_list;
90
+
};
91
+
92
+
/**
93
+
* sdw_master_runtime: Runtime stream parameters for Master
94
+
*
95
+
* @bus: Bus handle
96
+
* @stream: Stream runtime handle
97
+
* @direction: Data direction for Master
98
+
* @ch_count: Number of channels handled by the Master for
99
+
* this stream, can be zero.
100
+
* @slave_rt_list: Slave runtime list
101
+
* @port_list: List of Master Ports configured for this stream, can be zero.
102
+
* @bus_node: sdw_bus m_rt_list node
103
+
*/
104
+
struct sdw_master_runtime {
105
+
struct sdw_bus *bus;
106
+
struct sdw_stream_runtime *stream;
107
+
enum sdw_data_direction direction;
108
+
unsigned int ch_count;
109
+
struct list_head slave_rt_list;
110
+
struct list_head port_list;
111
+
struct list_head bus_node;
112
+
};
113
+
114
+
struct sdw_dpn_prop *sdw_get_slave_dpn_prop(struct sdw_slave *slave,
115
+
enum sdw_data_direction direction,
116
+
unsigned int port_num);
117
+
int sdw_configure_dpn_intr(struct sdw_slave *slave, int port,
118
+
bool enable, int mask);
119
+
48
120
int sdw_transfer(struct sdw_bus *bus, struct sdw_msg *msg);
49
121
int sdw_transfer_defer(struct sdw_bus *bus, struct sdw_msg *msg,
50
122
struct sdw_defer *defer);
+442
-9
drivers/soundwire/cadence_master.c
+442
-9
drivers/soundwire/cadence_master.c
···
13
13
#include <linux/mod_devicetable.h>
14
14
#include <linux/soundwire/sdw_registers.h>
15
15
#include <linux/soundwire/sdw.h>
16
+
#include <sound/pcm_params.h>
17
+
#include <sound/soc.h>
16
18
#include "bus.h"
17
19
#include "cadence_master.h"
18
20
···
398
396
return 0;
399
397
}
400
398
401
-
static enum sdw_command_response
399
+
enum sdw_command_response
402
400
cdns_xfer_msg(struct sdw_bus *bus, struct sdw_msg *msg)
403
401
{
404
402
struct sdw_cdns *cdns = bus_to_cdns(bus);
···
424
422
exit:
425
423
return ret;
426
424
}
425
+
EXPORT_SYMBOL(cdns_xfer_msg);
427
426
428
-
static enum sdw_command_response
427
+
enum sdw_command_response
429
428
cdns_xfer_msg_defer(struct sdw_bus *bus,
430
429
struct sdw_msg *msg, struct sdw_defer *defer)
431
430
{
···
446
443
447
444
return _cdns_xfer_msg(cdns, msg, cmd, 0, msg->len, true);
448
445
}
446
+
EXPORT_SYMBOL(cdns_xfer_msg_defer);
449
447
450
-
static enum sdw_command_response
448
+
enum sdw_command_response
451
449
cdns_reset_page_addr(struct sdw_bus *bus, unsigned int dev_num)
452
450
{
453
451
struct sdw_cdns *cdns = bus_to_cdns(bus);
···
460
456
461
457
return cdns_program_scp_addr(cdns, &msg);
462
458
}
459
+
EXPORT_SYMBOL(cdns_reset_page_addr);
463
460
464
461
/*
465
462
* IRQ handling
···
671
666
}
672
667
EXPORT_SYMBOL(sdw_cdns_enable_interrupt);
673
668
669
+
static int cdns_allocate_pdi(struct sdw_cdns *cdns,
670
+
struct sdw_cdns_pdi **stream,
671
+
u32 num, u32 pdi_offset)
672
+
{
673
+
struct sdw_cdns_pdi *pdi;
674
+
int i;
675
+
676
+
if (!num)
677
+
return 0;
678
+
679
+
pdi = devm_kcalloc(cdns->dev, num, sizeof(*pdi), GFP_KERNEL);
680
+
if (!pdi)
681
+
return -ENOMEM;
682
+
683
+
for (i = 0; i < num; i++) {
684
+
pdi[i].num = i + pdi_offset;
685
+
pdi[i].assigned = false;
686
+
}
687
+
688
+
*stream = pdi;
689
+
return 0;
690
+
}
691
+
692
+
/**
693
+
* sdw_cdns_pdi_init() - PDI initialization routine
694
+
*
695
+
* @cdns: Cadence instance
696
+
* @config: Stream configurations
697
+
*/
698
+
int sdw_cdns_pdi_init(struct sdw_cdns *cdns,
699
+
struct sdw_cdns_stream_config config)
700
+
{
701
+
struct sdw_cdns_streams *stream;
702
+
int offset, i, ret;
703
+
704
+
cdns->pcm.num_bd = config.pcm_bd;
705
+
cdns->pcm.num_in = config.pcm_in;
706
+
cdns->pcm.num_out = config.pcm_out;
707
+
cdns->pdm.num_bd = config.pdm_bd;
708
+
cdns->pdm.num_in = config.pdm_in;
709
+
cdns->pdm.num_out = config.pdm_out;
710
+
711
+
/* Allocate PDIs for PCMs */
712
+
stream = &cdns->pcm;
713
+
714
+
/* First two PDIs are reserved for bulk transfers */
715
+
stream->num_bd -= CDNS_PCM_PDI_OFFSET;
716
+
offset = CDNS_PCM_PDI_OFFSET;
717
+
718
+
ret = cdns_allocate_pdi(cdns, &stream->bd,
719
+
stream->num_bd, offset);
720
+
if (ret)
721
+
return ret;
722
+
723
+
offset += stream->num_bd;
724
+
725
+
ret = cdns_allocate_pdi(cdns, &stream->in,
726
+
stream->num_in, offset);
727
+
if (ret)
728
+
return ret;
729
+
730
+
offset += stream->num_in;
731
+
732
+
ret = cdns_allocate_pdi(cdns, &stream->out,
733
+
stream->num_out, offset);
734
+
if (ret)
735
+
return ret;
736
+
737
+
/* Update total number of PCM PDIs */
738
+
stream->num_pdi = stream->num_bd + stream->num_in + stream->num_out;
739
+
cdns->num_ports = stream->num_pdi;
740
+
741
+
/* Allocate PDIs for PDMs */
742
+
stream = &cdns->pdm;
743
+
offset = CDNS_PDM_PDI_OFFSET;
744
+
ret = cdns_allocate_pdi(cdns, &stream->bd,
745
+
stream->num_bd, offset);
746
+
if (ret)
747
+
return ret;
748
+
749
+
offset += stream->num_bd;
750
+
751
+
ret = cdns_allocate_pdi(cdns, &stream->in,
752
+
stream->num_in, offset);
753
+
if (ret)
754
+
return ret;
755
+
756
+
offset += stream->num_in;
757
+
758
+
ret = cdns_allocate_pdi(cdns, &stream->out,
759
+
stream->num_out, offset);
760
+
if (ret)
761
+
return ret;
762
+
763
+
/* Update total number of PDM PDIs */
764
+
stream->num_pdi = stream->num_bd + stream->num_in + stream->num_out;
765
+
cdns->num_ports += stream->num_pdi;
766
+
767
+
cdns->ports = devm_kcalloc(cdns->dev, cdns->num_ports,
768
+
sizeof(*cdns->ports), GFP_KERNEL);
769
+
if (!cdns->ports) {
770
+
ret = -ENOMEM;
771
+
return ret;
772
+
}
773
+
774
+
for (i = 0; i < cdns->num_ports; i++) {
775
+
cdns->ports[i].assigned = false;
776
+
cdns->ports[i].num = i + 1; /* Port 0 reserved for bulk */
777
+
}
778
+
779
+
return 0;
780
+
}
781
+
EXPORT_SYMBOL(sdw_cdns_pdi_init);
782
+
674
783
/**
675
784
* sdw_cdns_init() - Cadence initialization
676
785
* @cdns: Cadence instance
···
846
727
}
847
728
EXPORT_SYMBOL(sdw_cdns_init);
848
729
849
-
struct sdw_master_ops sdw_cdns_master_ops = {
850
-
.read_prop = sdw_master_read_prop,
851
-
.xfer_msg = cdns_xfer_msg,
852
-
.xfer_msg_defer = cdns_xfer_msg_defer,
853
-
.reset_page_addr = cdns_reset_page_addr,
730
+
int cdns_bus_conf(struct sdw_bus *bus, struct sdw_bus_params *params)
731
+
{
732
+
struct sdw_cdns *cdns = bus_to_cdns(bus);
733
+
int mcp_clkctrl_off, mcp_clkctrl;
734
+
int divider;
735
+
736
+
if (!params->curr_dr_freq) {
737
+
dev_err(cdns->dev, "NULL curr_dr_freq");
738
+
return -EINVAL;
739
+
}
740
+
741
+
divider = (params->max_dr_freq / params->curr_dr_freq) - 1;
742
+
743
+
if (params->next_bank)
744
+
mcp_clkctrl_off = CDNS_MCP_CLK_CTRL1;
745
+
else
746
+
mcp_clkctrl_off = CDNS_MCP_CLK_CTRL0;
747
+
748
+
mcp_clkctrl = cdns_readl(cdns, mcp_clkctrl_off);
749
+
mcp_clkctrl |= divider;
750
+
cdns_writel(cdns, mcp_clkctrl_off, mcp_clkctrl);
751
+
752
+
return 0;
753
+
}
754
+
EXPORT_SYMBOL(cdns_bus_conf);
755
+
756
+
static int cdns_port_params(struct sdw_bus *bus,
757
+
struct sdw_port_params *p_params, unsigned int bank)
758
+
{
759
+
struct sdw_cdns *cdns = bus_to_cdns(bus);
760
+
int dpn_config = 0, dpn_config_off;
761
+
762
+
if (bank)
763
+
dpn_config_off = CDNS_DPN_B1_CONFIG(p_params->num);
764
+
else
765
+
dpn_config_off = CDNS_DPN_B0_CONFIG(p_params->num);
766
+
767
+
dpn_config = cdns_readl(cdns, dpn_config_off);
768
+
769
+
dpn_config |= ((p_params->bps - 1) <<
770
+
SDW_REG_SHIFT(CDNS_DPN_CONFIG_WL));
771
+
dpn_config |= (p_params->flow_mode <<
772
+
SDW_REG_SHIFT(CDNS_DPN_CONFIG_PORT_FLOW));
773
+
dpn_config |= (p_params->data_mode <<
774
+
SDW_REG_SHIFT(CDNS_DPN_CONFIG_PORT_DAT));
775
+
776
+
cdns_writel(cdns, dpn_config_off, dpn_config);
777
+
778
+
return 0;
779
+
}
780
+
781
+
static int cdns_transport_params(struct sdw_bus *bus,
782
+
struct sdw_transport_params *t_params,
783
+
enum sdw_reg_bank bank)
784
+
{
785
+
struct sdw_cdns *cdns = bus_to_cdns(bus);
786
+
int dpn_offsetctrl = 0, dpn_offsetctrl_off;
787
+
int dpn_config = 0, dpn_config_off;
788
+
int dpn_hctrl = 0, dpn_hctrl_off;
789
+
int num = t_params->port_num;
790
+
int dpn_samplectrl_off;
791
+
792
+
/*
793
+
* Note: Only full data port is supported on the Master side for
794
+
* both PCM and PDM ports.
795
+
*/
796
+
797
+
if (bank) {
798
+
dpn_config_off = CDNS_DPN_B1_CONFIG(num);
799
+
dpn_samplectrl_off = CDNS_DPN_B1_SAMPLE_CTRL(num);
800
+
dpn_hctrl_off = CDNS_DPN_B1_HCTRL(num);
801
+
dpn_offsetctrl_off = CDNS_DPN_B1_OFFSET_CTRL(num);
802
+
} else {
803
+
dpn_config_off = CDNS_DPN_B0_CONFIG(num);
804
+
dpn_samplectrl_off = CDNS_DPN_B0_SAMPLE_CTRL(num);
805
+
dpn_hctrl_off = CDNS_DPN_B0_HCTRL(num);
806
+
dpn_offsetctrl_off = CDNS_DPN_B0_OFFSET_CTRL(num);
807
+
}
808
+
809
+
dpn_config = cdns_readl(cdns, dpn_config_off);
810
+
811
+
dpn_config |= (t_params->blk_grp_ctrl <<
812
+
SDW_REG_SHIFT(CDNS_DPN_CONFIG_BGC));
813
+
dpn_config |= (t_params->blk_pkg_mode <<
814
+
SDW_REG_SHIFT(CDNS_DPN_CONFIG_BPM));
815
+
cdns_writel(cdns, dpn_config_off, dpn_config);
816
+
817
+
dpn_offsetctrl |= (t_params->offset1 <<
818
+
SDW_REG_SHIFT(CDNS_DPN_OFFSET_CTRL_1));
819
+
dpn_offsetctrl |= (t_params->offset2 <<
820
+
SDW_REG_SHIFT(CDNS_DPN_OFFSET_CTRL_2));
821
+
cdns_writel(cdns, dpn_offsetctrl_off, dpn_offsetctrl);
822
+
823
+
dpn_hctrl |= (t_params->hstart <<
824
+
SDW_REG_SHIFT(CDNS_DPN_HCTRL_HSTART));
825
+
dpn_hctrl |= (t_params->hstop << SDW_REG_SHIFT(CDNS_DPN_HCTRL_HSTOP));
826
+
dpn_hctrl |= (t_params->lane_ctrl <<
827
+
SDW_REG_SHIFT(CDNS_DPN_HCTRL_LCTRL));
828
+
829
+
cdns_writel(cdns, dpn_hctrl_off, dpn_hctrl);
830
+
cdns_writel(cdns, dpn_samplectrl_off, (t_params->sample_interval - 1));
831
+
832
+
return 0;
833
+
}
834
+
835
+
static int cdns_port_enable(struct sdw_bus *bus,
836
+
struct sdw_enable_ch *enable_ch, unsigned int bank)
837
+
{
838
+
struct sdw_cdns *cdns = bus_to_cdns(bus);
839
+
int dpn_chnen_off, ch_mask;
840
+
841
+
if (bank)
842
+
dpn_chnen_off = CDNS_DPN_B1_CH_EN(enable_ch->port_num);
843
+
else
844
+
dpn_chnen_off = CDNS_DPN_B0_CH_EN(enable_ch->port_num);
845
+
846
+
ch_mask = enable_ch->ch_mask * enable_ch->enable;
847
+
cdns_writel(cdns, dpn_chnen_off, ch_mask);
848
+
849
+
return 0;
850
+
}
851
+
852
+
static const struct sdw_master_port_ops cdns_port_ops = {
853
+
.dpn_set_port_params = cdns_port_params,
854
+
.dpn_set_port_transport_params = cdns_transport_params,
855
+
.dpn_port_enable_ch = cdns_port_enable,
854
856
};
855
-
EXPORT_SYMBOL(sdw_cdns_master_ops);
856
857
857
858
/**
858
859
* sdw_cdns_probe() - Cadence probe routine
···
981
742
int sdw_cdns_probe(struct sdw_cdns *cdns)
982
743
{
983
744
init_completion(&cdns->tx_complete);
745
+
cdns->bus.port_ops = &cdns_port_ops;
984
746
985
747
return 0;
986
748
}
987
749
EXPORT_SYMBOL(sdw_cdns_probe);
750
+
751
+
int cdns_set_sdw_stream(struct snd_soc_dai *dai,
752
+
void *stream, bool pcm, int direction)
753
+
{
754
+
struct sdw_cdns *cdns = snd_soc_dai_get_drvdata(dai);
755
+
struct sdw_cdns_dma_data *dma;
756
+
757
+
dma = kzalloc(sizeof(*dma), GFP_KERNEL);
758
+
if (!dma)
759
+
return -ENOMEM;
760
+
761
+
if (pcm)
762
+
dma->stream_type = SDW_STREAM_PCM;
763
+
else
764
+
dma->stream_type = SDW_STREAM_PDM;
765
+
766
+
dma->bus = &cdns->bus;
767
+
dma->link_id = cdns->instance;
768
+
769
+
dma->stream = stream;
770
+
771
+
if (direction == SNDRV_PCM_STREAM_PLAYBACK)
772
+
dai->playback_dma_data = dma;
773
+
else
774
+
dai->capture_dma_data = dma;
775
+
776
+
return 0;
777
+
}
778
+
EXPORT_SYMBOL(cdns_set_sdw_stream);
779
+
780
+
/**
781
+
* cdns_find_pdi() - Find a free PDI
782
+
*
783
+
* @cdns: Cadence instance
784
+
* @num: Number of PDIs
785
+
* @pdi: PDI instances
786
+
*
787
+
* Find and return a free PDI for a given PDI array
788
+
*/
789
+
static struct sdw_cdns_pdi *cdns_find_pdi(struct sdw_cdns *cdns,
790
+
unsigned int num, struct sdw_cdns_pdi *pdi)
791
+
{
792
+
int i;
793
+
794
+
for (i = 0; i < num; i++) {
795
+
if (pdi[i].assigned == true)
796
+
continue;
797
+
pdi[i].assigned = true;
798
+
return &pdi[i];
799
+
}
800
+
801
+
return NULL;
802
+
}
803
+
804
+
/**
805
+
* sdw_cdns_config_stream: Configure a stream
806
+
*
807
+
* @cdns: Cadence instance
808
+
* @port: Cadence data port
809
+
* @ch: Channel count
810
+
* @dir: Data direction
811
+
* @pdi: PDI to be used
812
+
*/
813
+
void sdw_cdns_config_stream(struct sdw_cdns *cdns,
814
+
struct sdw_cdns_port *port,
815
+
u32 ch, u32 dir, struct sdw_cdns_pdi *pdi)
816
+
{
817
+
u32 offset, val = 0;
818
+
819
+
if (dir == SDW_DATA_DIR_RX)
820
+
val = CDNS_PORTCTRL_DIRN;
821
+
822
+
offset = CDNS_PORTCTRL + port->num * CDNS_PORT_OFFSET;
823
+
cdns_updatel(cdns, offset, CDNS_PORTCTRL_DIRN, val);
824
+
825
+
val = port->num;
826
+
val |= ((1 << ch) - 1) << SDW_REG_SHIFT(CDNS_PDI_CONFIG_CHANNEL);
827
+
cdns_writel(cdns, CDNS_PDI_CONFIG(pdi->num), val);
828
+
}
829
+
EXPORT_SYMBOL(sdw_cdns_config_stream);
830
+
831
+
/**
832
+
* cdns_get_num_pdi() - Get number of PDIs required
833
+
*
834
+
* @cdns: Cadence instance
835
+
* @pdi: PDI to be used
836
+
* @num: Number of PDIs
837
+
* @ch_count: Channel count
838
+
*/
839
+
static int cdns_get_num_pdi(struct sdw_cdns *cdns,
840
+
struct sdw_cdns_pdi *pdi,
841
+
unsigned int num, u32 ch_count)
842
+
{
843
+
int i, pdis = 0;
844
+
845
+
for (i = 0; i < num; i++) {
846
+
if (pdi[i].assigned == true)
847
+
continue;
848
+
849
+
if (pdi[i].ch_count < ch_count)
850
+
ch_count -= pdi[i].ch_count;
851
+
else
852
+
ch_count = 0;
853
+
854
+
pdis++;
855
+
856
+
if (!ch_count)
857
+
break;
858
+
}
859
+
860
+
if (ch_count)
861
+
return 0;
862
+
863
+
return pdis;
864
+
}
865
+
866
+
/**
867
+
* sdw_cdns_get_stream() - Get stream information
868
+
*
869
+
* @cdns: Cadence instance
870
+
* @stream: Stream to be allocated
871
+
* @ch: Channel count
872
+
* @dir: Data direction
873
+
*/
874
+
int sdw_cdns_get_stream(struct sdw_cdns *cdns,
875
+
struct sdw_cdns_streams *stream,
876
+
u32 ch, u32 dir)
877
+
{
878
+
int pdis = 0;
879
+
880
+
if (dir == SDW_DATA_DIR_RX)
881
+
pdis = cdns_get_num_pdi(cdns, stream->in, stream->num_in, ch);
882
+
else
883
+
pdis = cdns_get_num_pdi(cdns, stream->out, stream->num_out, ch);
884
+
885
+
/* check if we found PDI, else find in bi-directional */
886
+
if (!pdis)
887
+
pdis = cdns_get_num_pdi(cdns, stream->bd, stream->num_bd, ch);
888
+
889
+
return pdis;
890
+
}
891
+
EXPORT_SYMBOL(sdw_cdns_get_stream);
892
+
893
+
/**
894
+
* sdw_cdns_alloc_stream() - Allocate a stream
895
+
*
896
+
* @cdns: Cadence instance
897
+
* @stream: Stream to be allocated
898
+
* @port: Cadence data port
899
+
* @ch: Channel count
900
+
* @dir: Data direction
901
+
*/
902
+
int sdw_cdns_alloc_stream(struct sdw_cdns *cdns,
903
+
struct sdw_cdns_streams *stream,
904
+
struct sdw_cdns_port *port, u32 ch, u32 dir)
905
+
{
906
+
struct sdw_cdns_pdi *pdi = NULL;
907
+
908
+
if (dir == SDW_DATA_DIR_RX)
909
+
pdi = cdns_find_pdi(cdns, stream->num_in, stream->in);
910
+
else
911
+
pdi = cdns_find_pdi(cdns, stream->num_out, stream->out);
912
+
913
+
/* check if we found a PDI, else find in bi-directional */
914
+
if (!pdi)
915
+
pdi = cdns_find_pdi(cdns, stream->num_bd, stream->bd);
916
+
917
+
if (!pdi)
918
+
return -EIO;
919
+
920
+
port->pdi = pdi;
921
+
pdi->l_ch_num = 0;
922
+
pdi->h_ch_num = ch - 1;
923
+
pdi->dir = dir;
924
+
pdi->ch_count = ch;
925
+
926
+
return 0;
927
+
}
928
+
EXPORT_SYMBOL(sdw_cdns_alloc_stream);
929
+
930
+
void sdw_cdns_shutdown(struct snd_pcm_substream *substream,
931
+
struct snd_soc_dai *dai)
932
+
{
933
+
struct sdw_cdns_dma_data *dma;
934
+
935
+
dma = snd_soc_dai_get_dma_data(dai, substream);
936
+
if (!dma)
937
+
return;
938
+
939
+
snd_soc_dai_set_dma_data(dai, substream, NULL);
940
+
kfree(dma);
941
+
}
942
+
EXPORT_SYMBOL(sdw_cdns_shutdown);
988
943
989
944
MODULE_LICENSE("Dual BSD/GPL");
990
945
MODULE_DESCRIPTION("Cadence Soundwire Library");
+151
drivers/soundwire/cadence_master.h
+151
drivers/soundwire/cadence_master.h
···
1
1
// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
2
2
// Copyright(c) 2015-17 Intel Corporation.
3
+
#include <sound/soc.h>
3
4
4
5
#ifndef __SDW_CADENCE_H
5
6
#define __SDW_CADENCE_H
7
+
8
+
/**
9
+
* struct sdw_cdns_pdi: PDI (Physical Data Interface) instance
10
+
*
11
+
* @assigned: pdi assigned
12
+
* @num: pdi number
13
+
* @intel_alh_id: link identifier
14
+
* @l_ch_num: low channel for PDI
15
+
* @h_ch_num: high channel for PDI
16
+
* @ch_count: total channel count for PDI
17
+
* @dir: data direction
18
+
* @type: stream type, PDM or PCM
19
+
*/
20
+
struct sdw_cdns_pdi {
21
+
bool assigned;
22
+
int num;
23
+
int intel_alh_id;
24
+
int l_ch_num;
25
+
int h_ch_num;
26
+
int ch_count;
27
+
enum sdw_data_direction dir;
28
+
enum sdw_stream_type type;
29
+
};
30
+
31
+
/**
32
+
* struct sdw_cdns_port: Cadence port structure
33
+
*
34
+
* @num: port number
35
+
* @assigned: port assigned
36
+
* @ch: channel count
37
+
* @direction: data port direction
38
+
* @pdi: pdi for this port
39
+
*/
40
+
struct sdw_cdns_port {
41
+
unsigned int num;
42
+
bool assigned;
43
+
unsigned int ch;
44
+
enum sdw_data_direction direction;
45
+
struct sdw_cdns_pdi *pdi;
46
+
};
47
+
48
+
/**
49
+
* struct sdw_cdns_streams: Cadence stream data structure
50
+
*
51
+
* @num_bd: number of bidirectional streams
52
+
* @num_in: number of input streams
53
+
* @num_out: number of output streams
54
+
* @num_ch_bd: number of bidirectional stream channels
55
+
* @num_ch_bd: number of input stream channels
56
+
* @num_ch_bd: number of output stream channels
57
+
* @num_pdi: total number of PDIs
58
+
* @bd: bidirectional streams
59
+
* @in: input streams
60
+
* @out: output streams
61
+
*/
62
+
struct sdw_cdns_streams {
63
+
unsigned int num_bd;
64
+
unsigned int num_in;
65
+
unsigned int num_out;
66
+
unsigned int num_ch_bd;
67
+
unsigned int num_ch_in;
68
+
unsigned int num_ch_out;
69
+
unsigned int num_pdi;
70
+
struct sdw_cdns_pdi *bd;
71
+
struct sdw_cdns_pdi *in;
72
+
struct sdw_cdns_pdi *out;
73
+
};
74
+
75
+
/**
76
+
* struct sdw_cdns_stream_config: stream configuration
77
+
*
78
+
* @pcm_bd: number of bidirectional PCM streams supported
79
+
* @pcm_in: number of input PCM streams supported
80
+
* @pcm_out: number of output PCM streams supported
81
+
* @pdm_bd: number of bidirectional PDM streams supported
82
+
* @pdm_in: number of input PDM streams supported
83
+
* @pdm_out: number of output PDM streams supported
84
+
*/
85
+
struct sdw_cdns_stream_config {
86
+
unsigned int pcm_bd;
87
+
unsigned int pcm_in;
88
+
unsigned int pcm_out;
89
+
unsigned int pdm_bd;
90
+
unsigned int pdm_in;
91
+
unsigned int pdm_out;
92
+
};
93
+
94
+
/**
95
+
* struct sdw_cdns_dma_data: Cadence DMA data
96
+
*
97
+
* @name: SoundWire stream name
98
+
* @nr_ports: Number of ports
99
+
* @port: Ports
100
+
* @bus: Bus handle
101
+
* @stream_type: Stream type
102
+
* @link_id: Master link id
103
+
*/
104
+
struct sdw_cdns_dma_data {
105
+
char *name;
106
+
struct sdw_stream_runtime *stream;
107
+
int nr_ports;
108
+
struct sdw_cdns_port **port;
109
+
struct sdw_bus *bus;
110
+
enum sdw_stream_type stream_type;
111
+
int link_id;
112
+
};
6
113
7
114
/**
8
115
* struct sdw_cdns - Cadence driver context
···
119
12
* @response_buf: SoundWire response buffer
120
13
* @tx_complete: Tx completion
121
14
* @defer: Defer pointer
15
+
* @ports: Data ports
16
+
* @num_ports: Total number of data ports
17
+
* @pcm: PCM streams
18
+
* @pdm: PDM streams
122
19
* @registers: Cadence registers
123
20
* @link_up: Link status
124
21
* @msg_count: Messages sent on bus
···
135
24
u32 response_buf[0x80];
136
25
struct completion tx_complete;
137
26
struct sdw_defer *defer;
27
+
28
+
struct sdw_cdns_port *ports;
29
+
int num_ports;
30
+
31
+
struct sdw_cdns_streams pcm;
32
+
struct sdw_cdns_streams pdm;
138
33
139
34
void __iomem *registers;
140
35
···
159
42
irqreturn_t sdw_cdns_thread(int irq, void *dev_id);
160
43
161
44
int sdw_cdns_init(struct sdw_cdns *cdns);
45
+
int sdw_cdns_pdi_init(struct sdw_cdns *cdns,
46
+
struct sdw_cdns_stream_config config);
162
47
int sdw_cdns_enable_interrupt(struct sdw_cdns *cdns);
163
48
49
+
int sdw_cdns_get_stream(struct sdw_cdns *cdns,
50
+
struct sdw_cdns_streams *stream,
51
+
u32 ch, u32 dir);
52
+
int sdw_cdns_alloc_stream(struct sdw_cdns *cdns,
53
+
struct sdw_cdns_streams *stream,
54
+
struct sdw_cdns_port *port, u32 ch, u32 dir);
55
+
void sdw_cdns_config_stream(struct sdw_cdns *cdns, struct sdw_cdns_port *port,
56
+
u32 ch, u32 dir, struct sdw_cdns_pdi *pdi);
164
57
58
+
void sdw_cdns_shutdown(struct snd_pcm_substream *substream,
59
+
struct snd_soc_dai *dai);
60
+
int sdw_cdns_pcm_set_stream(struct snd_soc_dai *dai,
61
+
void *stream, int direction);
62
+
int sdw_cdns_pdm_set_stream(struct snd_soc_dai *dai,
63
+
void *stream, int direction);
64
+
65
+
enum sdw_command_response
66
+
cdns_reset_page_addr(struct sdw_bus *bus, unsigned int dev_num);
67
+
68
+
enum sdw_command_response
69
+
cdns_xfer_msg(struct sdw_bus *bus, struct sdw_msg *msg);
70
+
71
+
enum sdw_command_response
72
+
cdns_xfer_msg_defer(struct sdw_bus *bus,
73
+
struct sdw_msg *msg, struct sdw_defer *defer);
74
+
75
+
enum sdw_command_response
76
+
cdns_reset_page_addr(struct sdw_bus *bus, unsigned int dev_num);
77
+
78
+
int cdns_bus_conf(struct sdw_bus *bus, struct sdw_bus_params *params);
79
+
80
+
int cdns_set_sdw_stream(struct snd_soc_dai *dai,
81
+
void *stream, bool pcm, int direction);
165
82
#endif /* __SDW_CADENCE_H */
+523
-2
drivers/soundwire/intel.c
+523
-2
drivers/soundwire/intel.c
···
9
9
#include <linux/delay.h>
10
10
#include <linux/interrupt.h>
11
11
#include <linux/platform_device.h>
12
+
#include <sound/pcm_params.h>
13
+
#include <sound/soc.h>
12
14
#include <linux/soundwire/sdw_registers.h>
13
15
#include <linux/soundwire/sdw.h>
14
16
#include <linux/soundwire/sdw_intel.h>
···
86
84
#define SDW_ALH_STRMZCFG_DMAT_VAL 0x3
87
85
#define SDW_ALH_STRMZCFG_DMAT GENMASK(7, 0)
88
86
#define SDW_ALH_STRMZCFG_CHN GENMASK(19, 16)
87
+
88
+
enum intel_pdi_type {
89
+
INTEL_PDI_IN = 0,
90
+
INTEL_PDI_OUT = 1,
91
+
INTEL_PDI_BD = 2,
92
+
};
89
93
90
94
struct sdw_intel {
91
95
struct sdw_cdns cdns;
···
242
234
return ret;
243
235
}
244
236
237
+
/*
238
+
* PDI routines
239
+
*/
240
+
static void intel_pdi_init(struct sdw_intel *sdw,
241
+
struct sdw_cdns_stream_config *config)
242
+
{
243
+
void __iomem *shim = sdw->res->shim;
244
+
unsigned int link_id = sdw->instance;
245
+
int pcm_cap, pdm_cap;
246
+
247
+
/* PCM Stream Capability */
248
+
pcm_cap = intel_readw(shim, SDW_SHIM_PCMSCAP(link_id));
249
+
250
+
config->pcm_bd = (pcm_cap & SDW_SHIM_PCMSCAP_BSS) >>
251
+
SDW_REG_SHIFT(SDW_SHIM_PCMSCAP_BSS);
252
+
config->pcm_in = (pcm_cap & SDW_SHIM_PCMSCAP_ISS) >>
253
+
SDW_REG_SHIFT(SDW_SHIM_PCMSCAP_ISS);
254
+
config->pcm_out = (pcm_cap & SDW_SHIM_PCMSCAP_OSS) >>
255
+
SDW_REG_SHIFT(SDW_SHIM_PCMSCAP_OSS);
256
+
257
+
/* PDM Stream Capability */
258
+
pdm_cap = intel_readw(shim, SDW_SHIM_PDMSCAP(link_id));
259
+
260
+
config->pdm_bd = (pdm_cap & SDW_SHIM_PDMSCAP_BSS) >>
261
+
SDW_REG_SHIFT(SDW_SHIM_PDMSCAP_BSS);
262
+
config->pdm_in = (pdm_cap & SDW_SHIM_PDMSCAP_ISS) >>
263
+
SDW_REG_SHIFT(SDW_SHIM_PDMSCAP_ISS);
264
+
config->pdm_out = (pdm_cap & SDW_SHIM_PDMSCAP_OSS) >>
265
+
SDW_REG_SHIFT(SDW_SHIM_PDMSCAP_OSS);
266
+
}
267
+
268
+
static int
269
+
intel_pdi_get_ch_cap(struct sdw_intel *sdw, unsigned int pdi_num, bool pcm)
270
+
{
271
+
void __iomem *shim = sdw->res->shim;
272
+
unsigned int link_id = sdw->instance;
273
+
int count;
274
+
275
+
if (pcm) {
276
+
count = intel_readw(shim, SDW_SHIM_PCMSYCHC(link_id, pdi_num));
277
+
} else {
278
+
count = intel_readw(shim, SDW_SHIM_PDMSCAP(link_id));
279
+
count = ((count & SDW_SHIM_PDMSCAP_CPSS) >>
280
+
SDW_REG_SHIFT(SDW_SHIM_PDMSCAP_CPSS));
281
+
}
282
+
283
+
/* zero based values for channel count in register */
284
+
count++;
285
+
286
+
return count;
287
+
}
288
+
289
+
static int intel_pdi_get_ch_update(struct sdw_intel *sdw,
290
+
struct sdw_cdns_pdi *pdi,
291
+
unsigned int num_pdi,
292
+
unsigned int *num_ch, bool pcm)
293
+
{
294
+
int i, ch_count = 0;
295
+
296
+
for (i = 0; i < num_pdi; i++) {
297
+
pdi->ch_count = intel_pdi_get_ch_cap(sdw, pdi->num, pcm);
298
+
ch_count += pdi->ch_count;
299
+
pdi++;
300
+
}
301
+
302
+
*num_ch = ch_count;
303
+
return 0;
304
+
}
305
+
306
+
static int intel_pdi_stream_ch_update(struct sdw_intel *sdw,
307
+
struct sdw_cdns_streams *stream, bool pcm)
308
+
{
309
+
intel_pdi_get_ch_update(sdw, stream->bd, stream->num_bd,
310
+
&stream->num_ch_bd, pcm);
311
+
312
+
intel_pdi_get_ch_update(sdw, stream->in, stream->num_in,
313
+
&stream->num_ch_in, pcm);
314
+
315
+
intel_pdi_get_ch_update(sdw, stream->out, stream->num_out,
316
+
&stream->num_ch_out, pcm);
317
+
318
+
return 0;
319
+
}
320
+
321
+
static int intel_pdi_ch_update(struct sdw_intel *sdw)
322
+
{
323
+
/* First update PCM streams followed by PDM streams */
324
+
intel_pdi_stream_ch_update(sdw, &sdw->cdns.pcm, true);
325
+
intel_pdi_stream_ch_update(sdw, &sdw->cdns.pdm, false);
326
+
327
+
return 0;
328
+
}
329
+
330
+
static void
331
+
intel_pdi_shim_configure(struct sdw_intel *sdw, struct sdw_cdns_pdi *pdi)
332
+
{
333
+
void __iomem *shim = sdw->res->shim;
334
+
unsigned int link_id = sdw->instance;
335
+
int pdi_conf = 0;
336
+
337
+
pdi->intel_alh_id = (link_id * 16) + pdi->num + 5;
338
+
339
+
/*
340
+
* Program stream parameters to stream SHIM register
341
+
* This is applicable for PCM stream only.
342
+
*/
343
+
if (pdi->type != SDW_STREAM_PCM)
344
+
return;
345
+
346
+
if (pdi->dir == SDW_DATA_DIR_RX)
347
+
pdi_conf |= SDW_SHIM_PCMSYCM_DIR;
348
+
else
349
+
pdi_conf &= ~(SDW_SHIM_PCMSYCM_DIR);
350
+
351
+
pdi_conf |= (pdi->intel_alh_id <<
352
+
SDW_REG_SHIFT(SDW_SHIM_PCMSYCM_STREAM));
353
+
pdi_conf |= (pdi->l_ch_num << SDW_REG_SHIFT(SDW_SHIM_PCMSYCM_LCHN));
354
+
pdi_conf |= (pdi->h_ch_num << SDW_REG_SHIFT(SDW_SHIM_PCMSYCM_HCHN));
355
+
356
+
intel_writew(shim, SDW_SHIM_PCMSYCHM(link_id, pdi->num), pdi_conf);
357
+
}
358
+
359
+
static void
360
+
intel_pdi_alh_configure(struct sdw_intel *sdw, struct sdw_cdns_pdi *pdi)
361
+
{
362
+
void __iomem *alh = sdw->res->alh;
363
+
unsigned int link_id = sdw->instance;
364
+
unsigned int conf;
365
+
366
+
pdi->intel_alh_id = (link_id * 16) + pdi->num + 5;
367
+
368
+
/* Program Stream config ALH register */
369
+
conf = intel_readl(alh, SDW_ALH_STRMZCFG(pdi->intel_alh_id));
370
+
371
+
conf |= (SDW_ALH_STRMZCFG_DMAT_VAL <<
372
+
SDW_REG_SHIFT(SDW_ALH_STRMZCFG_DMAT));
373
+
374
+
conf |= ((pdi->ch_count - 1) <<
375
+
SDW_REG_SHIFT(SDW_ALH_STRMZCFG_CHN));
376
+
377
+
intel_writel(alh, SDW_ALH_STRMZCFG(pdi->intel_alh_id), conf);
378
+
}
379
+
380
+
static int intel_config_stream(struct sdw_intel *sdw,
381
+
struct snd_pcm_substream *substream,
382
+
struct snd_soc_dai *dai,
383
+
struct snd_pcm_hw_params *hw_params, int link_id)
384
+
{
385
+
if (sdw->res->ops && sdw->res->ops->config_stream)
386
+
return sdw->res->ops->config_stream(sdw->res->arg,
387
+
substream, dai, hw_params, link_id);
388
+
389
+
return -EIO;
390
+
}
391
+
392
+
/*
393
+
* DAI routines
394
+
*/
395
+
396
+
static struct sdw_cdns_port *intel_alloc_port(struct sdw_intel *sdw,
397
+
u32 ch, u32 dir, bool pcm)
398
+
{
399
+
struct sdw_cdns *cdns = &sdw->cdns;
400
+
struct sdw_cdns_port *port = NULL;
401
+
int i, ret = 0;
402
+
403
+
for (i = 0; i < cdns->num_ports; i++) {
404
+
if (cdns->ports[i].assigned == true)
405
+
continue;
406
+
407
+
port = &cdns->ports[i];
408
+
port->assigned = true;
409
+
port->direction = dir;
410
+
port->ch = ch;
411
+
break;
412
+
}
413
+
414
+
if (!port) {
415
+
dev_err(cdns->dev, "Unable to find a free port\n");
416
+
return NULL;
417
+
}
418
+
419
+
if (pcm) {
420
+
ret = sdw_cdns_alloc_stream(cdns, &cdns->pcm, port, ch, dir);
421
+
if (ret)
422
+
goto out;
423
+
424
+
intel_pdi_shim_configure(sdw, port->pdi);
425
+
sdw_cdns_config_stream(cdns, port, ch, dir, port->pdi);
426
+
427
+
intel_pdi_alh_configure(sdw, port->pdi);
428
+
429
+
} else {
430
+
ret = sdw_cdns_alloc_stream(cdns, &cdns->pdm, port, ch, dir);
431
+
}
432
+
433
+
out:
434
+
if (ret) {
435
+
port->assigned = false;
436
+
port = NULL;
437
+
}
438
+
439
+
return port;
440
+
}
441
+
442
+
static void intel_port_cleanup(struct sdw_cdns_dma_data *dma)
443
+
{
444
+
int i;
445
+
446
+
for (i = 0; i < dma->nr_ports; i++) {
447
+
if (dma->port[i]) {
448
+
dma->port[i]->pdi->assigned = false;
449
+
dma->port[i]->pdi = NULL;
450
+
dma->port[i]->assigned = false;
451
+
dma->port[i] = NULL;
452
+
}
453
+
}
454
+
}
455
+
456
+
static int intel_hw_params(struct snd_pcm_substream *substream,
457
+
struct snd_pcm_hw_params *params,
458
+
struct snd_soc_dai *dai)
459
+
{
460
+
struct sdw_cdns *cdns = snd_soc_dai_get_drvdata(dai);
461
+
struct sdw_intel *sdw = cdns_to_intel(cdns);
462
+
struct sdw_cdns_dma_data *dma;
463
+
struct sdw_stream_config sconfig;
464
+
struct sdw_port_config *pconfig;
465
+
int ret, i, ch, dir;
466
+
bool pcm = true;
467
+
468
+
dma = snd_soc_dai_get_dma_data(dai, substream);
469
+
if (!dma)
470
+
return -EIO;
471
+
472
+
ch = params_channels(params);
473
+
if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
474
+
dir = SDW_DATA_DIR_RX;
475
+
else
476
+
dir = SDW_DATA_DIR_TX;
477
+
478
+
if (dma->stream_type == SDW_STREAM_PDM) {
479
+
/* TODO: Check whether PDM decimator is already in use */
480
+
dma->nr_ports = sdw_cdns_get_stream(cdns, &cdns->pdm, ch, dir);
481
+
pcm = false;
482
+
} else {
483
+
dma->nr_ports = sdw_cdns_get_stream(cdns, &cdns->pcm, ch, dir);
484
+
}
485
+
486
+
if (!dma->nr_ports) {
487
+
dev_err(dai->dev, "ports/resources not available");
488
+
return -EINVAL;
489
+
}
490
+
491
+
dma->port = kcalloc(dma->nr_ports, sizeof(*dma->port), GFP_KERNEL);
492
+
if (!dma->port)
493
+
return -ENOMEM;
494
+
495
+
for (i = 0; i < dma->nr_ports; i++) {
496
+
dma->port[i] = intel_alloc_port(sdw, ch, dir, pcm);
497
+
if (!dma->port[i]) {
498
+
ret = -EINVAL;
499
+
goto port_error;
500
+
}
501
+
}
502
+
503
+
/* Inform DSP about PDI stream number */
504
+
for (i = 0; i < dma->nr_ports; i++) {
505
+
ret = intel_config_stream(sdw, substream, dai, params,
506
+
dma->port[i]->pdi->intel_alh_id);
507
+
if (ret)
508
+
goto port_error;
509
+
}
510
+
511
+
sconfig.direction = dir;
512
+
sconfig.ch_count = ch;
513
+
sconfig.frame_rate = params_rate(params);
514
+
sconfig.type = dma->stream_type;
515
+
516
+
if (dma->stream_type == SDW_STREAM_PDM) {
517
+
sconfig.frame_rate *= 50;
518
+
sconfig.bps = 1;
519
+
} else {
520
+
sconfig.bps = snd_pcm_format_width(params_format(params));
521
+
}
522
+
523
+
/* Port configuration */
524
+
pconfig = kcalloc(dma->nr_ports, sizeof(*pconfig), GFP_KERNEL);
525
+
if (!pconfig) {
526
+
ret = -ENOMEM;
527
+
goto port_error;
528
+
}
529
+
530
+
for (i = 0; i < dma->nr_ports; i++) {
531
+
pconfig[i].num = dma->port[i]->num;
532
+
pconfig[i].ch_mask = (1 << ch) - 1;
533
+
}
534
+
535
+
ret = sdw_stream_add_master(&cdns->bus, &sconfig,
536
+
pconfig, dma->nr_ports, dma->stream);
537
+
if (ret) {
538
+
dev_err(cdns->dev, "add master to stream failed:%d", ret);
539
+
goto stream_error;
540
+
}
541
+
542
+
kfree(pconfig);
543
+
return ret;
544
+
545
+
stream_error:
546
+
kfree(pconfig);
547
+
port_error:
548
+
intel_port_cleanup(dma);
549
+
kfree(dma->port);
550
+
return ret;
551
+
}
552
+
553
+
static int
554
+
intel_hw_free(struct snd_pcm_substream *substream, struct snd_soc_dai *dai)
555
+
{
556
+
struct sdw_cdns *cdns = snd_soc_dai_get_drvdata(dai);
557
+
struct sdw_cdns_dma_data *dma;
558
+
int ret;
559
+
560
+
dma = snd_soc_dai_get_dma_data(dai, substream);
561
+
if (!dma)
562
+
return -EIO;
563
+
564
+
ret = sdw_stream_remove_master(&cdns->bus, dma->stream);
565
+
if (ret < 0)
566
+
dev_err(dai->dev, "remove master from stream %s failed: %d",
567
+
dma->stream->name, ret);
568
+
569
+
intel_port_cleanup(dma);
570
+
kfree(dma->port);
571
+
return ret;
572
+
}
573
+
574
+
static int intel_pcm_set_sdw_stream(struct snd_soc_dai *dai,
575
+
void *stream, int direction)
576
+
{
577
+
return cdns_set_sdw_stream(dai, stream, true, direction);
578
+
}
579
+
580
+
static int intel_pdm_set_sdw_stream(struct snd_soc_dai *dai,
581
+
void *stream, int direction)
582
+
{
583
+
return cdns_set_sdw_stream(dai, stream, false, direction);
584
+
}
585
+
586
+
static struct snd_soc_dai_ops intel_pcm_dai_ops = {
587
+
.hw_params = intel_hw_params,
588
+
.hw_free = intel_hw_free,
589
+
.shutdown = sdw_cdns_shutdown,
590
+
.set_sdw_stream = intel_pcm_set_sdw_stream,
591
+
};
592
+
593
+
static struct snd_soc_dai_ops intel_pdm_dai_ops = {
594
+
.hw_params = intel_hw_params,
595
+
.hw_free = intel_hw_free,
596
+
.shutdown = sdw_cdns_shutdown,
597
+
.set_sdw_stream = intel_pdm_set_sdw_stream,
598
+
};
599
+
600
+
static const struct snd_soc_component_driver dai_component = {
601
+
.name = "soundwire",
602
+
};
603
+
604
+
static int intel_create_dai(struct sdw_cdns *cdns,
605
+
struct snd_soc_dai_driver *dais,
606
+
enum intel_pdi_type type,
607
+
u32 num, u32 off, u32 max_ch, bool pcm)
608
+
{
609
+
int i;
610
+
611
+
if (num == 0)
612
+
return 0;
613
+
614
+
/* TODO: Read supported rates/formats from hardware */
615
+
for (i = off; i < (off + num); i++) {
616
+
dais[i].name = kasprintf(GFP_KERNEL, "SDW%d Pin%d",
617
+
cdns->instance, i);
618
+
if (!dais[i].name)
619
+
return -ENOMEM;
620
+
621
+
if (type == INTEL_PDI_BD || type == INTEL_PDI_OUT) {
622
+
dais[i].playback.stream_name = kasprintf(GFP_KERNEL,
623
+
"SDW%d Tx%d",
624
+
cdns->instance, i);
625
+
if (!dais[i].playback.stream_name) {
626
+
kfree(dais[i].name);
627
+
return -ENOMEM;
628
+
}
629
+
630
+
dais[i].playback.channels_min = 1;
631
+
dais[i].playback.channels_max = max_ch;
632
+
dais[i].playback.rates = SNDRV_PCM_RATE_48000;
633
+
dais[i].playback.formats = SNDRV_PCM_FMTBIT_S16_LE;
634
+
}
635
+
636
+
if (type == INTEL_PDI_BD || type == INTEL_PDI_IN) {
637
+
dais[i].capture.stream_name = kasprintf(GFP_KERNEL,
638
+
"SDW%d Rx%d",
639
+
cdns->instance, i);
640
+
if (!dais[i].capture.stream_name) {
641
+
kfree(dais[i].name);
642
+
kfree(dais[i].playback.stream_name);
643
+
return -ENOMEM;
644
+
}
645
+
646
+
dais[i].playback.channels_min = 1;
647
+
dais[i].playback.channels_max = max_ch;
648
+
dais[i].capture.rates = SNDRV_PCM_RATE_48000;
649
+
dais[i].capture.formats = SNDRV_PCM_FMTBIT_S16_LE;
650
+
}
651
+
652
+
dais[i].id = SDW_DAI_ID_RANGE_START + i;
653
+
654
+
if (pcm)
655
+
dais[i].ops = &intel_pcm_dai_ops;
656
+
else
657
+
dais[i].ops = &intel_pdm_dai_ops;
658
+
}
659
+
660
+
return 0;
661
+
}
662
+
663
+
static int intel_register_dai(struct sdw_intel *sdw)
664
+
{
665
+
struct sdw_cdns *cdns = &sdw->cdns;
666
+
struct sdw_cdns_streams *stream;
667
+
struct snd_soc_dai_driver *dais;
668
+
int num_dai, ret, off = 0;
669
+
670
+
/* DAIs are created based on total number of PDIs supported */
671
+
num_dai = cdns->pcm.num_pdi + cdns->pdm.num_pdi;
672
+
673
+
dais = devm_kcalloc(cdns->dev, num_dai, sizeof(*dais), GFP_KERNEL);
674
+
if (!dais)
675
+
return -ENOMEM;
676
+
677
+
/* Create PCM DAIs */
678
+
stream = &cdns->pcm;
679
+
680
+
ret = intel_create_dai(cdns, dais, INTEL_PDI_IN,
681
+
stream->num_in, off, stream->num_ch_in, true);
682
+
if (ret)
683
+
return ret;
684
+
685
+
off += cdns->pcm.num_in;
686
+
ret = intel_create_dai(cdns, dais, INTEL_PDI_OUT,
687
+
cdns->pcm.num_out, off, stream->num_ch_out, true);
688
+
if (ret)
689
+
return ret;
690
+
691
+
off += cdns->pcm.num_out;
692
+
ret = intel_create_dai(cdns, dais, INTEL_PDI_BD,
693
+
cdns->pcm.num_bd, off, stream->num_ch_bd, true);
694
+
if (ret)
695
+
return ret;
696
+
697
+
/* Create PDM DAIs */
698
+
stream = &cdns->pdm;
699
+
off += cdns->pcm.num_bd;
700
+
ret = intel_create_dai(cdns, dais, INTEL_PDI_IN,
701
+
cdns->pdm.num_in, off, stream->num_ch_in, false);
702
+
if (ret)
703
+
return ret;
704
+
705
+
off += cdns->pdm.num_in;
706
+
ret = intel_create_dai(cdns, dais, INTEL_PDI_OUT,
707
+
cdns->pdm.num_out, off, stream->num_ch_out, false);
708
+
if (ret)
709
+
return ret;
710
+
711
+
off += cdns->pdm.num_bd;
712
+
ret = intel_create_dai(cdns, dais, INTEL_PDI_BD,
713
+
cdns->pdm.num_bd, off, stream->num_ch_bd, false);
714
+
if (ret)
715
+
return ret;
716
+
717
+
return snd_soc_register_component(cdns->dev, &dai_component,
718
+
dais, num_dai);
719
+
}
720
+
245
721
static int intel_prop_read(struct sdw_bus *bus)
246
722
{
247
723
/* Initialize with default handler to read all DisCo properties */
···
744
252
return 0;
745
253
}
746
254
255
+
static struct sdw_master_ops sdw_intel_ops = {
256
+
.read_prop = sdw_master_read_prop,
257
+
.xfer_msg = cdns_xfer_msg,
258
+
.xfer_msg_defer = cdns_xfer_msg_defer,
259
+
.reset_page_addr = cdns_reset_page_addr,
260
+
.set_bus_conf = cdns_bus_conf,
261
+
};
262
+
747
263
/*
748
264
* probe and init
749
265
*/
750
266
static int intel_probe(struct platform_device *pdev)
751
267
{
268
+
struct sdw_cdns_stream_config config;
752
269
struct sdw_intel *sdw;
753
270
int ret;
754
271
···
777
276
sdw_cdns_probe(&sdw->cdns);
778
277
779
278
/* Set property read ops */
780
-
sdw_cdns_master_ops.read_prop = intel_prop_read;
781
-
sdw->cdns.bus.ops = &sdw_cdns_master_ops;
279
+
sdw_intel_ops.read_prop = intel_prop_read;
280
+
sdw->cdns.bus.ops = &sdw_intel_ops;
281
+
282
+
sdw_intel_ops.read_prop = intel_prop_read;
283
+
sdw->cdns.bus.ops = &sdw_intel_ops;
782
284
783
285
platform_set_drvdata(pdev, sdw);
784
286
···
800
296
goto err_init;
801
297
802
298
ret = sdw_cdns_enable_interrupt(&sdw->cdns);
299
+
300
+
/* Read the PDI config and initialize cadence PDI */
301
+
intel_pdi_init(sdw, &config);
302
+
ret = sdw_cdns_pdi_init(&sdw->cdns, config);
803
303
if (ret)
804
304
goto err_init;
305
+
306
+
intel_pdi_ch_update(sdw);
805
307
806
308
/* Acquire IRQ */
807
309
ret = request_threaded_irq(sdw->res->irq, sdw_cdns_irq,
···
819
309
goto err_init;
820
310
}
821
311
312
+
/* Register DAIs */
313
+
ret = intel_register_dai(sdw);
314
+
if (ret) {
315
+
dev_err(sdw->cdns.dev, "DAI registration failed: %d", ret);
316
+
snd_soc_unregister_component(sdw->cdns.dev);
317
+
goto err_dai;
318
+
}
319
+
822
320
return 0;
823
321
322
+
err_dai:
323
+
free_irq(sdw->res->irq, sdw);
824
324
err_init:
825
325
sdw_delete_bus_master(&sdw->cdns.bus);
826
326
err_master_reg:
···
844
324
sdw = platform_get_drvdata(pdev);
845
325
846
326
free_irq(sdw->res->irq, sdw);
327
+
snd_soc_unregister_component(sdw->cdns.dev);
847
328
sdw_delete_bus_master(&sdw->cdns.bus);
848
329
849
330
return 0;
+4
drivers/soundwire/intel.h
+4
drivers/soundwire/intel.h
···
10
10
* @shim: Audio shim pointer
11
11
* @alh: ALH (Audio Link Hub) pointer
12
12
* @irq: Interrupt line
13
+
* @ops: Shim callback ops
14
+
* @arg: Shim callback ops argument
13
15
*
14
16
* This is set as pdata for each link instance.
15
17
*/
···
20
18
void __iomem *shim;
21
19
void __iomem *alh;
22
20
int irq;
21
+
const struct sdw_intel_ops *ops;
22
+
void *arg;
23
23
};
24
24
25
25
#endif /* __SDW_INTEL_LOCAL_H */
+3
drivers/soundwire/intel_init.c
+3
drivers/soundwire/intel_init.c
+1479
drivers/soundwire/stream.c
+1479
drivers/soundwire/stream.c
···
1
+
// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
2
+
// Copyright(c) 2015-18 Intel Corporation.
3
+
4
+
/*
5
+
* stream.c - SoundWire Bus stream operations.
6
+
*/
7
+
8
+
#include <linux/delay.h>
9
+
#include <linux/device.h>
10
+
#include <linux/init.h>
11
+
#include <linux/module.h>
12
+
#include <linux/mod_devicetable.h>
13
+
#include <linux/slab.h>
14
+
#include <linux/soundwire/sdw_registers.h>
15
+
#include <linux/soundwire/sdw.h>
16
+
#include "bus.h"
17
+
18
+
/*
19
+
* Array of supported rows and columns as per MIPI SoundWire Specification 1.1
20
+
*
21
+
* The rows are arranged as per the array index value programmed
22
+
* in register. The index 15 has dummy value 0 in order to fill hole.
23
+
*/
24
+
int rows[SDW_FRAME_ROWS] = {48, 50, 60, 64, 75, 80, 125, 147,
25
+
96, 100, 120, 128, 150, 160, 250, 0,
26
+
192, 200, 240, 256, 72, 144, 90, 180};
27
+
28
+
int cols[SDW_FRAME_COLS] = {2, 4, 6, 8, 10, 12, 14, 16};
29
+
30
+
static int sdw_find_col_index(int col)
31
+
{
32
+
int i;
33
+
34
+
for (i = 0; i < SDW_FRAME_COLS; i++) {
35
+
if (cols[i] == col)
36
+
return i;
37
+
}
38
+
39
+
pr_warn("Requested column not found, selecting lowest column no: 2\n");
40
+
return 0;
41
+
}
42
+
43
+
static int sdw_find_row_index(int row)
44
+
{
45
+
int i;
46
+
47
+
for (i = 0; i < SDW_FRAME_ROWS; i++) {
48
+
if (rows[i] == row)
49
+
return i;
50
+
}
51
+
52
+
pr_warn("Requested row not found, selecting lowest row no: 48\n");
53
+
return 0;
54
+
}
55
+
static int _sdw_program_slave_port_params(struct sdw_bus *bus,
56
+
struct sdw_slave *slave,
57
+
struct sdw_transport_params *t_params,
58
+
enum sdw_dpn_type type)
59
+
{
60
+
u32 addr1, addr2, addr3, addr4;
61
+
int ret;
62
+
u16 wbuf;
63
+
64
+
if (bus->params.next_bank) {
65
+
addr1 = SDW_DPN_OFFSETCTRL2_B1(t_params->port_num);
66
+
addr2 = SDW_DPN_BLOCKCTRL3_B1(t_params->port_num);
67
+
addr3 = SDW_DPN_SAMPLECTRL2_B1(t_params->port_num);
68
+
addr4 = SDW_DPN_HCTRL_B1(t_params->port_num);
69
+
} else {
70
+
addr1 = SDW_DPN_OFFSETCTRL2_B0(t_params->port_num);
71
+
addr2 = SDW_DPN_BLOCKCTRL3_B0(t_params->port_num);
72
+
addr3 = SDW_DPN_SAMPLECTRL2_B0(t_params->port_num);
73
+
addr4 = SDW_DPN_HCTRL_B0(t_params->port_num);
74
+
}
75
+
76
+
/* Program DPN_OffsetCtrl2 registers */
77
+
ret = sdw_write(slave, addr1, t_params->offset2);
78
+
if (ret < 0) {
79
+
dev_err(bus->dev, "DPN_OffsetCtrl2 register write failed");
80
+
return ret;
81
+
}
82
+
83
+
/* Program DPN_BlockCtrl3 register */
84
+
ret = sdw_write(slave, addr2, t_params->blk_pkg_mode);
85
+
if (ret < 0) {
86
+
dev_err(bus->dev, "DPN_BlockCtrl3 register write failed");
87
+
return ret;
88
+
}
89
+
90
+
/*
91
+
* Data ports are FULL, SIMPLE and REDUCED. This function handles
92
+
* FULL and REDUCED only and and beyond this point only FULL is
93
+
* handled, so bail out if we are not FULL data port type
94
+
*/
95
+
if (type != SDW_DPN_FULL)
96
+
return ret;
97
+
98
+
/* Program DPN_SampleCtrl2 register */
99
+
wbuf = (t_params->sample_interval - 1);
100
+
wbuf &= SDW_DPN_SAMPLECTRL_HIGH;
101
+
wbuf >>= SDW_REG_SHIFT(SDW_DPN_SAMPLECTRL_HIGH);
102
+
103
+
ret = sdw_write(slave, addr3, wbuf);
104
+
if (ret < 0) {
105
+
dev_err(bus->dev, "DPN_SampleCtrl2 register write failed");
106
+
return ret;
107
+
}
108
+
109
+
/* Program DPN_HCtrl register */
110
+
wbuf = t_params->hstart;
111
+
wbuf <<= SDW_REG_SHIFT(SDW_DPN_HCTRL_HSTART);
112
+
wbuf |= t_params->hstop;
113
+
114
+
ret = sdw_write(slave, addr4, wbuf);
115
+
if (ret < 0)
116
+
dev_err(bus->dev, "DPN_HCtrl register write failed");
117
+
118
+
return ret;
119
+
}
120
+
121
+
static int sdw_program_slave_port_params(struct sdw_bus *bus,
122
+
struct sdw_slave_runtime *s_rt,
123
+
struct sdw_port_runtime *p_rt)
124
+
{
125
+
struct sdw_transport_params *t_params = &p_rt->transport_params;
126
+
struct sdw_port_params *p_params = &p_rt->port_params;
127
+
struct sdw_slave_prop *slave_prop = &s_rt->slave->prop;
128
+
u32 addr1, addr2, addr3, addr4, addr5, addr6;
129
+
struct sdw_dpn_prop *dpn_prop;
130
+
int ret;
131
+
u8 wbuf;
132
+
133
+
dpn_prop = sdw_get_slave_dpn_prop(s_rt->slave,
134
+
s_rt->direction,
135
+
t_params->port_num);
136
+
if (!dpn_prop)
137
+
return -EINVAL;
138
+
139
+
addr1 = SDW_DPN_PORTCTRL(t_params->port_num);
140
+
addr2 = SDW_DPN_BLOCKCTRL1(t_params->port_num);
141
+
142
+
if (bus->params.next_bank) {
143
+
addr3 = SDW_DPN_SAMPLECTRL1_B1(t_params->port_num);
144
+
addr4 = SDW_DPN_OFFSETCTRL1_B1(t_params->port_num);
145
+
addr5 = SDW_DPN_BLOCKCTRL2_B1(t_params->port_num);
146
+
addr6 = SDW_DPN_LANECTRL_B1(t_params->port_num);
147
+
148
+
} else {
149
+
addr3 = SDW_DPN_SAMPLECTRL1_B0(t_params->port_num);
150
+
addr4 = SDW_DPN_OFFSETCTRL1_B0(t_params->port_num);
151
+
addr5 = SDW_DPN_BLOCKCTRL2_B0(t_params->port_num);
152
+
addr6 = SDW_DPN_LANECTRL_B0(t_params->port_num);
153
+
}
154
+
155
+
/* Program DPN_PortCtrl register */
156
+
wbuf = p_params->data_mode << SDW_REG_SHIFT(SDW_DPN_PORTCTRL_DATAMODE);
157
+
wbuf |= p_params->flow_mode;
158
+
159
+
ret = sdw_update(s_rt->slave, addr1, 0xF, wbuf);
160
+
if (ret < 0) {
161
+
dev_err(&s_rt->slave->dev,
162
+
"DPN_PortCtrl register write failed for port %d",
163
+
t_params->port_num);
164
+
return ret;
165
+
}
166
+
167
+
/* Program DPN_BlockCtrl1 register */
168
+
ret = sdw_write(s_rt->slave, addr2, (p_params->bps - 1));
169
+
if (ret < 0) {
170
+
dev_err(&s_rt->slave->dev,
171
+
"DPN_BlockCtrl1 register write failed for port %d",
172
+
t_params->port_num);
173
+
return ret;
174
+
}
175
+
176
+
/* Program DPN_SampleCtrl1 register */
177
+
wbuf = (t_params->sample_interval - 1) & SDW_DPN_SAMPLECTRL_LOW;
178
+
ret = sdw_write(s_rt->slave, addr3, wbuf);
179
+
if (ret < 0) {
180
+
dev_err(&s_rt->slave->dev,
181
+
"DPN_SampleCtrl1 register write failed for port %d",
182
+
t_params->port_num);
183
+
return ret;
184
+
}
185
+
186
+
/* Program DPN_OffsetCtrl1 registers */
187
+
ret = sdw_write(s_rt->slave, addr4, t_params->offset1);
188
+
if (ret < 0) {
189
+
dev_err(&s_rt->slave->dev,
190
+
"DPN_OffsetCtrl1 register write failed for port %d",
191
+
t_params->port_num);
192
+
return ret;
193
+
}
194
+
195
+
/* Program DPN_BlockCtrl2 register*/
196
+
if (t_params->blk_grp_ctrl_valid) {
197
+
ret = sdw_write(s_rt->slave, addr5, t_params->blk_grp_ctrl);
198
+
if (ret < 0) {
199
+
dev_err(&s_rt->slave->dev,
200
+
"DPN_BlockCtrl2 reg write failed for port %d",
201
+
t_params->port_num);
202
+
return ret;
203
+
}
204
+
}
205
+
206
+
/* program DPN_LaneCtrl register */
207
+
if (slave_prop->lane_control_support) {
208
+
ret = sdw_write(s_rt->slave, addr6, t_params->lane_ctrl);
209
+
if (ret < 0) {
210
+
dev_err(&s_rt->slave->dev,
211
+
"DPN_LaneCtrl register write failed for port %d",
212
+
t_params->port_num);
213
+
return ret;
214
+
}
215
+
}
216
+
217
+
if (dpn_prop->type != SDW_DPN_SIMPLE) {
218
+
ret = _sdw_program_slave_port_params(bus, s_rt->slave,
219
+
t_params, dpn_prop->type);
220
+
if (ret < 0)
221
+
dev_err(&s_rt->slave->dev,
222
+
"Transport reg write failed for port: %d",
223
+
t_params->port_num);
224
+
}
225
+
226
+
return ret;
227
+
}
228
+
229
+
static int sdw_program_master_port_params(struct sdw_bus *bus,
230
+
struct sdw_port_runtime *p_rt)
231
+
{
232
+
int ret;
233
+
234
+
/*
235
+
* we need to set transport and port parameters for the port.
236
+
* Transport parameters refers to the smaple interval, offsets and
237
+
* hstart/stop etc of the data. Port parameters refers to word
238
+
* length, flow mode etc of the port
239
+
*/
240
+
ret = bus->port_ops->dpn_set_port_transport_params(bus,
241
+
&p_rt->transport_params,
242
+
bus->params.next_bank);
243
+
if (ret < 0)
244
+
return ret;
245
+
246
+
return bus->port_ops->dpn_set_port_params(bus,
247
+
&p_rt->port_params,
248
+
bus->params.next_bank);
249
+
}
250
+
251
+
/**
252
+
* sdw_program_port_params() - Programs transport parameters of Master(s)
253
+
* and Slave(s)
254
+
*
255
+
* @m_rt: Master stream runtime
256
+
*/
257
+
static int sdw_program_port_params(struct sdw_master_runtime *m_rt)
258
+
{
259
+
struct sdw_slave_runtime *s_rt = NULL;
260
+
struct sdw_bus *bus = m_rt->bus;
261
+
struct sdw_port_runtime *p_rt;
262
+
int ret = 0;
263
+
264
+
/* Program transport & port parameters for Slave(s) */
265
+
list_for_each_entry(s_rt, &m_rt->slave_rt_list, m_rt_node) {
266
+
list_for_each_entry(p_rt, &s_rt->port_list, port_node) {
267
+
ret = sdw_program_slave_port_params(bus, s_rt, p_rt);
268
+
if (ret < 0)
269
+
return ret;
270
+
}
271
+
}
272
+
273
+
/* Program transport & port parameters for Master(s) */
274
+
list_for_each_entry(p_rt, &m_rt->port_list, port_node) {
275
+
ret = sdw_program_master_port_params(bus, p_rt);
276
+
if (ret < 0)
277
+
return ret;
278
+
}
279
+
280
+
return 0;
281
+
}
282
+
283
+
/**
284
+
* sdw_enable_disable_slave_ports: Enable/disable slave data port
285
+
*
286
+
* @bus: bus instance
287
+
* @s_rt: slave runtime
288
+
* @p_rt: port runtime
289
+
* @en: enable or disable operation
290
+
*
291
+
* This function only sets the enable/disable bits in the relevant bank, the
292
+
* actual enable/disable is done with a bank switch
293
+
*/
294
+
static int sdw_enable_disable_slave_ports(struct sdw_bus *bus,
295
+
struct sdw_slave_runtime *s_rt,
296
+
struct sdw_port_runtime *p_rt, bool en)
297
+
{
298
+
struct sdw_transport_params *t_params = &p_rt->transport_params;
299
+
u32 addr;
300
+
int ret;
301
+
302
+
if (bus->params.next_bank)
303
+
addr = SDW_DPN_CHANNELEN_B1(p_rt->num);
304
+
else
305
+
addr = SDW_DPN_CHANNELEN_B0(p_rt->num);
306
+
307
+
/*
308
+
* Since bus doesn't support sharing a port across two streams,
309
+
* it is safe to reset this register
310
+
*/
311
+
if (en)
312
+
ret = sdw_update(s_rt->slave, addr, 0xFF, p_rt->ch_mask);
313
+
else
314
+
ret = sdw_update(s_rt->slave, addr, 0xFF, 0x0);
315
+
316
+
if (ret < 0)
317
+
dev_err(&s_rt->slave->dev,
318
+
"Slave chn_en reg write failed:%d port:%d",
319
+
ret, t_params->port_num);
320
+
321
+
return ret;
322
+
}
323
+
324
+
static int sdw_enable_disable_master_ports(struct sdw_master_runtime *m_rt,
325
+
struct sdw_port_runtime *p_rt, bool en)
326
+
{
327
+
struct sdw_transport_params *t_params = &p_rt->transport_params;
328
+
struct sdw_bus *bus = m_rt->bus;
329
+
struct sdw_enable_ch enable_ch;
330
+
int ret = 0;
331
+
332
+
enable_ch.port_num = p_rt->num;
333
+
enable_ch.ch_mask = p_rt->ch_mask;
334
+
enable_ch.enable = en;
335
+
336
+
/* Perform Master port channel(s) enable/disable */
337
+
if (bus->port_ops->dpn_port_enable_ch) {
338
+
ret = bus->port_ops->dpn_port_enable_ch(bus,
339
+
&enable_ch, bus->params.next_bank);
340
+
if (ret < 0) {
341
+
dev_err(bus->dev,
342
+
"Master chn_en write failed:%d port:%d",
343
+
ret, t_params->port_num);
344
+
return ret;
345
+
}
346
+
} else {
347
+
dev_err(bus->dev,
348
+
"dpn_port_enable_ch not supported, %s failed\n",
349
+
en ? "enable" : "disable");
350
+
return -EINVAL;
351
+
}
352
+
353
+
return 0;
354
+
}
355
+
356
+
/**
357
+
* sdw_enable_disable_ports() - Enable/disable port(s) for Master and
358
+
* Slave(s)
359
+
*
360
+
* @m_rt: Master stream runtime
361
+
* @en: mode (enable/disable)
362
+
*/
363
+
static int sdw_enable_disable_ports(struct sdw_master_runtime *m_rt, bool en)
364
+
{
365
+
struct sdw_port_runtime *s_port, *m_port;
366
+
struct sdw_slave_runtime *s_rt = NULL;
367
+
int ret = 0;
368
+
369
+
/* Enable/Disable Slave port(s) */
370
+
list_for_each_entry(s_rt, &m_rt->slave_rt_list, m_rt_node) {
371
+
list_for_each_entry(s_port, &s_rt->port_list, port_node) {
372
+
ret = sdw_enable_disable_slave_ports(m_rt->bus, s_rt,
373
+
s_port, en);
374
+
if (ret < 0)
375
+
return ret;
376
+
}
377
+
}
378
+
379
+
/* Enable/Disable Master port(s) */
380
+
list_for_each_entry(m_port, &m_rt->port_list, port_node) {
381
+
ret = sdw_enable_disable_master_ports(m_rt, m_port, en);
382
+
if (ret < 0)
383
+
return ret;
384
+
}
385
+
386
+
return 0;
387
+
}
388
+
389
+
static int sdw_do_port_prep(struct sdw_slave_runtime *s_rt,
390
+
struct sdw_prepare_ch prep_ch, enum sdw_port_prep_ops cmd)
391
+
{
392
+
const struct sdw_slave_ops *ops = s_rt->slave->ops;
393
+
int ret;
394
+
395
+
if (ops->port_prep) {
396
+
ret = ops->port_prep(s_rt->slave, &prep_ch, cmd);
397
+
if (ret < 0) {
398
+
dev_err(&s_rt->slave->dev,
399
+
"Slave Port Prep cmd %d failed: %d", cmd, ret);
400
+
return ret;
401
+
}
402
+
}
403
+
404
+
return 0;
405
+
}
406
+
407
+
static int sdw_prep_deprep_slave_ports(struct sdw_bus *bus,
408
+
struct sdw_slave_runtime *s_rt,
409
+
struct sdw_port_runtime *p_rt, bool prep)
410
+
{
411
+
struct completion *port_ready = NULL;
412
+
struct sdw_dpn_prop *dpn_prop;
413
+
struct sdw_prepare_ch prep_ch;
414
+
unsigned int time_left;
415
+
bool intr = false;
416
+
int ret = 0, val;
417
+
u32 addr;
418
+
419
+
prep_ch.num = p_rt->num;
420
+
prep_ch.ch_mask = p_rt->ch_mask;
421
+
422
+
dpn_prop = sdw_get_slave_dpn_prop(s_rt->slave,
423
+
s_rt->direction,
424
+
prep_ch.num);
425
+
if (!dpn_prop) {
426
+
dev_err(bus->dev,
427
+
"Slave Port:%d properties not found", prep_ch.num);
428
+
return -EINVAL;
429
+
}
430
+
431
+
prep_ch.prepare = prep;
432
+
433
+
prep_ch.bank = bus->params.next_bank;
434
+
435
+
if (dpn_prop->device_interrupts || !dpn_prop->simple_ch_prep_sm)
436
+
intr = true;
437
+
438
+
/*
439
+
* Enable interrupt before Port prepare.
440
+
* For Port de-prepare, it is assumed that port
441
+
* was prepared earlier
442
+
*/
443
+
if (prep && intr) {
444
+
ret = sdw_configure_dpn_intr(s_rt->slave, p_rt->num, prep,
445
+
dpn_prop->device_interrupts);
446
+
if (ret < 0)
447
+
return ret;
448
+
}
449
+
450
+
/* Inform slave about the impending port prepare */
451
+
sdw_do_port_prep(s_rt, prep_ch, SDW_OPS_PORT_PRE_PREP);
452
+
453
+
/* Prepare Slave port implementing CP_SM */
454
+
if (!dpn_prop->simple_ch_prep_sm) {
455
+
addr = SDW_DPN_PREPARECTRL(p_rt->num);
456
+
457
+
if (prep)
458
+
ret = sdw_update(s_rt->slave, addr,
459
+
0xFF, p_rt->ch_mask);
460
+
else
461
+
ret = sdw_update(s_rt->slave, addr, 0xFF, 0x0);
462
+
463
+
if (ret < 0) {
464
+
dev_err(&s_rt->slave->dev,
465
+
"Slave prep_ctrl reg write failed");
466
+
return ret;
467
+
}
468
+
469
+
/* Wait for completion on port ready */
470
+
port_ready = &s_rt->slave->port_ready[prep_ch.num];
471
+
time_left = wait_for_completion_timeout(port_ready,
472
+
msecs_to_jiffies(dpn_prop->ch_prep_timeout));
473
+
474
+
val = sdw_read(s_rt->slave, SDW_DPN_PREPARESTATUS(p_rt->num));
475
+
val &= p_rt->ch_mask;
476
+
if (!time_left || val) {
477
+
dev_err(&s_rt->slave->dev,
478
+
"Chn prep failed for port:%d", prep_ch.num);
479
+
return -ETIMEDOUT;
480
+
}
481
+
}
482
+
483
+
/* Inform slaves about ports prepared */
484
+
sdw_do_port_prep(s_rt, prep_ch, SDW_OPS_PORT_POST_PREP);
485
+
486
+
/* Disable interrupt after Port de-prepare */
487
+
if (!prep && intr)
488
+
ret = sdw_configure_dpn_intr(s_rt->slave, p_rt->num, prep,
489
+
dpn_prop->device_interrupts);
490
+
491
+
return ret;
492
+
}
493
+
494
+
static int sdw_prep_deprep_master_ports(struct sdw_master_runtime *m_rt,
495
+
struct sdw_port_runtime *p_rt, bool prep)
496
+
{
497
+
struct sdw_transport_params *t_params = &p_rt->transport_params;
498
+
struct sdw_bus *bus = m_rt->bus;
499
+
const struct sdw_master_port_ops *ops = bus->port_ops;
500
+
struct sdw_prepare_ch prep_ch;
501
+
int ret = 0;
502
+
503
+
prep_ch.num = p_rt->num;
504
+
prep_ch.ch_mask = p_rt->ch_mask;
505
+
prep_ch.prepare = prep; /* Prepare/De-prepare */
506
+
prep_ch.bank = bus->params.next_bank;
507
+
508
+
/* Pre-prepare/Pre-deprepare port(s) */
509
+
if (ops->dpn_port_prep) {
510
+
ret = ops->dpn_port_prep(bus, &prep_ch);
511
+
if (ret < 0) {
512
+
dev_err(bus->dev, "Port prepare failed for port:%d",
513
+
t_params->port_num);
514
+
return ret;
515
+
}
516
+
}
517
+
518
+
return ret;
519
+
}
520
+
521
+
/**
522
+
* sdw_prep_deprep_ports() - Prepare/De-prepare port(s) for Master(s) and
523
+
* Slave(s)
524
+
*
525
+
* @m_rt: Master runtime handle
526
+
* @prep: Prepare or De-prepare
527
+
*/
528
+
static int sdw_prep_deprep_ports(struct sdw_master_runtime *m_rt, bool prep)
529
+
{
530
+
struct sdw_slave_runtime *s_rt = NULL;
531
+
struct sdw_port_runtime *p_rt;
532
+
int ret = 0;
533
+
534
+
/* Prepare/De-prepare Slave port(s) */
535
+
list_for_each_entry(s_rt, &m_rt->slave_rt_list, m_rt_node) {
536
+
list_for_each_entry(p_rt, &s_rt->port_list, port_node) {
537
+
ret = sdw_prep_deprep_slave_ports(m_rt->bus, s_rt,
538
+
p_rt, prep);
539
+
if (ret < 0)
540
+
return ret;
541
+
}
542
+
}
543
+
544
+
/* Prepare/De-prepare Master port(s) */
545
+
list_for_each_entry(p_rt, &m_rt->port_list, port_node) {
546
+
ret = sdw_prep_deprep_master_ports(m_rt, p_rt, prep);
547
+
if (ret < 0)
548
+
return ret;
549
+
}
550
+
551
+
return ret;
552
+
}
553
+
554
+
/**
555
+
* sdw_notify_config() - Notify bus configuration
556
+
*
557
+
* @m_rt: Master runtime handle
558
+
*
559
+
* This function notifies the Master(s) and Slave(s) of the
560
+
* new bus configuration.
561
+
*/
562
+
static int sdw_notify_config(struct sdw_master_runtime *m_rt)
563
+
{
564
+
struct sdw_slave_runtime *s_rt;
565
+
struct sdw_bus *bus = m_rt->bus;
566
+
struct sdw_slave *slave;
567
+
int ret = 0;
568
+
569
+
if (bus->ops->set_bus_conf) {
570
+
ret = bus->ops->set_bus_conf(bus, &bus->params);
571
+
if (ret < 0)
572
+
return ret;
573
+
}
574
+
575
+
list_for_each_entry(s_rt, &m_rt->slave_rt_list, m_rt_node) {
576
+
slave = s_rt->slave;
577
+
578
+
if (slave->ops->bus_config) {
579
+
ret = slave->ops->bus_config(slave, &bus->params);
580
+
if (ret < 0)
581
+
dev_err(bus->dev, "Notify Slave: %d failed",
582
+
slave->dev_num);
583
+
return ret;
584
+
}
585
+
}
586
+
587
+
return ret;
588
+
}
589
+
590
+
/**
591
+
* sdw_program_params() - Program transport and port parameters for Master(s)
592
+
* and Slave(s)
593
+
*
594
+
* @bus: SDW bus instance
595
+
*/
596
+
static int sdw_program_params(struct sdw_bus *bus)
597
+
{
598
+
struct sdw_master_runtime *m_rt = NULL;
599
+
int ret = 0;
600
+
601
+
list_for_each_entry(m_rt, &bus->m_rt_list, bus_node) {
602
+
ret = sdw_program_port_params(m_rt);
603
+
if (ret < 0) {
604
+
dev_err(bus->dev,
605
+
"Program transport params failed: %d", ret);
606
+
return ret;
607
+
}
608
+
609
+
ret = sdw_notify_config(m_rt);
610
+
if (ret < 0) {
611
+
dev_err(bus->dev, "Notify bus config failed: %d", ret);
612
+
return ret;
613
+
}
614
+
615
+
/* Enable port(s) on alternate bank for all active streams */
616
+
if (m_rt->stream->state != SDW_STREAM_ENABLED)
617
+
continue;
618
+
619
+
ret = sdw_enable_disable_ports(m_rt, true);
620
+
if (ret < 0) {
621
+
dev_err(bus->dev, "Enable channel failed: %d", ret);
622
+
return ret;
623
+
}
624
+
}
625
+
626
+
return ret;
627
+
}
628
+
629
+
static int sdw_bank_switch(struct sdw_bus *bus)
630
+
{
631
+
int col_index, row_index;
632
+
struct sdw_msg *wr_msg;
633
+
u8 *wbuf = NULL;
634
+
int ret = 0;
635
+
u16 addr;
636
+
637
+
wr_msg = kzalloc(sizeof(*wr_msg), GFP_KERNEL);
638
+
if (!wr_msg)
639
+
return -ENOMEM;
640
+
641
+
wbuf = kzalloc(sizeof(*wbuf), GFP_KERNEL);
642
+
if (!wbuf) {
643
+
ret = -ENOMEM;
644
+
goto error_1;
645
+
}
646
+
647
+
/* Get row and column index to program register */
648
+
col_index = sdw_find_col_index(bus->params.col);
649
+
row_index = sdw_find_row_index(bus->params.row);
650
+
wbuf[0] = col_index | (row_index << 3);
651
+
652
+
if (bus->params.next_bank)
653
+
addr = SDW_SCP_FRAMECTRL_B1;
654
+
else
655
+
addr = SDW_SCP_FRAMECTRL_B0;
656
+
657
+
sdw_fill_msg(wr_msg, NULL, addr, 1, SDW_BROADCAST_DEV_NUM,
658
+
SDW_MSG_FLAG_WRITE, wbuf);
659
+
wr_msg->ssp_sync = true;
660
+
661
+
ret = sdw_transfer(bus, wr_msg);
662
+
if (ret < 0) {
663
+
dev_err(bus->dev, "Slave frame_ctrl reg write failed");
664
+
goto error;
665
+
}
666
+
667
+
kfree(wr_msg);
668
+
kfree(wbuf);
669
+
bus->defer_msg.msg = NULL;
670
+
bus->params.curr_bank = !bus->params.curr_bank;
671
+
bus->params.next_bank = !bus->params.next_bank;
672
+
673
+
return 0;
674
+
675
+
error:
676
+
kfree(wbuf);
677
+
error_1:
678
+
kfree(wr_msg);
679
+
return ret;
680
+
}
681
+
682
+
static int do_bank_switch(struct sdw_stream_runtime *stream)
683
+
{
684
+
struct sdw_master_runtime *m_rt = stream->m_rt;
685
+
const struct sdw_master_ops *ops;
686
+
struct sdw_bus *bus = m_rt->bus;
687
+
int ret = 0;
688
+
689
+
ops = bus->ops;
690
+
691
+
/* Pre-bank switch */
692
+
if (ops->pre_bank_switch) {
693
+
ret = ops->pre_bank_switch(bus);
694
+
if (ret < 0) {
695
+
dev_err(bus->dev, "Pre bank switch op failed: %d", ret);
696
+
return ret;
697
+
}
698
+
}
699
+
700
+
/* Bank switch */
701
+
ret = sdw_bank_switch(bus);
702
+
if (ret < 0) {
703
+
dev_err(bus->dev, "Bank switch failed: %d", ret);
704
+
return ret;
705
+
}
706
+
707
+
/* Post-bank switch */
708
+
if (ops->post_bank_switch) {
709
+
ret = ops->post_bank_switch(bus);
710
+
if (ret < 0) {
711
+
dev_err(bus->dev,
712
+
"Post bank switch op failed: %d", ret);
713
+
}
714
+
}
715
+
716
+
return ret;
717
+
}
718
+
719
+
/**
720
+
* sdw_release_stream() - Free the assigned stream runtime
721
+
*
722
+
* @stream: SoundWire stream runtime
723
+
*
724
+
* sdw_release_stream should be called only once per stream
725
+
*/
726
+
void sdw_release_stream(struct sdw_stream_runtime *stream)
727
+
{
728
+
kfree(stream);
729
+
}
730
+
EXPORT_SYMBOL(sdw_release_stream);
731
+
732
+
/**
733
+
* sdw_alloc_stream() - Allocate and return stream runtime
734
+
*
735
+
* @stream_name: SoundWire stream name
736
+
*
737
+
* Allocates a SoundWire stream runtime instance.
738
+
* sdw_alloc_stream should be called only once per stream. Typically
739
+
* invoked from ALSA/ASoC machine/platform driver.
740
+
*/
741
+
struct sdw_stream_runtime *sdw_alloc_stream(char *stream_name)
742
+
{
743
+
struct sdw_stream_runtime *stream;
744
+
745
+
stream = kzalloc(sizeof(*stream), GFP_KERNEL);
746
+
if (!stream)
747
+
return NULL;
748
+
749
+
stream->name = stream_name;
750
+
stream->state = SDW_STREAM_ALLOCATED;
751
+
752
+
return stream;
753
+
}
754
+
EXPORT_SYMBOL(sdw_alloc_stream);
755
+
756
+
/**
757
+
* sdw_alloc_master_rt() - Allocates and initialize Master runtime handle
758
+
*
759
+
* @bus: SDW bus instance
760
+
* @stream_config: Stream configuration
761
+
* @stream: Stream runtime handle.
762
+
*
763
+
* This function is to be called with bus_lock held.
764
+
*/
765
+
static struct sdw_master_runtime
766
+
*sdw_alloc_master_rt(struct sdw_bus *bus,
767
+
struct sdw_stream_config *stream_config,
768
+
struct sdw_stream_runtime *stream)
769
+
{
770
+
struct sdw_master_runtime *m_rt;
771
+
772
+
m_rt = stream->m_rt;
773
+
774
+
/*
775
+
* check if Master is already allocated (as a result of Slave adding
776
+
* it first), if so skip allocation and go to configure
777
+
*/
778
+
if (m_rt)
779
+
goto stream_config;
780
+
781
+
m_rt = kzalloc(sizeof(*m_rt), GFP_KERNEL);
782
+
if (!m_rt)
783
+
return NULL;
784
+
785
+
/* Initialization of Master runtime handle */
786
+
INIT_LIST_HEAD(&m_rt->port_list);
787
+
INIT_LIST_HEAD(&m_rt->slave_rt_list);
788
+
stream->m_rt = m_rt;
789
+
790
+
list_add_tail(&m_rt->bus_node, &bus->m_rt_list);
791
+
792
+
stream_config:
793
+
m_rt->ch_count = stream_config->ch_count;
794
+
m_rt->bus = bus;
795
+
m_rt->stream = stream;
796
+
m_rt->direction = stream_config->direction;
797
+
798
+
return m_rt;
799
+
}
800
+
801
+
/**
802
+
* sdw_alloc_slave_rt() - Allocate and initialize Slave runtime handle.
803
+
*
804
+
* @slave: Slave handle
805
+
* @stream_config: Stream configuration
806
+
* @stream: Stream runtime handle
807
+
*
808
+
* This function is to be called with bus_lock held.
809
+
*/
810
+
static struct sdw_slave_runtime
811
+
*sdw_alloc_slave_rt(struct sdw_slave *slave,
812
+
struct sdw_stream_config *stream_config,
813
+
struct sdw_stream_runtime *stream)
814
+
{
815
+
struct sdw_slave_runtime *s_rt = NULL;
816
+
817
+
s_rt = kzalloc(sizeof(*s_rt), GFP_KERNEL);
818
+
if (!s_rt)
819
+
return NULL;
820
+
821
+
INIT_LIST_HEAD(&s_rt->port_list);
822
+
s_rt->ch_count = stream_config->ch_count;
823
+
s_rt->direction = stream_config->direction;
824
+
s_rt->slave = slave;
825
+
826
+
return s_rt;
827
+
}
828
+
829
+
static void sdw_master_port_release(struct sdw_bus *bus,
830
+
struct sdw_master_runtime *m_rt)
831
+
{
832
+
struct sdw_port_runtime *p_rt, *_p_rt;
833
+
834
+
list_for_each_entry_safe(p_rt, _p_rt,
835
+
&m_rt->port_list, port_node) {
836
+
list_del(&p_rt->port_node);
837
+
kfree(p_rt);
838
+
}
839
+
}
840
+
841
+
static void sdw_slave_port_release(struct sdw_bus *bus,
842
+
struct sdw_slave *slave,
843
+
struct sdw_stream_runtime *stream)
844
+
{
845
+
struct sdw_port_runtime *p_rt, *_p_rt;
846
+
struct sdw_master_runtime *m_rt = stream->m_rt;
847
+
struct sdw_slave_runtime *s_rt;
848
+
849
+
list_for_each_entry(s_rt, &m_rt->slave_rt_list, m_rt_node) {
850
+
if (s_rt->slave != slave)
851
+
continue;
852
+
853
+
list_for_each_entry_safe(p_rt, _p_rt,
854
+
&s_rt->port_list, port_node) {
855
+
list_del(&p_rt->port_node);
856
+
kfree(p_rt);
857
+
}
858
+
}
859
+
}
860
+
861
+
/**
862
+
* sdw_release_slave_stream() - Free Slave(s) runtime handle
863
+
*
864
+
* @slave: Slave handle.
865
+
* @stream: Stream runtime handle.
866
+
*
867
+
* This function is to be called with bus_lock held.
868
+
*/
869
+
static void sdw_release_slave_stream(struct sdw_slave *slave,
870
+
struct sdw_stream_runtime *stream)
871
+
{
872
+
struct sdw_slave_runtime *s_rt, *_s_rt;
873
+
struct sdw_master_runtime *m_rt = stream->m_rt;
874
+
875
+
/* Retrieve Slave runtime handle */
876
+
list_for_each_entry_safe(s_rt, _s_rt,
877
+
&m_rt->slave_rt_list, m_rt_node) {
878
+
879
+
if (s_rt->slave == slave) {
880
+
list_del(&s_rt->m_rt_node);
881
+
kfree(s_rt);
882
+
return;
883
+
}
884
+
}
885
+
}
886
+
887
+
/**
888
+
* sdw_release_master_stream() - Free Master runtime handle
889
+
*
890
+
* @stream: Stream runtime handle.
891
+
*
892
+
* This function is to be called with bus_lock held
893
+
* It frees the Master runtime handle and associated Slave(s) runtime
894
+
* handle. If this is called first then sdw_release_slave_stream() will have
895
+
* no effect as Slave(s) runtime handle would already be freed up.
896
+
*/
897
+
static void sdw_release_master_stream(struct sdw_stream_runtime *stream)
898
+
{
899
+
struct sdw_master_runtime *m_rt = stream->m_rt;
900
+
struct sdw_slave_runtime *s_rt, *_s_rt;
901
+
902
+
list_for_each_entry_safe(s_rt, _s_rt,
903
+
&m_rt->slave_rt_list, m_rt_node)
904
+
sdw_stream_remove_slave(s_rt->slave, stream);
905
+
906
+
list_del(&m_rt->bus_node);
907
+
}
908
+
909
+
/**
910
+
* sdw_stream_remove_master() - Remove master from sdw_stream
911
+
*
912
+
* @bus: SDW Bus instance
913
+
* @stream: SoundWire stream
914
+
*
915
+
* This removes and frees port_rt and master_rt from a stream
916
+
*/
917
+
int sdw_stream_remove_master(struct sdw_bus *bus,
918
+
struct sdw_stream_runtime *stream)
919
+
{
920
+
mutex_lock(&bus->bus_lock);
921
+
922
+
sdw_release_master_stream(stream);
923
+
sdw_master_port_release(bus, stream->m_rt);
924
+
stream->state = SDW_STREAM_RELEASED;
925
+
kfree(stream->m_rt);
926
+
stream->m_rt = NULL;
927
+
928
+
mutex_unlock(&bus->bus_lock);
929
+
930
+
return 0;
931
+
}
932
+
EXPORT_SYMBOL(sdw_stream_remove_master);
933
+
934
+
/**
935
+
* sdw_stream_remove_slave() - Remove slave from sdw_stream
936
+
*
937
+
* @slave: SDW Slave instance
938
+
* @stream: SoundWire stream
939
+
*
940
+
* This removes and frees port_rt and slave_rt from a stream
941
+
*/
942
+
int sdw_stream_remove_slave(struct sdw_slave *slave,
943
+
struct sdw_stream_runtime *stream)
944
+
{
945
+
mutex_lock(&slave->bus->bus_lock);
946
+
947
+
sdw_slave_port_release(slave->bus, slave, stream);
948
+
sdw_release_slave_stream(slave, stream);
949
+
950
+
mutex_unlock(&slave->bus->bus_lock);
951
+
952
+
return 0;
953
+
}
954
+
EXPORT_SYMBOL(sdw_stream_remove_slave);
955
+
956
+
/**
957
+
* sdw_config_stream() - Configure the allocated stream
958
+
*
959
+
* @dev: SDW device
960
+
* @stream: SoundWire stream
961
+
* @stream_config: Stream configuration for audio stream
962
+
* @is_slave: is API called from Slave or Master
963
+
*
964
+
* This function is to be called with bus_lock held.
965
+
*/
966
+
static int sdw_config_stream(struct device *dev,
967
+
struct sdw_stream_runtime *stream,
968
+
struct sdw_stream_config *stream_config, bool is_slave)
969
+
{
970
+
/*
971
+
* Update the stream rate, channel and bps based on data
972
+
* source. For more than one data source (multilink),
973
+
* match the rate, bps, stream type and increment number of channels.
974
+
*
975
+
* If rate/bps is zero, it means the values are not set, so skip
976
+
* comparison and allow the value to be set and stored in stream
977
+
*/
978
+
if (stream->params.rate &&
979
+
stream->params.rate != stream_config->frame_rate) {
980
+
dev_err(dev, "rate not matching, stream:%s", stream->name);
981
+
return -EINVAL;
982
+
}
983
+
984
+
if (stream->params.bps &&
985
+
stream->params.bps != stream_config->bps) {
986
+
dev_err(dev, "bps not matching, stream:%s", stream->name);
987
+
return -EINVAL;
988
+
}
989
+
990
+
stream->type = stream_config->type;
991
+
stream->params.rate = stream_config->frame_rate;
992
+
stream->params.bps = stream_config->bps;
993
+
994
+
/* TODO: Update this check during Device-device support */
995
+
if (is_slave)
996
+
stream->params.ch_count += stream_config->ch_count;
997
+
998
+
return 0;
999
+
}
1000
+
1001
+
static int sdw_is_valid_port_range(struct device *dev,
1002
+
struct sdw_port_runtime *p_rt)
1003
+
{
1004
+
if (!SDW_VALID_PORT_RANGE(p_rt->num)) {
1005
+
dev_err(dev,
1006
+
"SoundWire: Invalid port number :%d", p_rt->num);
1007
+
return -EINVAL;
1008
+
}
1009
+
1010
+
return 0;
1011
+
}
1012
+
1013
+
static struct sdw_port_runtime *sdw_port_alloc(struct device *dev,
1014
+
struct sdw_port_config *port_config,
1015
+
int port_index)
1016
+
{
1017
+
struct sdw_port_runtime *p_rt;
1018
+
1019
+
p_rt = kzalloc(sizeof(*p_rt), GFP_KERNEL);
1020
+
if (!p_rt)
1021
+
return NULL;
1022
+
1023
+
p_rt->ch_mask = port_config[port_index].ch_mask;
1024
+
p_rt->num = port_config[port_index].num;
1025
+
1026
+
return p_rt;
1027
+
}
1028
+
1029
+
static int sdw_master_port_config(struct sdw_bus *bus,
1030
+
struct sdw_master_runtime *m_rt,
1031
+
struct sdw_port_config *port_config,
1032
+
unsigned int num_ports)
1033
+
{
1034
+
struct sdw_port_runtime *p_rt;
1035
+
int i;
1036
+
1037
+
/* Iterate for number of ports to perform initialization */
1038
+
for (i = 0; i < num_ports; i++) {
1039
+
p_rt = sdw_port_alloc(bus->dev, port_config, i);
1040
+
if (!p_rt)
1041
+
return -ENOMEM;
1042
+
1043
+
/*
1044
+
* TODO: Check port capabilities for requested
1045
+
* configuration (audio mode support)
1046
+
*/
1047
+
1048
+
list_add_tail(&p_rt->port_node, &m_rt->port_list);
1049
+
}
1050
+
1051
+
return 0;
1052
+
}
1053
+
1054
+
static int sdw_slave_port_config(struct sdw_slave *slave,
1055
+
struct sdw_slave_runtime *s_rt,
1056
+
struct sdw_port_config *port_config,
1057
+
unsigned int num_config)
1058
+
{
1059
+
struct sdw_port_runtime *p_rt;
1060
+
int i, ret;
1061
+
1062
+
/* Iterate for number of ports to perform initialization */
1063
+
for (i = 0; i < num_config; i++) {
1064
+
p_rt = sdw_port_alloc(&slave->dev, port_config, i);
1065
+
if (!p_rt)
1066
+
return -ENOMEM;
1067
+
1068
+
/*
1069
+
* TODO: Check valid port range as defined by DisCo/
1070
+
* slave
1071
+
*/
1072
+
ret = sdw_is_valid_port_range(&slave->dev, p_rt);
1073
+
if (ret < 0) {
1074
+
kfree(p_rt);
1075
+
return ret;
1076
+
}
1077
+
1078
+
/*
1079
+
* TODO: Check port capabilities for requested
1080
+
* configuration (audio mode support)
1081
+
*/
1082
+
1083
+
list_add_tail(&p_rt->port_node, &s_rt->port_list);
1084
+
}
1085
+
1086
+
return 0;
1087
+
}
1088
+
1089
+
/**
1090
+
* sdw_stream_add_master() - Allocate and add master runtime to a stream
1091
+
*
1092
+
* @bus: SDW Bus instance
1093
+
* @stream_config: Stream configuration for audio stream
1094
+
* @port_config: Port configuration for audio stream
1095
+
* @num_ports: Number of ports
1096
+
* @stream: SoundWire stream
1097
+
*/
1098
+
int sdw_stream_add_master(struct sdw_bus *bus,
1099
+
struct sdw_stream_config *stream_config,
1100
+
struct sdw_port_config *port_config,
1101
+
unsigned int num_ports,
1102
+
struct sdw_stream_runtime *stream)
1103
+
{
1104
+
struct sdw_master_runtime *m_rt = NULL;
1105
+
int ret;
1106
+
1107
+
mutex_lock(&bus->bus_lock);
1108
+
1109
+
m_rt = sdw_alloc_master_rt(bus, stream_config, stream);
1110
+
if (!m_rt) {
1111
+
dev_err(bus->dev,
1112
+
"Master runtime config failed for stream:%s",
1113
+
stream->name);
1114
+
ret = -ENOMEM;
1115
+
goto error;
1116
+
}
1117
+
1118
+
ret = sdw_config_stream(bus->dev, stream, stream_config, false);
1119
+
if (ret)
1120
+
goto stream_error;
1121
+
1122
+
ret = sdw_master_port_config(bus, m_rt, port_config, num_ports);
1123
+
if (ret)
1124
+
goto stream_error;
1125
+
1126
+
stream->state = SDW_STREAM_CONFIGURED;
1127
+
1128
+
stream_error:
1129
+
sdw_release_master_stream(stream);
1130
+
error:
1131
+
mutex_unlock(&bus->bus_lock);
1132
+
return ret;
1133
+
}
1134
+
EXPORT_SYMBOL(sdw_stream_add_master);
1135
+
1136
+
/**
1137
+
* sdw_stream_add_slave() - Allocate and add master/slave runtime to a stream
1138
+
*
1139
+
* @slave: SDW Slave instance
1140
+
* @stream_config: Stream configuration for audio stream
1141
+
* @stream: SoundWire stream
1142
+
* @port_config: Port configuration for audio stream
1143
+
* @num_ports: Number of ports
1144
+
*/
1145
+
int sdw_stream_add_slave(struct sdw_slave *slave,
1146
+
struct sdw_stream_config *stream_config,
1147
+
struct sdw_port_config *port_config,
1148
+
unsigned int num_ports,
1149
+
struct sdw_stream_runtime *stream)
1150
+
{
1151
+
struct sdw_slave_runtime *s_rt;
1152
+
struct sdw_master_runtime *m_rt;
1153
+
int ret;
1154
+
1155
+
mutex_lock(&slave->bus->bus_lock);
1156
+
1157
+
/*
1158
+
* If this API is invoked by Slave first then m_rt is not valid.
1159
+
* So, allocate m_rt and add Slave to it.
1160
+
*/
1161
+
m_rt = sdw_alloc_master_rt(slave->bus, stream_config, stream);
1162
+
if (!m_rt) {
1163
+
dev_err(&slave->dev,
1164
+
"alloc master runtime failed for stream:%s",
1165
+
stream->name);
1166
+
ret = -ENOMEM;
1167
+
goto error;
1168
+
}
1169
+
1170
+
s_rt = sdw_alloc_slave_rt(slave, stream_config, stream);
1171
+
if (!s_rt) {
1172
+
dev_err(&slave->dev,
1173
+
"Slave runtime config failed for stream:%s",
1174
+
stream->name);
1175
+
ret = -ENOMEM;
1176
+
goto stream_error;
1177
+
}
1178
+
1179
+
ret = sdw_config_stream(&slave->dev, stream, stream_config, true);
1180
+
if (ret)
1181
+
goto stream_error;
1182
+
1183
+
list_add_tail(&s_rt->m_rt_node, &m_rt->slave_rt_list);
1184
+
1185
+
ret = sdw_slave_port_config(slave, s_rt, port_config, num_ports);
1186
+
if (ret)
1187
+
goto stream_error;
1188
+
1189
+
stream->state = SDW_STREAM_CONFIGURED;
1190
+
goto error;
1191
+
1192
+
stream_error:
1193
+
/*
1194
+
* we hit error so cleanup the stream, release all Slave(s) and
1195
+
* Master runtime
1196
+
*/
1197
+
sdw_release_master_stream(stream);
1198
+
error:
1199
+
mutex_unlock(&slave->bus->bus_lock);
1200
+
return ret;
1201
+
}
1202
+
EXPORT_SYMBOL(sdw_stream_add_slave);
1203
+
1204
+
/**
1205
+
* sdw_get_slave_dpn_prop() - Get Slave port capabilities
1206
+
*
1207
+
* @slave: Slave handle
1208
+
* @direction: Data direction.
1209
+
* @port_num: Port number
1210
+
*/
1211
+
struct sdw_dpn_prop *sdw_get_slave_dpn_prop(struct sdw_slave *slave,
1212
+
enum sdw_data_direction direction,
1213
+
unsigned int port_num)
1214
+
{
1215
+
struct sdw_dpn_prop *dpn_prop;
1216
+
u8 num_ports;
1217
+
int i;
1218
+
1219
+
if (direction == SDW_DATA_DIR_TX) {
1220
+
num_ports = hweight32(slave->prop.source_ports);
1221
+
dpn_prop = slave->prop.src_dpn_prop;
1222
+
} else {
1223
+
num_ports = hweight32(slave->prop.sink_ports);
1224
+
dpn_prop = slave->prop.sink_dpn_prop;
1225
+
}
1226
+
1227
+
for (i = 0; i < num_ports; i++) {
1228
+
dpn_prop = &dpn_prop[i];
1229
+
1230
+
if (dpn_prop->num == port_num)
1231
+
return &dpn_prop[i];
1232
+
}
1233
+
1234
+
return NULL;
1235
+
}
1236
+
1237
+
static int _sdw_prepare_stream(struct sdw_stream_runtime *stream)
1238
+
{
1239
+
struct sdw_master_runtime *m_rt = stream->m_rt;
1240
+
struct sdw_bus *bus = m_rt->bus;
1241
+
struct sdw_master_prop *prop = NULL;
1242
+
struct sdw_bus_params params;
1243
+
int ret;
1244
+
1245
+
prop = &bus->prop;
1246
+
memcpy(¶ms, &bus->params, sizeof(params));
1247
+
1248
+
/* TODO: Support Asynchronous mode */
1249
+
if ((prop->max_freq % stream->params.rate) != 0) {
1250
+
dev_err(bus->dev, "Async mode not supported");
1251
+
return -EINVAL;
1252
+
}
1253
+
1254
+
/* Increment cumulative bus bandwidth */
1255
+
/* TODO: Update this during Device-Device support */
1256
+
bus->params.bandwidth += m_rt->stream->params.rate *
1257
+
m_rt->ch_count * m_rt->stream->params.bps;
1258
+
1259
+
/* Program params */
1260
+
ret = sdw_program_params(bus);
1261
+
if (ret < 0) {
1262
+
dev_err(bus->dev, "Program params failed: %d", ret);
1263
+
goto restore_params;
1264
+
}
1265
+
1266
+
ret = do_bank_switch(stream);
1267
+
if (ret < 0) {
1268
+
dev_err(bus->dev, "Bank switch failed: %d", ret);
1269
+
goto restore_params;
1270
+
}
1271
+
1272
+
/* Prepare port(s) on the new clock configuration */
1273
+
ret = sdw_prep_deprep_ports(m_rt, true);
1274
+
if (ret < 0) {
1275
+
dev_err(bus->dev, "Prepare port(s) failed ret = %d",
1276
+
ret);
1277
+
return ret;
1278
+
}
1279
+
1280
+
stream->state = SDW_STREAM_PREPARED;
1281
+
1282
+
return ret;
1283
+
1284
+
restore_params:
1285
+
memcpy(&bus->params, ¶ms, sizeof(params));
1286
+
return ret;
1287
+
}
1288
+
1289
+
/**
1290
+
* sdw_prepare_stream() - Prepare SoundWire stream
1291
+
*
1292
+
* @stream: Soundwire stream
1293
+
*
1294
+
* Documentation/soundwire/stream.txt explains this API in detail
1295
+
*/
1296
+
int sdw_prepare_stream(struct sdw_stream_runtime *stream)
1297
+
{
1298
+
int ret = 0;
1299
+
1300
+
if (!stream) {
1301
+
pr_err("SoundWire: Handle not found for stream");
1302
+
return -EINVAL;
1303
+
}
1304
+
1305
+
mutex_lock(&stream->m_rt->bus->bus_lock);
1306
+
1307
+
ret = _sdw_prepare_stream(stream);
1308
+
if (ret < 0)
1309
+
pr_err("Prepare for stream:%s failed: %d", stream->name, ret);
1310
+
1311
+
mutex_unlock(&stream->m_rt->bus->bus_lock);
1312
+
return ret;
1313
+
}
1314
+
EXPORT_SYMBOL(sdw_prepare_stream);
1315
+
1316
+
static int _sdw_enable_stream(struct sdw_stream_runtime *stream)
1317
+
{
1318
+
struct sdw_master_runtime *m_rt = stream->m_rt;
1319
+
struct sdw_bus *bus = m_rt->bus;
1320
+
int ret;
1321
+
1322
+
/* Program params */
1323
+
ret = sdw_program_params(bus);
1324
+
if (ret < 0) {
1325
+
dev_err(bus->dev, "Program params failed: %d", ret);
1326
+
return ret;
1327
+
}
1328
+
1329
+
/* Enable port(s) */
1330
+
ret = sdw_enable_disable_ports(m_rt, true);
1331
+
if (ret < 0) {
1332
+
dev_err(bus->dev, "Enable port(s) failed ret: %d", ret);
1333
+
return ret;
1334
+
}
1335
+
1336
+
ret = do_bank_switch(stream);
1337
+
if (ret < 0) {
1338
+
dev_err(bus->dev, "Bank switch failed: %d", ret);
1339
+
return ret;
1340
+
}
1341
+
1342
+
stream->state = SDW_STREAM_ENABLED;
1343
+
return 0;
1344
+
}
1345
+
1346
+
/**
1347
+
* sdw_enable_stream() - Enable SoundWire stream
1348
+
*
1349
+
* @stream: Soundwire stream
1350
+
*
1351
+
* Documentation/soundwire/stream.txt explains this API in detail
1352
+
*/
1353
+
int sdw_enable_stream(struct sdw_stream_runtime *stream)
1354
+
{
1355
+
int ret = 0;
1356
+
1357
+
if (!stream) {
1358
+
pr_err("SoundWire: Handle not found for stream");
1359
+
return -EINVAL;
1360
+
}
1361
+
1362
+
mutex_lock(&stream->m_rt->bus->bus_lock);
1363
+
1364
+
ret = _sdw_enable_stream(stream);
1365
+
if (ret < 0)
1366
+
pr_err("Enable for stream:%s failed: %d", stream->name, ret);
1367
+
1368
+
mutex_unlock(&stream->m_rt->bus->bus_lock);
1369
+
return ret;
1370
+
}
1371
+
EXPORT_SYMBOL(sdw_enable_stream);
1372
+
1373
+
static int _sdw_disable_stream(struct sdw_stream_runtime *stream)
1374
+
{
1375
+
struct sdw_master_runtime *m_rt = stream->m_rt;
1376
+
struct sdw_bus *bus = m_rt->bus;
1377
+
int ret;
1378
+
1379
+
/* Disable port(s) */
1380
+
ret = sdw_enable_disable_ports(m_rt, false);
1381
+
if (ret < 0) {
1382
+
dev_err(bus->dev, "Disable port(s) failed: %d", ret);
1383
+
return ret;
1384
+
}
1385
+
1386
+
stream->state = SDW_STREAM_DISABLED;
1387
+
1388
+
/* Program params */
1389
+
ret = sdw_program_params(bus);
1390
+
if (ret < 0) {
1391
+
dev_err(bus->dev, "Program params failed: %d", ret);
1392
+
return ret;
1393
+
}
1394
+
1395
+
return do_bank_switch(stream);
1396
+
}
1397
+
1398
+
/**
1399
+
* sdw_disable_stream() - Disable SoundWire stream
1400
+
*
1401
+
* @stream: Soundwire stream
1402
+
*
1403
+
* Documentation/soundwire/stream.txt explains this API in detail
1404
+
*/
1405
+
int sdw_disable_stream(struct sdw_stream_runtime *stream)
1406
+
{
1407
+
int ret = 0;
1408
+
1409
+
if (!stream) {
1410
+
pr_err("SoundWire: Handle not found for stream");
1411
+
return -EINVAL;
1412
+
}
1413
+
1414
+
mutex_lock(&stream->m_rt->bus->bus_lock);
1415
+
1416
+
ret = _sdw_disable_stream(stream);
1417
+
if (ret < 0)
1418
+
pr_err("Disable for stream:%s failed: %d", stream->name, ret);
1419
+
1420
+
mutex_unlock(&stream->m_rt->bus->bus_lock);
1421
+
return ret;
1422
+
}
1423
+
EXPORT_SYMBOL(sdw_disable_stream);
1424
+
1425
+
static int _sdw_deprepare_stream(struct sdw_stream_runtime *stream)
1426
+
{
1427
+
struct sdw_master_runtime *m_rt = stream->m_rt;
1428
+
struct sdw_bus *bus = m_rt->bus;
1429
+
int ret = 0;
1430
+
1431
+
/* De-prepare port(s) */
1432
+
ret = sdw_prep_deprep_ports(m_rt, false);
1433
+
if (ret < 0) {
1434
+
dev_err(bus->dev, "De-prepare port(s) failed: %d", ret);
1435
+
return ret;
1436
+
}
1437
+
1438
+
stream->state = SDW_STREAM_DEPREPARED;
1439
+
1440
+
/* TODO: Update this during Device-Device support */
1441
+
bus->params.bandwidth -= m_rt->stream->params.rate *
1442
+
m_rt->ch_count * m_rt->stream->params.bps;
1443
+
1444
+
/* Program params */
1445
+
ret = sdw_program_params(bus);
1446
+
if (ret < 0) {
1447
+
dev_err(bus->dev, "Program params failed: %d", ret);
1448
+
return ret;
1449
+
}
1450
+
1451
+
return do_bank_switch(stream);
1452
+
}
1453
+
1454
+
/**
1455
+
* sdw_deprepare_stream() - Deprepare SoundWire stream
1456
+
*
1457
+
* @stream: Soundwire stream
1458
+
*
1459
+
* Documentation/soundwire/stream.txt explains this API in detail
1460
+
*/
1461
+
int sdw_deprepare_stream(struct sdw_stream_runtime *stream)
1462
+
{
1463
+
int ret = 0;
1464
+
1465
+
if (!stream) {
1466
+
pr_err("SoundWire: Handle not found for stream");
1467
+
return -EINVAL;
1468
+
}
1469
+
1470
+
mutex_lock(&stream->m_rt->bus->bus_lock);
1471
+
1472
+
ret = _sdw_deprepare_stream(stream);
1473
+
if (ret < 0)
1474
+
pr_err("De-prepare for stream:%d failed: %d", ret, ret);
1475
+
1476
+
mutex_unlock(&stream->m_rt->bus->bus_lock);
1477
+
return ret;
1478
+
}
1479
+
EXPORT_SYMBOL(sdw_deprepare_stream);
+331
-1
include/linux/soundwire/sdw.h
+331
-1
include/linux/soundwire/sdw.h
···
23
23
#define SDW_MASTER_DEV_NUM 14
24
24
25
25
#define SDW_NUM_DEV_ID_REGISTERS 6
26
+
/* frame shape defines */
26
27
28
+
/*
29
+
* Note: The maximum row define in SoundWire spec 1.1 is 23. In order to
30
+
* fill hole with 0, one more dummy entry is added
31
+
*/
32
+
#define SDW_FRAME_ROWS 24
33
+
#define SDW_FRAME_COLS 8
34
+
#define SDW_FRAME_ROW_COLS (SDW_FRAME_ROWS * SDW_FRAME_COLS)
35
+
36
+
#define SDW_FRAME_CTRL_BITS 48
27
37
#define SDW_MAX_DEVICES 11
38
+
39
+
#define SDW_VALID_PORT_RANGE(n) (n <= 14 && n >= 1)
40
+
41
+
#define SDW_DAI_ID_RANGE_START 100
42
+
#define SDW_DAI_ID_RANGE_END 200
28
43
29
44
/**
30
45
* enum sdw_slave_status - Slave status
···
74
59
SDW_CMD_FAIL = 2,
75
60
SDW_CMD_TIMEOUT = 3,
76
61
SDW_CMD_FAIL_OTHER = 4,
62
+
};
63
+
64
+
/**
65
+
* enum sdw_stream_type: data stream type
66
+
*
67
+
* @SDW_STREAM_PCM: PCM data stream
68
+
* @SDW_STREAM_PDM: PDM data stream
69
+
*
70
+
* spec doesn't define this, but is used in implementation
71
+
*/
72
+
enum sdw_stream_type {
73
+
SDW_STREAM_PCM = 0,
74
+
SDW_STREAM_PDM = 1,
75
+
};
76
+
77
+
/**
78
+
* enum sdw_data_direction: Data direction
79
+
*
80
+
* @SDW_DATA_DIR_RX: Data into Port
81
+
* @SDW_DATA_DIR_TX: Data out of Port
82
+
*/
83
+
enum sdw_data_direction {
84
+
SDW_DATA_DIR_RX = 0,
85
+
SDW_DATA_DIR_TX = 1,
77
86
};
78
87
79
88
/*
···
380
341
};
381
342
382
343
/**
383
-
* struct sdw_slave_ops - Slave driver callback ops
344
+
* sdw_reg_bank - SoundWire register banks
345
+
* @SDW_BANK0: Soundwire register bank 0
346
+
* @SDW_BANK1: Soundwire register bank 1
347
+
*/
348
+
enum sdw_reg_bank {
349
+
SDW_BANK0,
350
+
SDW_BANK1,
351
+
};
352
+
353
+
/**
354
+
* struct sdw_bus_conf: Bus configuration
355
+
*
356
+
* @clk_freq: Clock frequency, in Hz
357
+
* @num_rows: Number of rows in frame
358
+
* @num_cols: Number of columns in frame
359
+
* @bank: Next register bank
360
+
*/
361
+
struct sdw_bus_conf {
362
+
unsigned int clk_freq;
363
+
unsigned int num_rows;
364
+
unsigned int num_cols;
365
+
unsigned int bank;
366
+
};
367
+
368
+
/**
369
+
* struct sdw_prepare_ch: Prepare/De-prepare Data Port channel
370
+
*
371
+
* @num: Port number
372
+
* @ch_mask: Active channel mask
373
+
* @prepare: Prepare (true) /de-prepare (false) channel
374
+
* @bank: Register bank, which bank Slave/Master driver should program for
375
+
* implementation defined registers. This is always updated to next_bank
376
+
* value read from bus params.
377
+
*
378
+
*/
379
+
struct sdw_prepare_ch {
380
+
unsigned int num;
381
+
unsigned int ch_mask;
382
+
bool prepare;
383
+
unsigned int bank;
384
+
};
385
+
386
+
/**
387
+
* enum sdw_port_prep_ops: Prepare operations for Data Port
388
+
*
389
+
* @SDW_OPS_PORT_PRE_PREP: Pre prepare operation for the Port
390
+
* @SDW_OPS_PORT_PREP: Prepare operation for the Port
391
+
* @SDW_OPS_PORT_POST_PREP: Post prepare operation for the Port
392
+
*/
393
+
enum sdw_port_prep_ops {
394
+
SDW_OPS_PORT_PRE_PREP = 0,
395
+
SDW_OPS_PORT_PREP = 1,
396
+
SDW_OPS_PORT_POST_PREP = 2,
397
+
};
398
+
399
+
/**
400
+
* struct sdw_bus_params: Structure holding bus configuration
401
+
*
402
+
* @curr_bank: Current bank in use (BANK0/BANK1)
403
+
* @next_bank: Next bank to use (BANK0/BANK1). next_bank will always be
404
+
* set to !curr_bank
405
+
* @max_dr_freq: Maximum double rate clock frequency supported, in Hz
406
+
* @curr_dr_freq: Current double rate clock frequency, in Hz
407
+
* @bandwidth: Current bandwidth
408
+
* @col: Active columns
409
+
* @row: Active rows
410
+
*/
411
+
struct sdw_bus_params {
412
+
enum sdw_reg_bank curr_bank;
413
+
enum sdw_reg_bank next_bank;
414
+
unsigned int max_dr_freq;
415
+
unsigned int curr_dr_freq;
416
+
unsigned int bandwidth;
417
+
unsigned int col;
418
+
unsigned int row;
419
+
};
420
+
421
+
/**
422
+
* struct sdw_slave_ops: Slave driver callback ops
423
+
*
384
424
* @read_prop: Read Slave properties
385
425
* @interrupt_callback: Device interrupt notification (invoked in thread
386
426
* context)
387
427
* @update_status: Update Slave status
428
+
* @bus_config: Update the bus config for Slave
429
+
* @port_prep: Prepare the port with parameters
388
430
*/
389
431
struct sdw_slave_ops {
390
432
int (*read_prop)(struct sdw_slave *sdw);
···
473
353
struct sdw_slave_intr_status *status);
474
354
int (*update_status)(struct sdw_slave *slave,
475
355
enum sdw_slave_status status);
356
+
int (*bus_config)(struct sdw_slave *slave,
357
+
struct sdw_bus_params *params);
358
+
int (*port_prep)(struct sdw_slave *slave,
359
+
struct sdw_prepare_ch *prepare_ch,
360
+
enum sdw_port_prep_ops pre_ops);
476
361
};
477
362
478
363
/**
···
531
406
* SDW master structures and APIs
532
407
*/
533
408
409
+
/**
410
+
* struct sdw_port_params: Data Port parameters
411
+
*
412
+
* @num: Port number
413
+
* @bps: Word length of the Port
414
+
* @flow_mode: Port Data flow mode
415
+
* @data_mode: Test modes or normal mode
416
+
*
417
+
* This is used to program the Data Port based on Data Port stream
418
+
* parameters.
419
+
*/
420
+
struct sdw_port_params {
421
+
unsigned int num;
422
+
unsigned int bps;
423
+
unsigned int flow_mode;
424
+
unsigned int data_mode;
425
+
};
426
+
427
+
/**
428
+
* struct sdw_transport_params: Data Port Transport Parameters
429
+
*
430
+
* @blk_grp_ctrl_valid: Port implements block group control
431
+
* @num: Port number
432
+
* @blk_grp_ctrl: Block group control value
433
+
* @sample_interval: Sample interval
434
+
* @offset1: Blockoffset of the payload data
435
+
* @offset2: Blockoffset of the payload data
436
+
* @hstart: Horizontal start of the payload data
437
+
* @hstop: Horizontal stop of the payload data
438
+
* @blk_pkg_mode: Block per channel or block per port
439
+
* @lane_ctrl: Data lane Port uses for Data transfer. Currently only single
440
+
* data lane is supported in bus
441
+
*
442
+
* This is used to program the Data Port based on Data Port transport
443
+
* parameters. All these parameters are banked and can be modified
444
+
* during a bank switch without any artifacts in audio stream.
445
+
*/
446
+
struct sdw_transport_params {
447
+
bool blk_grp_ctrl_valid;
448
+
unsigned int port_num;
449
+
unsigned int blk_grp_ctrl;
450
+
unsigned int sample_interval;
451
+
unsigned int offset1;
452
+
unsigned int offset2;
453
+
unsigned int hstart;
454
+
unsigned int hstop;
455
+
unsigned int blk_pkg_mode;
456
+
unsigned int lane_ctrl;
457
+
};
458
+
459
+
/**
460
+
* struct sdw_enable_ch: Enable/disable Data Port channel
461
+
*
462
+
* @num: Port number
463
+
* @ch_mask: Active channel mask
464
+
* @enable: Enable (true) /disable (false) channel
465
+
*/
466
+
struct sdw_enable_ch {
467
+
unsigned int port_num;
468
+
unsigned int ch_mask;
469
+
bool enable;
470
+
};
471
+
472
+
/**
473
+
* struct sdw_master_port_ops: Callback functions from bus to Master
474
+
* driver to set Master Data ports.
475
+
*
476
+
* @dpn_set_port_params: Set the Port parameters for the Master Port.
477
+
* Mandatory callback
478
+
* @dpn_set_port_transport_params: Set transport parameters for the Master
479
+
* Port. Mandatory callback
480
+
* @dpn_port_prep: Port prepare operations for the Master Data Port.
481
+
* @dpn_port_enable_ch: Enable the channels of Master Port.
482
+
*/
483
+
struct sdw_master_port_ops {
484
+
int (*dpn_set_port_params)(struct sdw_bus *bus,
485
+
struct sdw_port_params *port_params,
486
+
unsigned int bank);
487
+
int (*dpn_set_port_transport_params)(struct sdw_bus *bus,
488
+
struct sdw_transport_params *transport_params,
489
+
enum sdw_reg_bank bank);
490
+
int (*dpn_port_prep)(struct sdw_bus *bus,
491
+
struct sdw_prepare_ch *prepare_ch);
492
+
int (*dpn_port_enable_ch)(struct sdw_bus *bus,
493
+
struct sdw_enable_ch *enable_ch, unsigned int bank);
494
+
};
495
+
534
496
struct sdw_msg;
535
497
536
498
/**
···
638
426
* @xfer_msg: Transfer message callback
639
427
* @xfer_msg_defer: Defer version of transfer message callback
640
428
* @reset_page_addr: Reset the SCP page address registers
429
+
* @set_bus_conf: Set the bus configuration
430
+
* @pre_bank_switch: Callback for pre bank switch
431
+
* @post_bank_switch: Callback for post bank switch
641
432
*/
642
433
struct sdw_master_ops {
643
434
int (*read_prop)(struct sdw_bus *bus);
···
652
437
struct sdw_defer *defer);
653
438
enum sdw_command_response (*reset_page_addr)
654
439
(struct sdw_bus *bus, unsigned int dev_num);
440
+
int (*set_bus_conf)(struct sdw_bus *bus,
441
+
struct sdw_bus_params *params);
442
+
int (*pre_bank_switch)(struct sdw_bus *bus);
443
+
int (*post_bank_switch)(struct sdw_bus *bus);
444
+
655
445
};
656
446
657
447
/**
···
669
449
* @bus_lock: bus lock
670
450
* @msg_lock: message lock
671
451
* @ops: Master callback ops
452
+
* @port_ops: Master port callback ops
453
+
* @params: Current bus parameters
672
454
* @prop: Master properties
455
+
* @m_rt_list: List of Master instance of all stream(s) running on Bus. This
456
+
* is used to compute and program bus bandwidth, clock, frame shape,
457
+
* transport and port parameters
673
458
* @defer_msg: Defer message
674
459
* @clk_stop_timeout: Clock stop timeout computed
460
+
* @bank_switch_timeout: Bank switch timeout computed
675
461
*/
676
462
struct sdw_bus {
677
463
struct device *dev;
···
687
461
struct mutex bus_lock;
688
462
struct mutex msg_lock;
689
463
const struct sdw_master_ops *ops;
464
+
const struct sdw_master_port_ops *port_ops;
465
+
struct sdw_bus_params params;
690
466
struct sdw_master_prop prop;
467
+
struct list_head m_rt_list;
691
468
struct sdw_defer defer_msg;
692
469
unsigned int clk_stop_timeout;
470
+
u32 bank_switch_timeout;
693
471
};
694
472
695
473
int sdw_add_bus_master(struct sdw_bus *bus);
696
474
void sdw_delete_bus_master(struct sdw_bus *bus);
475
+
476
+
/**
477
+
* sdw_port_config: Master or Slave Port configuration
478
+
*
479
+
* @num: Port number
480
+
* @ch_mask: channels mask for port
481
+
*/
482
+
struct sdw_port_config {
483
+
unsigned int num;
484
+
unsigned int ch_mask;
485
+
};
486
+
487
+
/**
488
+
* sdw_stream_config: Master or Slave stream configuration
489
+
*
490
+
* @frame_rate: Audio frame rate of the stream, in Hz
491
+
* @ch_count: Channel count of the stream
492
+
* @bps: Number of bits per audio sample
493
+
* @direction: Data direction
494
+
* @type: Stream type PCM or PDM
495
+
*/
496
+
struct sdw_stream_config {
497
+
unsigned int frame_rate;
498
+
unsigned int ch_count;
499
+
unsigned int bps;
500
+
enum sdw_data_direction direction;
501
+
enum sdw_stream_type type;
502
+
};
503
+
504
+
/**
505
+
* sdw_stream_state: Stream states
506
+
*
507
+
* @SDW_STREAM_ALLOCATED: New stream allocated.
508
+
* @SDW_STREAM_CONFIGURED: Stream configured
509
+
* @SDW_STREAM_PREPARED: Stream prepared
510
+
* @SDW_STREAM_ENABLED: Stream enabled
511
+
* @SDW_STREAM_DISABLED: Stream disabled
512
+
* @SDW_STREAM_DEPREPARED: Stream de-prepared
513
+
* @SDW_STREAM_RELEASED: Stream released
514
+
*/
515
+
enum sdw_stream_state {
516
+
SDW_STREAM_ALLOCATED = 0,
517
+
SDW_STREAM_CONFIGURED = 1,
518
+
SDW_STREAM_PREPARED = 2,
519
+
SDW_STREAM_ENABLED = 3,
520
+
SDW_STREAM_DISABLED = 4,
521
+
SDW_STREAM_DEPREPARED = 5,
522
+
SDW_STREAM_RELEASED = 6,
523
+
};
524
+
525
+
/**
526
+
* sdw_stream_params: Stream parameters
527
+
*
528
+
* @rate: Sampling frequency, in Hz
529
+
* @ch_count: Number of channels
530
+
* @bps: bits per channel sample
531
+
*/
532
+
struct sdw_stream_params {
533
+
unsigned int rate;
534
+
unsigned int ch_count;
535
+
unsigned int bps;
536
+
};
537
+
538
+
/**
539
+
* sdw_stream_runtime: Runtime stream parameters
540
+
*
541
+
* @name: SoundWire stream name
542
+
* @params: Stream parameters
543
+
* @state: Current state of the stream
544
+
* @type: Stream type PCM or PDM
545
+
* @m_rt: Master runtime
546
+
*/
547
+
struct sdw_stream_runtime {
548
+
char *name;
549
+
struct sdw_stream_params params;
550
+
enum sdw_stream_state state;
551
+
enum sdw_stream_type type;
552
+
struct sdw_master_runtime *m_rt;
553
+
};
554
+
555
+
struct sdw_stream_runtime *sdw_alloc_stream(char *stream_name);
556
+
void sdw_release_stream(struct sdw_stream_runtime *stream);
557
+
int sdw_stream_add_master(struct sdw_bus *bus,
558
+
struct sdw_stream_config *stream_config,
559
+
struct sdw_port_config *port_config,
560
+
unsigned int num_ports,
561
+
struct sdw_stream_runtime *stream);
562
+
int sdw_stream_add_slave(struct sdw_slave *slave,
563
+
struct sdw_stream_config *stream_config,
564
+
struct sdw_port_config *port_config,
565
+
unsigned int num_ports,
566
+
struct sdw_stream_runtime *stream);
567
+
int sdw_stream_remove_master(struct sdw_bus *bus,
568
+
struct sdw_stream_runtime *stream);
569
+
int sdw_stream_remove_slave(struct sdw_slave *slave,
570
+
struct sdw_stream_runtime *stream);
571
+
int sdw_prepare_stream(struct sdw_stream_runtime *stream);
572
+
int sdw_enable_stream(struct sdw_stream_runtime *stream);
573
+
int sdw_disable_stream(struct sdw_stream_runtime *stream);
574
+
int sdw_deprepare_stream(struct sdw_stream_runtime *stream);
697
575
698
576
/* messaging and data APIs */
699
577
+14
include/linux/soundwire/sdw_intel.h
+14
include/linux/soundwire/sdw_intel.h
···
5
5
#define __SDW_INTEL_H
6
6
7
7
/**
8
+
* struct sdw_intel_ops: Intel audio driver callback ops
9
+
*
10
+
* @config_stream: configure the stream with the hw_params
11
+
*/
12
+
struct sdw_intel_ops {
13
+
int (*config_stream)(void *arg, void *substream,
14
+
void *dai, void *hw_params, int stream_num);
15
+
};
16
+
17
+
/**
8
18
* struct sdw_intel_res - Soundwire Intel resource structure
9
19
* @mmio_base: mmio base of SoundWire registers
10
20
* @irq: interrupt number
11
21
* @handle: ACPI parent handle
12
22
* @parent: parent device
23
+
* @ops: callback ops
24
+
* @arg: callback arg
13
25
*/
14
26
struct sdw_intel_res {
15
27
void __iomem *mmio_base;
16
28
int irq;
17
29
acpi_handle handle;
18
30
struct device *parent;
31
+
const struct sdw_intel_ops *ops;
32
+
void *arg;
19
33
};
20
34
21
35
void *sdw_intel_init(acpi_handle *parent_handle, struct sdw_intel_res *res);
+23
include/sound/soc-dai.h
+23
include/sound/soc-dai.h
···
170
170
unsigned int rx_num, unsigned int *rx_slot);
171
171
int (*set_tristate)(struct snd_soc_dai *dai, int tristate);
172
172
173
+
int (*set_sdw_stream)(struct snd_soc_dai *dai,
174
+
void *stream, int direction);
173
175
/*
174
176
* DAI digital mute - optional.
175
177
* Called by soc-core to minimise any pops.
···
358
356
static inline void *snd_soc_dai_get_drvdata(struct snd_soc_dai *dai)
359
357
{
360
358
return dev_get_drvdata(dai->dev);
359
+
}
360
+
361
+
/**
362
+
* snd_soc_dai_set_sdw_stream() - Configures a DAI for SDW stream operation
363
+
* @dai: DAI
364
+
* @stream: STREAM
365
+
* @direction: Stream direction(Playback/Capture)
366
+
* SoundWire subsystem doesn't have a notion of direction and we reuse
367
+
* the ASoC stream direction to configure sink/source ports.
368
+
* Playback maps to source ports and Capture for sink ports.
369
+
*
370
+
* This should be invoked with NULL to clear the stream set previously.
371
+
* Returns 0 on success, a negative error code otherwise.
372
+
*/
373
+
static inline int snd_soc_dai_set_sdw_stream(struct snd_soc_dai *dai,
374
+
void *stream, int direction)
375
+
{
376
+
if (dai->driver->ops->set_sdw_stream)
377
+
return dai->driver->ops->set_sdw_stream(dai, stream, direction);
378
+
else
379
+
return -ENOTSUPP;
361
380
}
362
381
363
382
#endif