tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux
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Merge branch 'omap-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap-2.6

* 'omap-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap-2.6: (39 commits)
omap: delete unused bootloader tag variables
omap: Devkit8000: Remove unused pins
omap: Devkit8000: Change position of init calls
omap: Devkit8000: Remove unnecessary include file
omap: Devkit8000: Fix typo in pin name
omap: Devkit8000: Add missing package selection
omap: Devkit8000: Fix typo in supplies
n8x0_defconfig: remove CONFIG_NILFS2_FS override
omap: board-sdp-flash.c: Fix typos in debug output
omap4: Fix McBSP4 base address
omap: rx51_defconfig: Remove CONFIG_SYSFS_DEPRECATED*=y options
omap: rx51_defconfig: Remove duplicate phonet
omap: fix a gpmc nand problem
AM3517: initialize i2c subsystem after mux subsystem
omap: remove one of the define of INT_34XX_BENCH_MPU_EMUL
omap: fix the compile error if CONFIG_MTD_NAND_OMAP2 is notenabled
OMAP4: Clocks: Change SPI Instance Names
omap: Devkit8000: Fix wrong usb port on Devkit8000
OMAP4: Fix for CONTROL register Base
OMAP4-HSMMC: FIX for MMC5 Controller IRQ Base
...

Linus Torvalds 17282b98 58927533

+113 -124
unified split
-1
arch/arm/configs/n8x0_defconfig
··· 1058 1058 # CONFIG_ROMFS_FS is not set 1059 1059 # CONFIG_SYSV_FS is not set 1060 1060 # CONFIG_UFS_FS is not set 1061 - # CONFIG_NILFS2_FS is not set 1062 1061 CONFIG_NETWORK_FILESYSTEMS=y 1063 1062 # CONFIG_NFS_FS is not set 1064 1063 # CONFIG_NFSD is not set
+1 -1
arch/arm/configs/omap_zoom2_defconfig
··· 661 661 CONFIG_SERIAL_8250=y 662 662 CONFIG_SERIAL_8250_CONSOLE=y 663 663 CONFIG_SERIAL_8250_NR_UARTS=32 664 - CONFIG_SERIAL_8250_RUNTIME_UARTS=4 664 + CONFIG_SERIAL_8250_RUNTIME_UARTS=1 665 665 CONFIG_SERIAL_8250_EXTENDED=y 666 666 CONFIG_SERIAL_8250_MANY_PORTS=y 667 667 CONFIG_SERIAL_8250_SHARE_IRQ=y
+1 -1
arch/arm/configs/omap_zoom3_defconfig
··· 680 680 CONFIG_SERIAL_8250=y 681 681 CONFIG_SERIAL_8250_CONSOLE=y 682 682 CONFIG_SERIAL_8250_NR_UARTS=32 683 - CONFIG_SERIAL_8250_RUNTIME_UARTS=4 683 + CONFIG_SERIAL_8250_RUNTIME_UARTS=1 684 684 CONFIG_SERIAL_8250_EXTENDED=y 685 685 CONFIG_SERIAL_8250_MANY_PORTS=y 686 686 CONFIG_SERIAL_8250_SHARE_IRQ=y
-3
arch/arm/configs/rx51_defconfig
··· 59 59 CONFIG_USER_SCHED=y 60 60 # CONFIG_CGROUP_SCHED is not set 61 61 # CONFIG_CGROUPS is not set 62 - CONFIG_SYSFS_DEPRECATED=y 63 - CONFIG_SYSFS_DEPRECATED_V2=y 64 62 # CONFIG_RELAY is not set 65 63 # CONFIG_NAMESPACES is not set 66 64 CONFIG_BLK_DEV_INITRD=y ··· 478 480 # CONFIG_BT_HCIBFUSB is not set 479 481 # CONFIG_BT_HCIVHCI is not set 480 482 # CONFIG_AF_RXRPC is not set 481 - # CONFIG_PHONET is not set 482 483 CONFIG_WIRELESS=y 483 484 CONFIG_CFG80211=y 484 485 # CONFIG_CFG80211_REG_DEBUG is not set
-15
arch/arm/mach-omap1/timer32k.c
··· 68 68 * --------------------------------------------------------------------------- 69 69 */ 70 70 71 - #if defined(CONFIG_ARCH_OMAP16XX) 72 - #define TIMER_32K_SYNCHRONIZED 0xfffbc410 73 - #else 74 - #error OMAP 32KHz timer does not currently work on 15XX! 75 - #endif 76 - 77 71 /* 16xx specific defines */ 78 72 #define OMAP1_32K_TIMER_BASE 0xfffb9000 79 73 #define OMAP1_32K_TIMER_CR 0x08 ··· 143 149 .set_next_event = omap_32k_timer_set_next_event, 144 150 .set_mode = omap_32k_timer_set_mode, 145 151 }; 146 - 147 - /* 148 - * The 32KHz synchronized timer is an additional timer on 16xx. 149 - * It is always running. 150 - */ 151 - static inline unsigned long omap_32k_sync_timer_read(void) 152 - { 153 - return omap_readl(TIMER_32K_SYNCHRONIZED); 154 - } 155 152 156 153 static irqreturn_t omap_32k_timer_interrupt(int irq, void *dev_id) 157 154 {
+4 -2
arch/arm/mach-omap2/Kconfig
··· 59 59 select OMAP_PACKAGE_CBB 60 60 61 61 config MACH_DEVKIT8000 62 - bool "DEVKIT8000 board" 63 - depends on ARCH_OMAP3 62 + bool "DEVKIT8000 board" 63 + depends on ARCH_OMAP3 64 + select OMAP_PACKAGE_CUS 65 + select OMAP_MUX 64 66 65 67 config MACH_OMAP_LDP 66 68 bool "OMAP3 LDP board"
+1
arch/arm/mach-omap2/board-3630sdp.c
··· 96 96 static void __init omap_sdp_init(void) 97 97 { 98 98 omap3_mux_init(board_mux, OMAP_PACKAGE_CBP); 99 + omap_serial_init(); 99 100 zoom_peripherals_init(); 100 101 board_smc91x_init(); 101 102 enable_board_wakeup_source();
+2 -2
arch/arm/mach-omap2/board-am3517evm.c
··· 294 294 295 295 static void __init am3517_evm_init(void) 296 296 { 297 - am3517_evm_i2c_init(); 298 - 299 297 omap3_mux_init(board_mux, OMAP_PACKAGE_CBB); 298 + 299 + am3517_evm_i2c_init(); 300 300 platform_add_devices(am3517_evm_devices, 301 301 ARRAY_SIZE(am3517_evm_devices)); 302 302
+9 -30
arch/arm/mach-omap2/board-devkit8000.c
··· 50 50 #include <linux/input/matrix_keypad.h> 51 51 #include <linux/spi/spi.h> 52 52 #include <linux/spi/ads7846.h> 53 - #include <linux/usb/otg.h> 54 53 #include <linux/dm9000.h> 55 54 #include <linux/interrupt.h> 56 55 ··· 268 269 devkit8000_vmmc1_supply.dev = mmc[0].dev; 269 270 devkit8000_vsim_supply.dev = mmc[0].dev; 270 271 271 - /* REVISIT: need ehci-omap hooks for external VBUS 272 - * power switch and overcurrent detect 273 - */ 274 - 275 - gpio_request(gpio + 1, "EHCI_nOC"); 276 - gpio_direction_input(gpio + 1); 277 - 278 - /* TWL4030_GPIO_MAX + 0 == ledA, EHCI nEN_USB_PWR (out, active low) */ 279 - gpio_request(gpio + TWL4030_GPIO_MAX, "nEN_USB_PWR"); 280 - gpio_direction_output(gpio + TWL4030_GPIO_MAX, 1); 281 - 282 - /* TWL4030_GPIO_MAX + 1 == ledB, PMU_STAT (out, active low LED) */ 283 - gpio_leds[2].gpio = gpio + TWL4030_GPIO_MAX + 1; 284 - 285 272 return 0; 286 273 } 287 274 ··· 288 303 .dev = &devkit8000_lcd_device.dev, 289 304 }, 290 305 { 291 - .supply = "vdss_dsi", 306 + .supply = "vdds_dsi", 292 307 .dev = &devkit8000_dss_device.dev, 293 308 } 294 309 }; ··· 624 639 static const struct ehci_hcd_omap_platform_data ehci_pdata __initconst = { 625 640 626 641 .port_mode[0] = EHCI_HCD_OMAP_MODE_PHY, 627 - .port_mode[1] = EHCI_HCD_OMAP_MODE_PHY, 642 + .port_mode[1] = EHCI_HCD_OMAP_MODE_UNKNOWN, 628 643 .port_mode[2] = EHCI_HCD_OMAP_MODE_UNKNOWN, 629 644 630 645 .phy_reset = true, 631 646 .reset_gpio_port[0] = -EINVAL, 632 - .reset_gpio_port[1] = 147, 647 + .reset_gpio_port[1] = -EINVAL, 633 648 .reset_gpio_port[2] = -EINVAL 634 649 }; 635 650 636 651 static void __init devkit8000_init(void) 637 652 { 653 + omap_serial_init(); 654 + 655 + omap_dm9000_init(); 656 + 638 657 devkit8000_i2c_init(); 639 658 platform_add_devices(devkit8000_devices, 640 659 ARRAY_SIZE(devkit8000_devices)); ··· 648 659 spi_register_board_info(devkit8000_spi_board_info, 649 660 ARRAY_SIZE(devkit8000_spi_board_info)); 650 661 651 - omap_serial_init(); 652 - 653 - omap_dm9000_init(); 654 - 655 662 devkit8000_ads7846_init(); 656 - 657 - omap_mux_init_gpio(170, OMAP_PIN_INPUT); 658 - 659 - gpio_request(170, "DVI_nPD"); 660 - /* REVISIT leave DVI powered down until it's needed ... */ 661 - gpio_direction_output(170, true); 662 663 663 664 usb_musb_init(&musb_board_data); 664 665 usb_ehci_init(&ehci_pdata); 665 666 devkit8000_flash_init(); 666 667 667 668 /* Ensure SDRC pins are mux'd for self-refresh */ 668 - omap_mux_init_signal("sdr_cke0", OMAP_PIN_OUTPUT); 669 - omap_mux_init_signal("sdr_cke1", OMAP_PIN_OUTPUT); 669 + omap_mux_init_signal("sdrc_cke0", OMAP_PIN_OUTPUT); 670 + omap_mux_init_signal("sdrc_cke1", OMAP_PIN_OUTPUT); 670 671 } 671 672 672 673 static void __init devkit8000_map_io(void)
+4 -4
arch/arm/mach-omap2/board-igep0020.c
··· 458 458 }; 459 459 460 460 static const struct ehci_hcd_omap_platform_data ehci_pdata __initconst = { 461 - .port_mode[0] = EHCI_HCD_OMAP_MODE_UNKNOWN, 462 - .port_mode[1] = EHCI_HCD_OMAP_MODE_PHY, 461 + .port_mode[0] = EHCI_HCD_OMAP_MODE_PHY, 462 + .port_mode[1] = EHCI_HCD_OMAP_MODE_UNKNOWN, 463 463 .port_mode[2] = EHCI_HCD_OMAP_MODE_UNKNOWN, 464 464 465 465 .phy_reset = true, 466 - .reset_gpio_port[0] = -EINVAL, 467 - .reset_gpio_port[1] = IGEP2_GPIO_USBH_NRESET, 466 + .reset_gpio_port[0] = IGEP2_GPIO_USBH_NRESET, 467 + .reset_gpio_port[1] = -EINVAL, 468 468 .reset_gpio_port[2] = -EINVAL, 469 469 }; 470 470
+9 -9
arch/arm/mach-omap2/board-n8x0.c
··· 216 216 */ 217 217 #define N8X0_SLOT_SWITCH_GPIO 96 218 218 #define N810_EMMC_VSD_GPIO 23 219 - #define NN810_EMMC_VIO_GPIO 9 219 + #define N810_EMMC_VIO_GPIO 9 220 220 221 221 static int n8x0_mmc_switch_slot(struct device *dev, int slot) 222 222 { ··· 304 304 if (power_on) { 305 305 gpio_set_value(N810_EMMC_VSD_GPIO, 1); 306 306 msleep(1); 307 - gpio_set_value(NN810_EMMC_VIO_GPIO, 1); 307 + gpio_set_value(N810_EMMC_VIO_GPIO, 1); 308 308 msleep(1); 309 309 } else { 310 - gpio_set_value(NN810_EMMC_VIO_GPIO, 0); 310 + gpio_set_value(N810_EMMC_VIO_GPIO, 0); 311 311 msleep(50); 312 312 gpio_set_value(N810_EMMC_VSD_GPIO, 0); 313 313 msleep(50); ··· 468 468 469 469 if (machine_is_nokia_n810()) { 470 470 gpio_free(N810_EMMC_VSD_GPIO); 471 - gpio_free(NN810_EMMC_VIO_GPIO); 471 + gpio_free(N810_EMMC_VIO_GPIO); 472 472 } 473 473 } 474 474 ··· 529 529 530 530 err = gpio_request(N8X0_SLOT_SWITCH_GPIO, "MMC slot switch"); 531 531 if (err) 532 - return err; 532 + return; 533 533 534 534 gpio_direction_output(N8X0_SLOT_SWITCH_GPIO, 0); 535 535 ··· 537 537 err = gpio_request(N810_EMMC_VSD_GPIO, "MMC slot 2 Vddf"); 538 538 if (err) { 539 539 gpio_free(N8X0_SLOT_SWITCH_GPIO); 540 - return err; 540 + return; 541 541 } 542 542 gpio_direction_output(N810_EMMC_VSD_GPIO, 0); 543 543 544 - err = gpio_request(NN810_EMMC_VIO_GPIO, "MMC slot 2 Vdd"); 544 + err = gpio_request(N810_EMMC_VIO_GPIO, "MMC slot 2 Vdd"); 545 545 if (err) { 546 546 gpio_free(N8X0_SLOT_SWITCH_GPIO); 547 547 gpio_free(N810_EMMC_VSD_GPIO); 548 - return err; 548 + return; 549 549 } 550 - gpio_direction_output(NN810_EMMC_VIO_GPIO, 0); 550 + gpio_direction_output(N810_EMMC_VIO_GPIO, 0); 551 551 } 552 552 553 553 mmc_data[0] = &mmc1_data;
+4 -4
arch/arm/mach-omap2/board-sdp-flash.c
··· 253 253 } 254 254 255 255 if (norcs > GPMC_CS_NUM) 256 - printk(KERN_INFO "OneNAND: Unable to find configuration " 257 - " in GPMC\n "); 256 + printk(KERN_INFO "NOR: Unable to find configuration " 257 + "in GPMC\n"); 258 258 else 259 259 board_nor_init(sdp_partition_info[0], norcs); 260 260 261 261 if (onenandcs > GPMC_CS_NUM) 262 262 printk(KERN_INFO "OneNAND: Unable to find configuration " 263 - " in GPMC\n "); 263 + "in GPMC\n"); 264 264 else 265 265 board_onenand_init(sdp_partition_info[1], onenandcs); 266 266 267 267 if (nandcs > GPMC_CS_NUM) 268 268 printk(KERN_INFO "NAND: Unable to find configuration " 269 - " in GPMC\n "); 269 + "in GPMC\n"); 270 270 else 271 271 board_nand_init(sdp_partition_info[2], nandcs); 272 272 }
+1 -1
arch/arm/mach-omap2/board-zoom-debugboard.c
··· 96 96 97 97 static struct platform_device zoom_debugboard_serial_device = { 98 98 .name = "serial8250", 99 - .id = 3, 99 + .id = PLAT8250_DEV_PLATFORM, 100 100 .dev = { 101 101 .platform_data = serial_platform_data, 102 102 },
-1
arch/arm/mach-omap2/board-zoom-peripherals.c
··· 280 280 void __init zoom_peripherals_init(void) 281 281 { 282 282 omap_i2c_init(); 283 - omap_serial_init(); 284 283 usb_musb_init(&musb_board_data); 285 284 enable_board_wakeup_source(); 286 285 }
+1 -1
arch/arm/mach-omap2/clock3xxx_data.c
··· 895 895 .ops = &clkops_omap2_dflt_wait, 896 896 .parent = &dpll4_m4_ck, 897 897 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), 898 - .enable_bit = OMAP3430_PWRDN_CAM_SHIFT, 898 + .enable_bit = OMAP3430_PWRDN_DSS1_SHIFT, 899 899 .flags = INVERT_ENABLE, 900 900 .clkdm_name = "dpll4_clkdm", 901 901 .recalc = &omap3_clkoutx2_recalc,
+4 -4
arch/arm/mach-omap2/clock44xx_data.c
··· 2671 2671 CLK("omap-mcbsp.2", "ick", &dummy_ck, CK_443X), 2672 2672 CLK("omap-mcbsp.3", "ick", &dummy_ck, CK_443X), 2673 2673 CLK("omap-mcbsp.4", "ick", &dummy_ck, CK_443X), 2674 - CLK("omap-mcspi.1", "ick", &dummy_ck, CK_443X), 2675 - CLK("omap-mcspi.2", "ick", &dummy_ck, CK_443X), 2676 - CLK("omap-mcspi.3", "ick", &dummy_ck, CK_443X), 2677 - CLK("omap-mcspi.4", "ick", &dummy_ck, CK_443X), 2674 + CLK("omap2_mcspi.1", "ick", &dummy_ck, CK_443X), 2675 + CLK("omap2_mcspi.2", "ick", &dummy_ck, CK_443X), 2676 + CLK("omap2_mcspi.3", "ick", &dummy_ck, CK_443X), 2677 + CLK("omap2_mcspi.4", "ick", &dummy_ck, CK_443X), 2678 2678 CLK(NULL, "uart1_ick", &dummy_ck, CK_443X), 2679 2679 CLK(NULL, "uart2_ick", &dummy_ck, CK_443X), 2680 2680 CLK(NULL, "uart3_ick", &dummy_ck, CK_443X),
+3 -3
arch/arm/mach-omap2/clockdomain.c
··· 240 240 bits = OMAP24XX_CLKSTCTRL_ENABLE_AUTO; 241 241 else 242 242 bits = OMAP24XX_CLKSTCTRL_DISABLE_AUTO; 243 - } else if (cpu_is_omap34xx() | cpu_is_omap44xx()) { 243 + } else if (cpu_is_omap34xx() || cpu_is_omap44xx()) { 244 244 if (enable) 245 245 bits = OMAP34XX_CLKSTCTRL_ENABLE_AUTO; 246 246 else ··· 812 812 cm_set_mod_reg_bits(OMAP24XX_FORCESTATE, 813 813 clkdm->pwrdm.ptr->prcm_offs, OMAP2_PM_PWSTCTRL); 814 814 815 - } else if (cpu_is_omap34xx() | cpu_is_omap44xx()) { 815 + } else if (cpu_is_omap34xx() || cpu_is_omap44xx()) { 816 816 817 817 u32 bits = (OMAP34XX_CLKSTCTRL_FORCE_SLEEP << 818 818 __ffs(clkdm->clktrctrl_mask)); ··· 856 856 cm_clear_mod_reg_bits(OMAP24XX_FORCESTATE, 857 857 clkdm->pwrdm.ptr->prcm_offs, OMAP2_PM_PWSTCTRL); 858 858 859 - } else if (cpu_is_omap34xx() | cpu_is_omap44xx()) { 859 + } else if (cpu_is_omap34xx() || cpu_is_omap44xx()) { 860 860 861 861 u32 bits = (OMAP34XX_CLKSTCTRL_FORCE_WAKEUP << 862 862 __ffs(clkdm->clktrctrl_mask));
+1 -1
arch/arm/mach-omap2/devices.c
··· 726 726 if (!cpu_is_omap44xx()) 727 727 return; 728 728 base = OMAP4_MMC5_BASE + OMAP4_MMC_REG_OFFSET; 729 - irq = OMAP44XX_IRQ_MMC4; 729 + irq = OMAP44XX_IRQ_MMC5; 730 730 break; 731 731 default: 732 732 continue;
+3
arch/arm/mach-omap2/gpmc-nand.c
··· 39 39 struct gpmc_timings t; 40 40 int err; 41 41 42 + if (!gpmc_nand_data->gpmc_t) 43 + return 0; 44 + 42 45 memset(&t, 0, sizeof(t)); 43 46 t.sync_clk = gpmc_round_ns_to_ticks(gpmc_nand_data->gpmc_t->sync_clk); 44 47 t.cs_on = gpmc_round_ns_to_ticks(gpmc_nand_data->gpmc_t->cs_on);
+1 -1
arch/arm/mach-omap2/include/mach/entry-macro.S
··· 52 52 53 53 mrc p15, 0, \tmp, c0, c0, 0 @ get processor revision 54 54 and \tmp, \tmp, #0x000f0000 @ only check architecture 55 - cmp \tmp, #0x00060000 @ is v6? 55 + cmp \tmp, #0x00070000 @ is v6? 56 56 beq 2400f @ found v6 so it's omap24xx 57 57 mrc p15, 0, \tmp, c0, c0, 0 @ get processor revision 58 58 and \tmp, \tmp, #0x000000f0 @ check cortex 8 or 9
+3 -3
arch/arm/mach-omap2/omap-headsmp.S
··· 33 33 ENTRY(omap_secondary_startup) 34 34 hold: ldr r12,=0x103 35 35 dsb 36 - smc @ read from AuxCoreBoot0 36 + smc #0 @ read from AuxCoreBoot0 37 37 mov r0, r0, lsr #9 38 38 mrc p15, 0, r4, c0, c0, 5 39 39 and r4, r4, #0x0f ··· 52 52 stmfd sp!, {r1-r12, lr} 53 53 ldr r12, =0x104 54 54 dsb 55 - smc 55 + smc #0 56 56 ldmfd sp!, {r1-r12, pc} 57 57 END(omap_modify_auxcoreboot0) 58 58 ··· 60 60 stmfd sp!, {r2-r12, lr} 61 61 ldr r12, =0x105 62 62 dsb 63 - smc 63 + smc #0 64 64 ldmfd sp!, {r2-r12, pc} 65 65 END(omap_auxcoreboot_addr)
+1 -1
arch/arm/mach-omap2/omap44xx-smc.S
··· 27 27 mov r12, r0 28 28 mov r0, r1 29 29 dsb 30 - smc 30 + smc #0 31 31 ldmfd sp!, {r2-r12, pc} 32 32 END(omap_smc1)
+3
arch/arm/mach-omap2/omap_hwmod.c
··· 1511 1511 c = oh->slaves[oh->_mpu_port_index]->_clk; 1512 1512 } 1513 1513 1514 + if (!c->clkdm) 1515 + return NULL; 1516 + 1514 1517 return c->clkdm->pwrdm.ptr; 1515 1518 1516 1519 }
+1 -1
arch/arm/mach-omap2/powerdomain.c
··· 222 222 { 223 223 struct powerdomain **p = NULL; 224 224 225 - if (cpu_is_omap24xx() | cpu_is_omap34xx()) { 225 + if (cpu_is_omap24xx() || cpu_is_omap34xx()) { 226 226 pwrstctrl_reg_offs = OMAP2_PM_PWSTCTRL; 227 227 pwrstst_reg_offs = OMAP2_PM_PWSTST; 228 228 } else if (cpu_is_omap44xx()) {
+2 -2
arch/arm/mach-omap2/prcm.c
··· 123 123 u32 omap_prcm_get_reset_sources(void) 124 124 { 125 125 /* XXX This presumably needs modification for 34XX */ 126 - if (cpu_is_omap24xx() | cpu_is_omap34xx()) 126 + if (cpu_is_omap24xx() || cpu_is_omap34xx()) 127 127 return prm_read_mod_reg(WKUP_MOD, OMAP2_RM_RSTST) & 0x7f; 128 128 if (cpu_is_omap44xx()) 129 129 return prm_read_mod_reg(WKUP_MOD, OMAP4_RM_RSTST) & 0x7f; ··· 157 157 else 158 158 WARN_ON(1); 159 159 160 - if (cpu_is_omap24xx() | cpu_is_omap34xx()) 160 + if (cpu_is_omap24xx() || cpu_is_omap34xx()) 161 161 prm_set_mod_reg_bits(OMAP_RST_DPLL3, prcm_offs, 162 162 OMAP2_RM_RSTCTRL); 163 163 if (cpu_is_omap44xx())
+18 -17
arch/arm/mach-omap2/serial.c
··· 115 115 } 116 116 }; 117 117 118 - #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4) 119 118 static struct plat_serial8250_port serial_platform_data3[] = { 120 119 { 121 120 .irq = 70, ··· 127 128 } 128 129 }; 129 130 130 - static inline void omap2_set_globals_uart4(struct omap_globals *omap2_globals) 131 - { 132 - serial_platform_data3[0].mapbase = omap2_globals->uart4_phys; 133 - } 134 - #else 135 - static inline void omap2_set_globals_uart4(struct omap_globals *omap2_globals) 136 - { 137 - } 138 - #endif 139 - 140 131 void __init omap2_set_globals_uart(struct omap_globals *omap2_globals) 141 132 { 142 133 serial_platform_data0[0].mapbase = omap2_globals->uart1_phys; 143 134 serial_platform_data1[0].mapbase = omap2_globals->uart2_phys; 144 135 serial_platform_data2[0].mapbase = omap2_globals->uart3_phys; 145 - if (cpu_is_omap3630() || cpu_is_omap44xx()) 146 - omap2_set_globals_uart4(omap2_globals); 136 + serial_platform_data3[0].mapbase = omap2_globals->uart4_phys; 147 137 } 148 138 149 139 static inline unsigned int __serial_read_reg(struct uart_port *up, ··· 538 550 unsigned int value; 539 551 540 552 if (sscanf(buf, "%u", &value) != 1) { 541 - printk(KERN_ERR "sleep_timeout_store: Invalid value\n"); 553 + dev_err(dev, "sleep_timeout_store: Invalid value\n"); 542 554 return -EINVAL; 543 555 } 544 556 ··· 652 664 struct device *dev = &pdev->dev; 653 665 struct plat_serial8250_port *p = dev->platform_data; 654 666 667 + /* Don't map zero-based physical address */ 668 + if (p->mapbase == 0) { 669 + dev_warn(dev, "no physical address for uart#%d," 670 + " so skipping early_init...\n", i); 671 + continue; 672 + } 655 673 /* 656 674 * Module 4KB + L4 interconnect 4KB 657 675 * Static mapping, never released 658 676 */ 659 677 p->membase = ioremap(p->mapbase, SZ_8K); 660 678 if (!p->membase) { 661 - printk(KERN_ERR "ioremap failed for uart%i\n", i + 1); 679 + dev_err(dev, "ioremap failed for uart%i\n", i + 1); 662 680 continue; 663 681 } 664 682 665 683 sprintf(name, "uart%d_ick", i + 1); 666 684 uart->ick = clk_get(NULL, name); 667 685 if (IS_ERR(uart->ick)) { 668 - printk(KERN_ERR "Could not get uart%d_ick\n", i + 1); 686 + dev_err(dev, "Could not get uart%d_ick\n", i + 1); 669 687 uart->ick = NULL; 670 688 } 671 689 672 690 sprintf(name, "uart%d_fck", i+1); 673 691 uart->fck = clk_get(NULL, name); 674 692 if (IS_ERR(uart->fck)) { 675 - printk(KERN_ERR "Could not get uart%d_fck\n", i + 1); 693 + dev_err(dev, "Could not get uart%d_fck\n", i + 1); 676 694 uart->fck = NULL; 677 695 } 678 696 ··· 720 726 uart = &omap_uart[port]; 721 727 pdev = &uart->pdev; 722 728 dev = &pdev->dev; 729 + 730 + /* Don't proceed if there's no clocks available */ 731 + if (unlikely(!uart->ick || !uart->fck)) { 732 + WARN(1, "%s: can't init uart%d, no clocks available\n", 733 + kobject_name(&dev->kobj), port); 734 + return; 735 + } 723 736 724 737 omap_uart_enable_clocks(uart); 725 738
+14 -8
arch/arm/plat-omap/common.c
··· 44 44 45 45 #define NO_LENGTH_CHECK 0xffffffff 46 46 47 - unsigned char omap_bootloader_tag[512]; 48 - int omap_bootloader_tag_len; 49 - 50 47 struct omap_board_config_kernel *omap_board_config; 51 48 int omap_board_config_size; 52 49 ··· 97 100 98 101 #include <linux/clocksource.h> 99 102 103 + /* 104 + * offset_32k holds the init time counter value. It is then subtracted 105 + * from every counter read to achieve a counter that counts time from the 106 + * kernel boot (needed for sched_clock()). 107 + */ 108 + static u32 offset_32k __read_mostly; 109 + 100 110 #ifdef CONFIG_ARCH_OMAP16XX 101 111 static cycle_t omap16xx_32k_read(struct clocksource *cs) 102 112 { 103 - return omap_readl(OMAP16XX_TIMER_32K_SYNCHRONIZED); 113 + return omap_readl(OMAP16XX_TIMER_32K_SYNCHRONIZED) - offset_32k; 104 114 } 105 115 #else 106 116 #define omap16xx_32k_read NULL ··· 116 112 #ifdef CONFIG_ARCH_OMAP2420 117 113 static cycle_t omap2420_32k_read(struct clocksource *cs) 118 114 { 119 - return omap_readl(OMAP2420_32KSYNCT_BASE + 0x10); 115 + return omap_readl(OMAP2420_32KSYNCT_BASE + 0x10) - offset_32k; 120 116 } 121 117 #else 122 118 #define omap2420_32k_read NULL ··· 125 121 #ifdef CONFIG_ARCH_OMAP2430 126 122 static cycle_t omap2430_32k_read(struct clocksource *cs) 127 123 { 128 - return omap_readl(OMAP2430_32KSYNCT_BASE + 0x10); 124 + return omap_readl(OMAP2430_32KSYNCT_BASE + 0x10) - offset_32k; 129 125 } 130 126 #else 131 127 #define omap2430_32k_read NULL ··· 134 130 #ifdef CONFIG_ARCH_OMAP3 135 131 static cycle_t omap34xx_32k_read(struct clocksource *cs) 136 132 { 137 - return omap_readl(OMAP3430_32KSYNCT_BASE + 0x10); 133 + return omap_readl(OMAP3430_32KSYNCT_BASE + 0x10) - offset_32k; 138 134 } 139 135 #else 140 136 #define omap34xx_32k_read NULL ··· 143 139 #ifdef CONFIG_ARCH_OMAP4 144 140 static cycle_t omap44xx_32k_read(struct clocksource *cs) 145 141 { 146 - return omap_readl(OMAP4430_32KSYNCT_BASE + 0x10); 142 + return omap_readl(OMAP4430_32KSYNCT_BASE + 0x10) - offset_32k; 147 143 } 148 144 #else 149 145 #define omap44xx_32k_read NULL ··· 230 226 231 227 clocksource_32k.mult = clocksource_hz2mult(32768, 232 228 clocksource_32k.shift); 229 + 230 + offset_32k = clocksource_32k.read(&clocksource_32k); 233 231 234 232 if (clocksource_register(&clocksource_32k)) 235 233 printk(err, clocksource_32k.name);
+9
arch/arm/plat-omap/dma.c
··· 937 937 { 938 938 u32 l; 939 939 940 + /* 941 + * The CPC/CDAC register needs to be initialized to zero 942 + * before starting dma transfer. 943 + */ 944 + if (cpu_is_omap15xx()) 945 + dma_write(0, CPC(lch)); 946 + else 947 + dma_write(0, CDAC(lch)); 948 + 940 949 if (!omap_dma_in_1510_mode() && dma_chan[lch].next_lch != -1) { 941 950 int next_lch, cur_lch; 942 951 char dma_chan_link_map[OMAP_DMA4_LOGICAL_DMA_CH_COUNT];
+3 -3
arch/arm/plat-omap/gpio.c
··· 798 798 case METHOD_MPUIO: 799 799 reg += OMAP_MPUIO_GPIO_INT_EDGE; 800 800 l = __raw_readl(reg); 801 - if (trigger & IRQ_TYPE_EDGE_BOTH) 801 + if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) 802 802 bank->toggle_mask |= 1 << gpio; 803 803 if (trigger & IRQ_TYPE_EDGE_RISING) 804 804 l |= 1 << gpio; ··· 812 812 case METHOD_GPIO_1510: 813 813 reg += OMAP1510_GPIO_INT_CONTROL; 814 814 l = __raw_readl(reg); 815 - if (trigger & IRQ_TYPE_EDGE_BOTH) 815 + if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) 816 816 bank->toggle_mask |= 1 << gpio; 817 817 if (trigger & IRQ_TYPE_EDGE_RISING) 818 818 l |= 1 << gpio; ··· 846 846 case METHOD_GPIO_7XX: 847 847 reg += OMAP7XX_GPIO_INT_CONTROL; 848 848 l = __raw_readl(reg); 849 - if (trigger & IRQ_TYPE_EDGE_BOTH) 849 + if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) 850 850 bank->toggle_mask |= 1 << gpio; 851 851 if (trigger & IRQ_TYPE_EDGE_RISING) 852 852 l |= 1 << gpio;
-2
arch/arm/plat-omap/include/plat/irqs.h
··· 345 345 #define INT_34XX_MMC3_IRQ 94 346 346 #define INT_34XX_GPT12_IRQ 95 347 347 348 - #define INT_34XX_BENCH_MPU_EMUL 3 349 - 350 348 #define INT_35XX_HECC0_IRQ 24 351 349 #define INT_35XX_HECC1_IRQ 28 352 350 #define INT_35XX_EMAC_C0_RXTHRESH_IRQ 67
+1 -1
arch/arm/plat-omap/include/plat/mcbsp.h
··· 59 59 #define OMAP44XX_MCBSP1_BASE 0x49022000 60 60 #define OMAP44XX_MCBSP2_BASE 0x49024000 61 61 #define OMAP44XX_MCBSP3_BASE 0x49026000 62 - #define OMAP44XX_MCBSP4_BASE 0x48074000 62 + #define OMAP44XX_MCBSP4_BASE 0x48096000 63 63 64 64 #if defined(CONFIG_ARCH_OMAP15XX) || defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850) 65 65
+7
arch/arm/plat-omap/include/plat/nand.h
··· 29 29 /* size (4 KiB) for IO mapping */ 30 30 #define NAND_IO_SIZE SZ_4K 31 31 32 + #if defined(CONFIG_MTD_NAND_OMAP2) || defined(CONFIG_MTD_NAND_OMAP2_MODULE) 32 33 extern int gpmc_nand_init(struct omap_nand_platform_data *d); 34 + #else 35 + static inline int gpmc_nand_init(struct omap_nand_platform_data *d) 36 + { 37 + return 0; 38 + } 39 + #endif
+1 -1
arch/arm/plat-omap/include/plat/omap44xx.h
··· 32 32 #define OMAP4430_PRM_BASE 0x4a306000 33 33 #define OMAP44XX_GPMC_BASE 0x50000000 34 34 #define OMAP443X_SCM_BASE 0x4a002000 35 - #define OMAP443X_CTRL_BASE OMAP443X_SCM_BASE 35 + #define OMAP443X_CTRL_BASE 0x4a100000 36 36 #define OMAP44XX_IC_BASE 0x48200000 37 37 #define OMAP44XX_IVA_INTC_BASE 0x40000000 38 38 #define IRQ_SIR_IRQ 0x0040
+1 -1
arch/arm/plat-omap/include/plat/omap_hwmod.h
··· 294 294 u16 rev_offs; 295 295 u16 sysc_offs; 296 296 u16 syss_offs; 297 + u16 sysc_flags; 297 298 u8 idlemodes; 298 - u8 sysc_flags; 299 299 u8 clockact; 300 300 struct omap_hwmod_sysc_fields *sysc_fields; 301 301 };